July 2015 - U-Boot

[U-Boot] [PATCH 02/10] x86: Enable DM RTC support for all x86 boards
by Bin Meng 20 Jul '15

20 Jul '15

Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/galileo.dts | 1 + arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 1 + arch/x86/dts/qemu-x86_q35.dts | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 1 + 11 files changed, 11 insertions(+) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 7c7034c..ad390bf 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 4eccefd..84eae3a 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 2ba081e..d77ff8a 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -10,6 +10,7 @@ #include <dt-bindings/interrupt-router/intel-irq.h> /include/ "skeleton.dtsi" +/include/ "rtc.dtsi" / { model = "Intel Galileo"; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 0e59b18..9527233 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Intel Minnowboard Max"; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 557428a..0c522c8 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "QEMU x86 (I440FX)"; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index c259f2a..5fbabc2 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -20,6 +20,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "QEMU x86 (Q35)"; diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 9931d65..e394dab 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index b3a5f28..340510f 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 1ced47e..3f80483 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -15,5 +15,6 @@ CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 29dd44b..e98f5eb 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -21,5 +21,6 @@ CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 5639cc5..a4c20bd 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y -- 1.8.2.1

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[U-Boot] [PATCH 01/10] x86: Change pci option rom area MTRR setting to cacheable
by Bin Meng 20 Jul '15

20 Jul '15

Turn on cache on the pci option rom area to improve the performance. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/cpu.c | 27 ++++++++++++++++++++------- arch/x86/include/asm/mtrr.h | 2 ++ 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index af927b9..b4e0fd9 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -363,13 +363,26 @@ int x86_cpu_init_f(void) mtrr_cap = native_read_msr(MTRR_CAP_MSR); if (mtrr_cap & MTRR_CAP_FIX) { /* Mark the VGA RAM area as uncacheable */ - native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0); - - /* Mark the PCI ROM area as uncacheable */ - native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0); + native_write_msr(MTRR_FIX_16K_A0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + + /* + * Mark the PCI ROM area as cacheable to improve ROM + * execution performance. + */ + native_write_msr(MTRR_FIX_4K_C0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_C8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); /* Enable the fixed range MTRRs */ msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 70762ee..f9b30f6 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -55,6 +55,8 @@ #define MTRR_FIX_4K_F0000_MSR 0x26e #define MTRR_FIX_4K_F8000_MSR 0x26f +#define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t) + #if !defined(__ASSEMBLER__) /** -- 1.8.2.1

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[U-Boot] [PATCH] buildman: Correct '--fetch-arch' command documentation
by Bin Meng 20 Jul '15

20 Jul '15

The doc wrongly put sandbox in the '--fetch-arch' command. Remove it. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- tools/buildman/README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/buildman/README b/tools/buildman/README index 8ecdd8f..10c7135 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -318,7 +318,7 @@ settings file to find them. To make this easier, buildman can automatically download and install toolchains from kernel.org. First list the available architectures: -$ ./tools/buildman/buildman sandbox --fetch-arch list +$ ./tools/buildman/buildman --fetch-arch list Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/ @@ -329,7 +329,7 @@ sparc sparc64 tilegx x86_64 xtensa Then pick one and download it: -$ ./tools/buildman/buildman sandbox --fetch-arch or32 +$ ./tools/buildman/buildman --fetch-arch or32 Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/ -- 1.8.2.1

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[U-Boot] [PATCH v2 2/2] x86: Simplify architecture defined exception handling in irq_llsr()
by Bin Meng 20 Jul '15

20 Jul '15

Instead of using switch..case for architecture defined exceptions, simply unify the handling by printing a message of exception name, followed by registers dump then halt the CPU. With this unification, it also fixes the wrong exception numbers for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/cpu/interrupts.c | 151 ++++++++++++++-------------------------------- 1 file changed, 46 insertions(+), 105 deletions(-) diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 043a8d4..853c82f 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -32,6 +32,41 @@ DECLARE_GLOBAL_DATA_PTR; "pushl $"#x"\n" \ "jmp irq_common_entry\n" +static char *exceptions[] = { + "Divide Error", + "Debug", + "NMI Interrupt", + "Breakpoint", + "Overflow", + "BOUND Range Exceeded", + "Invalid Opcode (Undefined Opcode)", + "Device Not Avaiable (No Math Coprocessor)", + "Double Fault", + "Coprocessor Segment Overrun", + "Invalid TSS", + "Segment Not Present", + "Stack Segment Fault", + "Gerneral Protection", + "Page Fault", + "Reserved", + "x87 FPU Floating-Point Error", + "Alignment Check", + "Machine Check", + "SIMD Floating-Point Exception", + "Virtualization Exception", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved" +}; + static void dump_regs(struct irq_regs *regs) { unsigned long cs, eip, eflags; @@ -112,6 +147,13 @@ static void dump_regs(struct irq_regs *regs) } } +static void do_exception(struct irq_regs *regs) +{ + printf("%s\n", exceptions[regs->irq_id]); + dump_regs(regs); + hang(); +} + struct idt_entry { u16 base_low; u16 selector; @@ -228,111 +270,10 @@ void irq_llsr(struct irq_regs *regs) * Order Number: 253665-029US, November 2008 * Table 6-1. Exceptions and Interrupts */ - switch (regs->irq_id) { - case 0x00: - printf("Divide Error (Division by zero)\n"); - dump_regs(regs); - hang(); - break; - case 0x01: - printf("Debug Interrupt (Single step)\n"); - dump_regs(regs); - break; - case 0x02: - printf("NMI Interrupt\n"); - dump_regs(regs); - break; - case 0x03: - printf("Breakpoint\n"); - dump_regs(regs); - break; - case 0x04: - printf("Overflow\n"); - dump_regs(regs); - hang(); - break; - case 0x05: - printf("BOUND Range Exceeded\n"); - dump_regs(regs); - hang(); - break; - case 0x06: - printf("Invalid Opcode (UnDefined Opcode)\n"); - dump_regs(regs); - hang(); - break; - case 0x07: - printf("Device Not Available (No Math Coprocessor)\n"); - dump_regs(regs); - hang(); - break; - case 0x08: - printf("Double fault\n"); - dump_regs(regs); - hang(); - break; - case 0x09: - printf("Co-processor segment overrun\n"); - dump_regs(regs); - hang(); - break; - case 0x0a: - printf("Invalid TSS\n"); - dump_regs(regs); - break; - case 0x0b: - printf("Segment Not Present\n"); - dump_regs(regs); - hang(); - break; - case 0x0c: - printf("Stack Segment Fault\n"); - dump_regs(regs); - hang(); - break; - case 0x0d: - printf("General Protection\n"); - dump_regs(regs); - break; - case 0x0e: - printf("Page fault\n"); - dump_regs(regs); - hang(); - break; - case 0x0f: - printf("Floating-Point Error (Math Fault)\n"); - dump_regs(regs); - break; - case 0x10: - printf("Alignment check\n"); - dump_regs(regs); - break; - case 0x11: - printf("Machine Check\n"); - dump_regs(regs); - break; - case 0x12: - printf("SIMD Floating-Point Exception\n"); - dump_regs(regs); - break; - case 0x13: - case 0x14: - case 0x15: - case 0x16: - case 0x17: - case 0x18: - case 0x19: - case 0x1a: - case 0x1b: - case 0x1c: - case 0x1d: - case 0x1e: - case 0x1f: - printf("Reserved Exception\n"); - dump_regs(regs); - break; - - default: + if (regs->irq_id < 32) { + /* Architecture defined exception */ + do_exception(regs); + } else { /* Hardware or User IRQ */ do_irq(regs->irq_id); } -- 1.8.2.1

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[U-Boot] [PATCH v2 1/2] x86: Display correct CS/EIP/EFLAGS when there is an error code
by Bin Meng 20 Jul '15

20 Jul '15

Some exceptions cause an error code to be saved on the current stack after the EIP value. We should extract CS/EIP/EFLAGS from different position on the stack based on the exception number. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Use enum for x86 exception numbers arch/x86/cpu/interrupts.c | 29 ++++++++++++++++++++++++++++- arch/x86/include/asm/interrupt.h | 24 ++++++++++++++++++++++++ arch/x86/include/asm/ptrace.h | 16 +++++++++++++--- 3 files changed, 65 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index c777d36..043a8d4 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -34,12 +34,39 @@ DECLARE_GLOBAL_DATA_PTR; static void dump_regs(struct irq_regs *regs) { + unsigned long cs, eip, eflags; unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; unsigned long sp; + /* + * Some exceptions cause an error code to be saved on the current stack + * after the EIP value. We should extract CS/EIP/EFLAGS from different + * position on the stack based on the exception number. + */ + switch (regs->irq_id) { + case EXC_DF: + case EXC_TS: + case EXC_NP: + case EXC_SS: + case EXC_GP: + case EXC_PF: + case EXC_AC: + cs = regs->context.ctx2.xcs; + eip = regs->context.ctx2.eip; + eflags = regs->context.ctx2.eflags; + /* We should fix up the ESP due to error code */ + regs->esp += 4; + break; + default: + cs = regs->context.ctx1.xcs; + eip = regs->context.ctx1.eip; + eflags = regs->context.ctx1.eflags; + break; + } + printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n", - (u16)regs->xcs, regs->eip, regs->eflags); + (u16)cs, eip, eflags); printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n", regs->eax, regs->ebx, regs->ecx, regs->edx); diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 0a75f89..6eef4f9 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -13,6 +13,30 @@ #include <asm/types.h> +/* Architecture defined exceptions */ +enum x86_exception { + EXC_DE = 0, + EXC_DB, + EXC_NMI, + EXC_BP, + EXC_OF, + EXC_BR, + EXC_UD, + EXC_NM, + EXC_DF, + EXC_CSO, + EXC_TS, + EXC_NP, + EXC_SS, + EXC_GP, + EXC_PF, + EXC_MF = 16, + EXC_AC, + EXC_MC, + EXC_XM, + EXC_VE +}; + /* arch/x86/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index a727dbf..3849bc0 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -63,9 +63,19 @@ struct irq_regs { /* Pushed by vector handler (irq_<num>) */ long irq_id; /* Pushed by cpu in response to interrupt */ - long eip; - long xcs; - long eflags; + union { + struct { + long eip; + long xcs; + long eflags; + } ctx1; + struct { + long err; + long eip; + long xcs; + long eflags; + } ctx2; + } context; } __attribute__ ((packed)); /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -- 1.8.2.1

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[U-Boot] u-boot-with-spl.bin don't include the dtb image when enable CONFIG_OF_SEPARATE
by Wang Haikun 19 Jul '15

19 Jul '15

Hi Simon, It seems that we don't update the source image name to u-boot-dtb.bin in case of enabling CONFIG_OF_SEPARATE when generate u-boot-with-spl.bin file. ifdef CONFIG_TPL SPL_PAYLOAD := tpl/u-boot-with-tpl.bin else SPL_PAYLOAD := u-boot.bin endif OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) Best regards, Wang Haikun

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[U-Boot] [RFC] STM32F429: Change flash layout
by Antonio Borneo 19 Jul '15

19 Jul '15

STM32F429 has a peculiar arrangement for flash sector size. Starting at 0x08000000, the sectors are (total flash size is 2M): (4 x 16K) + (1 x 64K) + (7 x 128K) + (4 x 16K) + (1 x 64K) + (7 x 128K) Current U-Boot code for STM32F429 uses the following flash layout: - 0x08000000 : U-Boot (256K) - 0x08040000 : U-Boot env (8K) - 0x08042000 : DTB (8K) - 0x08044000 : Linux kernel With this layout, environment, DTB and first part of kernel are in the same sector of 128K. U-Boot command "saveenv" erases the whole sector, deleting both DTB and kernel! Splitting environment, DTB and kernel in independent flash sectors is the correct way to go, but we should avoid wasting big sectors of 128K for the tiny environment and DTB. Since the reset entry point is fixed at 0x08000000, a good solution is to use a simple SPL to jump ahead, so the initial small sectors become available for env and DTB. But the new flash layout will then look a little upside-down: - 0x08000000 : SPL (16K) - almost only a "goto 0x0800c000" - 0x08004000 : U-Boot env (16K) - 0x08008000 : DTB (16K) - 0x0800c000 : U-Boot (16K + 64K + 128K) - 0x08040000 : Linux kernel I have already run some experiment recompiling U-Boot for the new target address 0x0800c000. The SPL can be as simple as extracting the first 8 bytes from the binary of U-Boot compiled for 0x0800c000. A more complete SPL could print a welcome msg on console, check that the content at 0x0800c000 is reasonable for a U-Boot binary then either print an error msg or jump to U-Boot. Before sending patches, I would like to get confirmation that the proposed flash layout can be accepted. Any other target in U-Boot that has similar flash layout constraint? Also, does it make sense to build a full SPL when a simple dd bs=8 count=1 if=u-boot.bin of=spl/u-boot-spl.bin can already provide a working solution? Regards, Antonio

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[U-Boot] [PATCH 05/10] x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
by Bin Meng 18 Jul '15

18 Jul '15

Currently during writing MP table I/O interrupt assignment entry, we assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which however is not always the case on some platforms. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/include/asm/mpspec.h | 17 +++++++++++++++++ arch/x86/lib/mpspec.c | 23 ++++++++++++++++------- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index efa9231..ad8eba9 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -432,6 +432,23 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid, u32 mptable_finalize(struct mp_config_table *mc); /** + * mp_determine_pci_dstirq() - Determine PCI device's int pin on the I/O APIC + * + * This determines a PCI device's interrupt pin number on the I/O APIC. + * + * This can be implemented by platform codes to handle specifal cases, which + * do not conform to the normal chipset/board design where PIRQ[A-H] are mapped + * directly to I/O APIC INTPIN#16-23. + * + * @bus: bus number of the pci device + * @dev: device number of the pci device + * @func: function number of the pci device + * @pirq: PIRQ number the PCI device's interrupt pin is routed to + * @return: interrupt pin number on the I/O APIC + */ +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); + +/** * write_mp_table() - Write MP table * * This writes MP table at a given address. diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index f16fbcb..f90567c 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -269,6 +269,12 @@ static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base, return (i == entry_num) ? false : true; } +__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + /* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */ + return pirq + 16; +} + static int mptable_add_intsrc(struct mp_config_table *mc, int bus_isa, int apicid) { @@ -304,24 +310,27 @@ static int mptable_add_intsrc(struct mp_config_table *mc, for (i = 0; i < count; i++) { struct pirq_routing pr; + int bus, dev, func; + int dstirq; pr.bdf = fdt_addr_to_cpu(cell[0]); pr.pin = fdt_addr_to_cpu(cell[1]); pr.pirq = fdt_addr_to_cpu(cell[2]); + bus = PCI_BUS(pr.bdf); + dev = PCI_DEV(pr.bdf); + func = PCI_FUNC(pr.bdf); if (check_dup_entry(intsrc_base, intsrc_entries, - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin)) { + bus, dev, pr.pin)) { debug("found entry for bus %d device %d INT%c, skipping\n", - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), - 'A' + pr.pin - 1); + bus, dev, 'A' + pr.pin - 1); cell += sizeof(struct pirq_routing) / sizeof(u32); continue; } - /* PIRQ[A-H] are always connected to I/O APIC INTPIN#16-23 */ - mp_write_pci_intsrc(mc, MP_INT, PCI_BUS(pr.bdf), - PCI_DEV(pr.bdf), pr.pin, apicid, - pr.pirq + 16); + dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); + mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin, + apicid, dstirq); intsrc_entries++; cell += sizeof(struct pirq_routing) / sizeof(u32); } -- 1.8.2.1

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[U-Boot] [PATCH 0/6] x86: dm: pci: Convert to DM PCI on Intel Crown Bay
by Bin Meng 18 Jul '15

18 Jul '15

The existing driver model pci codes have several bugs when it comes to a pci topology with more than 2 pci bridges, which is unfortunately the case on the Intel Queensbay/Topcliff chipset. With those fixes, now U-Boot can boot on the Intel Crown Bay board with driver model pci enabled. Testing shows that 'pci' command could discover all pci devices with their configuration space configured correctly. So does the 'dm tree' command. Bin Meng (6): Fix incorrect comments in linker_lists.h dm: pci: Correct primary/secondary/subordinate bus number assignment dm: pci: Use complete bdf in all pci config read/write routines dm: pci: Pass only device/function to pci_bus_find_devfn() dm: pci: Support bridge device configuration correctly x86: Convert to use driver model pci on queensbay/crownbay arch/x86/cpu/queensbay/Makefile | 1 - arch/x86/cpu/queensbay/tnc.c | 5 --- arch/x86/cpu/queensbay/tnc_pci.c | 46 ------------------------ arch/x86/dts/crownbay.dts | 6 +++- configs/crownbay_defconfig | 1 + drivers/pci/pci-uclass.c | 54 ++++++++++++++--------------- drivers/pci/pci_auto.c | 75 +++++++++++++++++++++++++++++++++------- drivers/pci/pci_common.c | 7 +++- include/linker_lists.h | 20 +++++------ 9 files changed, 110 insertions(+), 105 deletions(-) delete mode 100644 arch/x86/cpu/queensbay/tnc_pci.c -- 1.8.2.1

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[U-Boot] [PATCH 08/10] x86: qemu: Add MP initialization
by Bin Meng 18 Jul '15

18 Jul '15

The existing MP initialization process works on QEMU multicore, except that we need increase delay time for BSP to wait APs to show up online. Use a Kconfig option to control the delay time factor to the normal one. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/mp_init.c | 4 ++++ arch/x86/cpu/qemu/Kconfig | 11 +++++++++++ arch/x86/dts/qemu-x86_i440fx.dts | 20 ++++++++++++++++++++ arch/x86/dts/qemu-x86_q35.dts | 20 ++++++++++++++++++++ configs/qemu-x86_defconfig | 4 ++++ doc/README.x86 | 5 +++++ 6 files changed, 64 insertions(+) diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index e686b28..f87201b 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -75,6 +75,10 @@ static int wait_for_aps(atomic_t *val, int target, int total_delay, int timeout = 0; int delayed = 0; +#ifdef CONFIG_QEMU + total_delay *= CONFIG_MPINIT_DELAY_FACTOR; +#endif + while (atomic_read(val) != target) { udelay(delay_step); delayed += delay_step; diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index fb775d7..a690060 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -18,4 +18,15 @@ config SYS_CAR_SIZE hex default 0x10000 +config MPINIT_DELAY_FACTOR + int "QEMU multicore initialization delay factor" + depends on SMP + default 100 + help + During multicore initialization after BSP sends SIPI to wake up APs, + U-Boot needs to wait some time for AP to show up online. The delay + time is good for real hardware, but seems not enough for QEMU. The + value of this option will be used as the multiplier to the normal + delay time. + endif diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 0c522c8..e3c6fc3 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -24,6 +24,26 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <1>; + }; + + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 5fbabc2..0305864 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -35,6 +35,26 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <1>; + }; + + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a4c20bd..62c3f35 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -1,6 +1,9 @@ CONFIG_X86=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" +CONFIG_SMP=y +CONFIG_MAX_CPUS=2 CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -9,6 +12,7 @@ CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y +CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/doc/README.x86 b/doc/README.x86 index 5d71244..1cab42c 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -281,6 +281,11 @@ QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will show QEMU's VGA console window. Note this will disable QEMU's serial output. If you want to check both consoles, use '-serial stdio'. +Multicore is also supported by QEMU via '-smp n' where n is the number of cores +to instantiate. Currently the default U-Boot built for QEMU supports 2 cores. +In order to support more cores, you need add additional cpu nodes in the device +tree and change CONFIG_MAX_CPUS accordingly. + CPU Microcode ------------- Modern CPUs usually require a special bit stream called microcode [8] to be -- 1.8.2.1

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