March 2015 - U-Boot

[U-Boot] [PATCH] sf: Poll both the read status and flag status
by Siva Durga Prasad Paladugu 17 Apr '15

17 Apr '15

Poll both the Read status and Flag status registers for sucessful erase and program operations for the Micron devices with E_FSR flag set in params table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/mtd/spi/sf_ops.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 34bc54e..38592f5 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -154,21 +154,17 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) } #endif -int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout, + u8 cmd, u8 poll_bit) { - struct spi_slave *spi = flash->spi; unsigned long timebase; unsigned long flags = SPI_XFER_BEGIN; int ret; u8 status; u8 check_status = 0x0; - u8 poll_bit = STATUS_WIP; - u8 cmd = flash->poll_cmd; - if (cmd == CMD_FLAG_STATUS) { - poll_bit = STATUS_PEC; + if (cmd == CMD_FLAG_STATUS) check_status = poll_bit; - } #ifdef CONFIG_SF_DUAL_FLASH if (spi->flags & SPI_XFER_U_PAGE) @@ -204,6 +200,28 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) return -1; } +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + int ret; + u8 poll_bit = STATUS_WIP; + u8 cmd = CMD_READ_STATUS; + + ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit); + if (ret < 0) + return ret; + + if (flash->poll_cmd == CMD_FLAG_STATUS) { + poll_bit = STATUS_PEC; + cmd = CMD_FLAG_STATUS; + ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit); + if (ret < 0) + return ret; + } + + return 0; +} + int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, size_t cmd_len, const void *buf, size_t buf_len) { -- 2.1.1

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[U-Boot] [PATCH] sf: Correct the macros as per new array fast read command
by Siva Durga Prasad Paladugu 17 Apr '15

17 Apr '15

Correct the macros as per insertion of array fast read command CMD_READ_ARRAY_FAST in spi_read_cmds_array in file sf_probe.c Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- include/spi.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/include/spi.h b/include/spi.h index c58e453..7829063 100644 --- a/include/spi.h +++ b/include/spi.h @@ -38,11 +38,12 @@ /* SPI RX operation modes */ #define SPI_OPM_RX_AS (1 << 0) -#define SPI_OPM_RX_DOUT (1 << 1) -#define SPI_OPM_RX_DIO (1 << 2) -#define SPI_OPM_RX_QOF (1 << 3) -#define SPI_OPM_RX_QIOF (1 << 4) -#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ +#define SPI_OPM_RX_AF (1 << 1) +#define SPI_OPM_RX_DOUT (1 << 2) +#define SPI_OPM_RX_DIO (1 << 3) +#define SPI_OPM_RX_QOF (1 << 4) +#define SPI_OPM_RX_QIOF (1 << 5) +#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ SPI_OPM_RX_QIOF) -- 2.1.1

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[U-Boot] [PATCH 1/4] mmc: fsl_esdhc: Add adapter card type identification support
by Yangbo Lu 16 Apr '15

16 Apr '15

Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- arch/powerpc/include/asm/global_data.h | 3 +++ board/freescale/common/qixis.h | 14 +++++++++++++ drivers/mmc/fsl_esdhc.c | 38 +++++++++++++++++++++++++++++++++- drivers/mmc/mmc.c | 6 ++++++ drivers/mmc/mmc_private.h | 3 +++ include/fsl_esdhc.h | 4 ++++ 6 files changed, 67 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index c57d9c0..4090975 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -15,6 +15,9 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; +#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT) + u8 sdhc_adapter; +#endif #endif #if defined(CONFIG_8xx) unsigned long brg_clk; diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 52d2021..51ce9c3 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -115,4 +115,18 @@ void qixis_write_i2c(unsigned int reg, u8 value); qixis_write_i2c(offsetof(struct qixis, reg), value) #endif +/* Use for SDHC adapter card type identification and operation */ +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */ +#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */ +#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */ +#define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */ +#define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */ +#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */ +#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ +#define QIXIS_SDCLKIN 0x08 +#define QIXIS_SDCLKOUT 0x02 +#endif + #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f5d2ccb..355cada 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -643,6 +643,39 @@ int fsl_esdhc_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, cfg); } +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +void mmc_adapter_card_type_ident(void) +{ + u8 card_id; + u8 value; + + card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; + gd->arch.sdhc_adapter = card_id; + + switch (card_id) { + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); + QIXIS_WRITE(brdcfg[5], value); + break; + case QIXIS_ESDHC_ADAPTER_TYPE_RSV: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_MMC: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_SD: + break; + case QIXIS_ESDHC_NO_ADAPTER: + break; + default: + break; + } +} +#endif + #ifdef CONFIG_OF_LIBFDT void fdt_fixup_esdhc(void *blob, bd_t *bd) { @@ -658,7 +691,10 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, compat, "clock-frequency", gd->arch.sdhc_clk, 1); - +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + do_fixup_by_compat_u32(blob, compat, "adapter-type", + (u32)(gd->arch.sdhc_adapter), 1); +#endif do_fixup_by_compat(blob, compat, "status", "okay", 4 + 1, 1); } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a13769e..dc32aec 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1588,6 +1588,9 @@ int mmc_start_init(struct mmc *mmc) if (mmc->has_init) return 0; +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + mmc_adapter_card_type_ident(); +#endif board_mmc_power_init(); /* made sure it's not NULL earlier */ @@ -1739,6 +1742,9 @@ static void do_preinit(void) list_for_each(entry, &mmc_devices) { m = list_entry(entry, struct mmc, link); +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + mmc_set_preinit(m, 1); +#endif if (m->preinit) mmc_start_init(m); } diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 16dcf9f..447a700 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -16,6 +16,9 @@ extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); extern int mmc_send_status(struct mmc *mmc, int timeout); extern int mmc_set_blocklen(struct mmc *mmc, int len); +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +void mmc_adapter_card_type_ident(void); +#endif #ifndef CONFIG_SPL_BUILD diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 313fa1e..5462b4c 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -16,6 +16,10 @@ /* needed for the mmc_cfg definition */ #include <mmc.h> +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +#include "../board/freescale/common/qixis.h" +#endif + /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/1] ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
by Bryan Brinsko 16 Apr '15

16 Apr '15

The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko(a)rockwellcollins.com> --- arch/arm/include/asm/system.h | 37 +++++++++++++++++++++++++++++++++++++ arch/arm/lib/cache-cp15.c | 14 ++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2a5bed2..9cd2f1e 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -196,6 +196,28 @@ static inline void set_dacr(unsigned int val) isb(); } +#ifdef CONFIG_ARMV7 +/* Short-Descriptor Translation Table Level 1 Bits */ +#define TTB_SECT_NS_MASK (1 << 19) +#define TTB_SECT_NG_MASK (1 << 17) +#define TTB_SECT_S_MASK (1 << 16) +/* Note: TTB AP bits are set elsewhere */ +#define TTB_SECT_TEX(x) ((x & 0x7) << 12) +#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) +#define TTB_SECT_XN_MASK (1 << 4) +#define TTB_SECT_C_MASK (1 << 3) +#define TTB_SECT_B_MASK (1 << 2) +#define TTB_SECT (2 << 0) + +/* options available for data cache on each page */ +enum dcache_option { + DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | + TTB_SECT_XN_MASK | TTB_SECT, + DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, + DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, + DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), +}; +#else /* options available for data cache on each page */ enum dcache_option { DCACHE_OFF = 0x12, @@ -203,6 +225,7 @@ enum dcache_option { DCACHE_WRITEBACK = 0x1e, DCACHE_WRITEALLOC = 0x16, }; +#endif /* Size of an MMU section */ enum { @@ -210,6 +233,20 @@ enum { MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, }; +#ifdef CONFIG_ARMV7 +/* TTBR0 bits */ +#define TTBR0_BASE_ADDR_MASK 0xFFFFC000 +#define TTBR0_RGN_NC (0 << 3) +#define TTBR0_RGN_WBWA (1 << 3) +#define TTBR0_RGN_WT (2 << 3) +#define TTBR0_RGN_WB (3 << 3) +/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ +#define TTBR0_IRGN_NC (0 << 0 | 0 << 6) +#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) +#define TTBR0_IRGN_WT (1 << 0 | 0 << 6) +#define TTBR0_IRGN_WB (1 << 0 | 1 << 6) +#endif + /** * Change the cache settings for a region. * diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0291afa..c65e068 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -96,9 +96,23 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } +#ifdef CONFIG_ARMV7 + /* Set TTBR0 */ + reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT; +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA; +#else + reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB; +#endif + asm volatile("mcr p15, 0, %0, c2, c0, 0" + : : "r" (reg) : "memory"); +#else /* Copy the page table address to cp15 */ asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (gd->arch.tlb_addr) : "memory"); +#endif /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); -- 1.9.1

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[U-Boot] [PATCH 1/2] fix ARM DCC support for ARMv7 based cores (e.g. CortexA)
by Alexander Merkle 16 Apr '15

16 Apr '15

fix arm_dcc.c implementation for ARMv7 based cores. remove now obsolete workaround for ZYNQ Alexander Merkle (2): fix ARM DCC support for ARMv7 based cores (e.g. CortexA) fix ARM DCC support for ARMv7 based cores (e.g. CortexA) drivers/serial/arm_dcc.c | 4 ++-- include/configs/zynq-common.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.1.4

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[U-Boot] [PATCH] Armv8: Initializing CNTVOFF_EL2
by fenghua＠phytium.com.cn 16 Apr '15

16 Apr '15

From: David Feng <fenghua(a)phytium.com.cn> Linux-arm64 require that CNTVOFF_EL2 should be programmed with a consistent value on all cpus. Initializing CNTVOFF_EL2 at state transition instead of start.S could prevent potential different value on cpus if ATF exist and u-boot runs at only one cpu. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- arch/arm/include/asm/macro.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 1c8c425..39df86a 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -113,6 +113,9 @@ lr .req x30 mov \xreg1, #0x33ff msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */ + /* Initialize Generic Timers */ + msr cntvoff_el2, xzr + /* Initialize SCTLR_EL2 * * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1 -- 1.7.9.5

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[U-Boot] [PATCH] arm: implement find_next_zero_bit function
by Vitaly Andrianov 16 Apr '15

16 Apr '15

This commit copies implementation of the find_next_zero_bit() from git://git.denx.de/u-boot.git/arch/mips/include/asm/bitops.h. v2014.07 The function is required to enable MCAST_TFTP support for ARM platforms. Signed-off-by: Vitaly Andrianov <vitalya(a)ti.com> --- arch/arm/include/asm/bitops.h | 43 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 597dafb..9b78043 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -95,9 +95,6 @@ static inline int __test_and_change_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit(void * addr, int size, int offset); - /* * This routine doesn't need to be atomic. */ @@ -129,6 +126,43 @@ static inline unsigned long ffz(unsigned long word) return k; } +static inline int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *)addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + tmp = *(p++); + if (~tmp) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL >> size; +found_middle: + return result + ffz(tmp); +} + /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word @@ -138,6 +172,9 @@ static inline unsigned long ffz(unsigned long word) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + #define ext2_set_bit test_and_set_bit #define ext2_clear_bit test_and_clear_bit #define ext2_test_bit test_bit -- 1.9.1

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[U-Boot] [UBOOT PATCH] f_thor: Dont perform reset at the end of thor
by Siva Durga Prasad Paladugu 15 Apr '15

15 Apr '15

Dont perform reset at the end of thor download if configured to do reset off. Reset may not be required in all cases and hence provided an option to do so. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/usb/gadget/f_thor.c | 7 +++++++ drivers/usb/gadget/f_thor.h | 3 +++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c85b0fb..8cf0718 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -123,6 +123,9 @@ static int process_rqt_cmd(const struct rqt_box *rqt) send_rsp(rsp); g_dnl_unregister(); dfu_free_entities(); +#ifdef CONFIG_THOR_RESET_OFF + return RESET_DONE; +#endif run_command("reset", 0); break; case RQT_CMD_POWEROFF: @@ -726,6 +729,10 @@ int thor_handle(void) if (ret > 0) { ret = process_data(); +#ifdef CONFIG_THOR_RESET_OFF + if (ret == RESET_DONE) + break; +#endif if (ret < 0) return ret; } else { diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h index 833a9d2..8341285 100644 --- a/drivers/usb/gadget/f_thor.h +++ b/drivers/usb/gadget/f_thor.h @@ -121,4 +121,7 @@ struct f_thor { #define F_NAME_BUF_SIZE 32 #define THOR_PACKET_SIZE SZ_1M /* 1 MiB */ #define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */ +#ifdef CONFIG_THOR_RESET_OFF +#define RESET_DONE 0xFFFFFFFF +#endif #endif /* _USB_THOR_H_ */ -- 1.7.4

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[U-Boot] [UBOOT PATCH] usb: gadget: f_thor: Allocate request up to THOR_PACKET_SIZE
by Siva Durga Prasad Paladugu 15 Apr '15

15 Apr '15

Allocate request up to THOR_PACKET_SIZE not the ep0->maxpacket as the descriptors data depend on the number of descriptors and this 64 bytes were not enough and the buffer might overflow which results in memalign failures later. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/usb/gadget/f_thor.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c85b0fb..98d2d8c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -766,7 +766,7 @@ static int thor_func_bind(struct usb_configuration *c, struct usb_function *f) goto fail; } dev->req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, - gadget->ep0->maxpacket); + THOR_PACKET_SIZE); if (!dev->req->buf) { status = -ENOMEM; goto fail; -- 1.7.4

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[U-Boot] [PATCH 0/2] ARMv8: driver model enable
by fenghua＠phytium.com.cn 15 Apr '15

15 Apr '15

From: David Feng <fenghua(a)phytium.com.cn> Currently serial_pl01x.c driver contain DM and non-DM mode, but it will access static varible in non-DM mode. So, u-boot using non-DM pl01x driver can not be placed in flash. This patch set enable pre-allocation malloc that is required by DM and enable DM in vexpress64 board. David Feng (2): ARMv8: enable pre-allocation malloc ARMv8: enable DM in vexpress64 board arch/arm/include/asm/config.h | 4 ---- arch/arm/lib/crt0_64.S | 13 +++++++++++-- board/armltd/vexpress64/vexpress64.c | 13 +++++++++++++ include/configs/vexpress_aemv8a.h | 14 ++++++++++++-- 4 files changed, 36 insertions(+), 8 deletions(-) -- 1.7.9.5

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