January 2015 - U-Boot

[U-Boot] [PATCH] spl: Change printf to puts for "Unsupported boot-device"
by Stefan Roese 29 Jan '15

29 Jan '15

Microblaze currently doesn't use printf in SPL. So this one line was the only reference to it and resulted in the printf functionality to be pulled in. Exceeding the 4k size limit. Lets change the printf back to puts so that Microblaze is fixed again. The only drawback is that the detected boot-device number will not be printed. But this message alone should be helpful enough to get an idea where the boot process is broken. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Michal Simek <michal.simek(a)xilinx.com> --- common/spl/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index 1826c47..daaeb50 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -231,7 +231,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) #endif default: #if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - printf("SPL: Unsupported Boot Device %d\n", boot_device); + puts("SPL: Unsupported Boot Device!\n"); #endif hang(); } -- 2.2.2

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[U-Boot] [PATCH] Makefile: clean boot.bin
by Bo Shen 29 Jan '15

29 Jan '15

When build for Atmel related boards which support SPL, it will generate boot.bin, also clean when it when do "make clean" operation. Signed-off-by: Bo Shen <voice.shen(a)atmel.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 36a9a28..ea5ae8f 100644 --- a/Makefile +++ b/Makefile @@ -1278,7 +1278,7 @@ CLEAN_DIRS += $(MODVERDIR) \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ - u-boot* MLO* SPL System.map + boot* u-boot* MLO* SPL System.map # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl \ -- 2.3.0.rc0

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[U-Boot] [PATCH] MIPS: unify CPU code in arch/mips/cpu/
by Daniel Schwierzeck 29 Jan '15

29 Jan '15

Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/. The CPU specific config.mk files need to remain until CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol. Signed-off-by: Paul Burton <paul.burton(a)imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/Makefile | 6 +- arch/mips/cpu/Makefile | 9 ++ arch/mips/cpu/cpu.c | 38 +++++ arch/mips/cpu/interrupts.c | 22 +++ arch/mips/cpu/mips32/Makefile | 9 -- arch/mips/cpu/mips32/cpu.c | 34 ---- arch/mips/cpu/mips32/interrupts.c | 22 --- arch/mips/cpu/mips32/start.S | 320 -------------------------------------- arch/mips/cpu/mips32/time.c | 19 --- arch/mips/cpu/mips64/Makefile | 9 -- arch/mips/cpu/mips64/cpu.c | 37 ----- arch/mips/cpu/mips64/interrupts.c | 22 --- arch/mips/cpu/mips64/start.S | 291 ---------------------------------- arch/mips/cpu/mips64/time.c | 19 --- arch/mips/cpu/start.S | 320 ++++++++++++++++++++++++++++++++++++++ arch/mips/cpu/time.c | 19 +++ 16 files changed, 410 insertions(+), 786 deletions(-) create mode 100644 arch/mips/cpu/Makefile create mode 100644 arch/mips/cpu/cpu.c create mode 100644 arch/mips/cpu/interrupts.c delete mode 100644 arch/mips/cpu/mips32/Makefile delete mode 100644 arch/mips/cpu/mips32/cpu.c delete mode 100644 arch/mips/cpu/mips32/interrupts.c delete mode 100644 arch/mips/cpu/mips32/start.S delete mode 100644 arch/mips/cpu/mips32/time.c delete mode 100644 arch/mips/cpu/mips64/Makefile delete mode 100644 arch/mips/cpu/mips64/cpu.c delete mode 100644 arch/mips/cpu/mips64/interrupts.c delete mode 100644 arch/mips/cpu/mips64/start.S delete mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 arch/mips/cpu/start.S create mode 100644 arch/mips/cpu/time.c diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ff01bfe..43f0f5c 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -2,11 +2,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -head-$(CONFIG_CPU_MIPS32) := arch/mips/cpu/mips32/start.o -head-$(CONFIG_CPU_MIPS64) := arch/mips/cpu/mips64/start.o +head-y := arch/mips/cpu/start.o -libs-$(CONFIG_CPU_MIPS32) += arch/mips/cpu/mips32/ -libs-$(CONFIG_CPU_MIPS64) += arch/mips/cpu/mips64/ +libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile new file mode 100644 index 0000000..fc6b455 --- /dev/null +++ b/arch/mips/cpu/Makefile @@ -0,0 +1,9 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y = start.o + +obj-y += time.o +obj-y += interrupts.o +obj-y += cpu.o diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c new file mode 100644 index 0000000..8d3b2f5 --- /dev/null +++ b/arch/mips/cpu/cpu.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mipsregs.h> +#include <asm/reboot.h> + +void __weak _machine_restart(void) +{ + fprintf(stderr, "*** reset failed ***\n"); + + while (1) + /* NOP */; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + _machine_restart(); + + return 0; +} + +void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) +{ + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); + tlb_write_indexed(); +} diff --git a/arch/mips/cpu/interrupts.c b/arch/mips/cpu/interrupts.c new file mode 100644 index 0000000..275fcf5 --- /dev/null +++ b/arch/mips/cpu/interrupts.c @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +int interrupt_init(void) +{ + return 0; +} + +void enable_interrupts(void) +{ +} + +int disable_interrupts(void) +{ + return 0; +} diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile deleted file mode 100644 index cb4db9c..0000000 --- a/arch/mips/cpu/mips32/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cpu.o interrupts.o time.o diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c deleted file mode 100644 index 07deca8..0000000 --- a/arch/mips/cpu/mips32/cpu.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <asm/mipsregs.h> -#include <asm/reboot.h> - -void __attribute__((weak)) _machine_restart(void) -{ -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - fprintf(stderr, "*** reset failed ***\n"); - return 0; -} - -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); - tlb_write_indexed(); -} diff --git a/arch/mips/cpu/mips32/interrupts.c b/arch/mips/cpu/mips32/interrupts.c deleted file mode 100644 index 275fcf5..0000000 --- a/arch/mips/cpu/mips32/interrupts.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -int interrupt_init(void) -{ - return 0; -} - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S deleted file mode 100644 index 3b5b622..0000000 --- a/arch/mips/cpu/mips32/start.S +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Startup Code for MIPS32 CPU-core - * - * Copyright (c) 2003 Wolfgang Denk <wd(a)denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <asm/asm.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> - -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) -#endif - -#ifdef CONFIG_32BIT -# define MIPS_RELOC 3 -# define STATUS_SET 0 -#endif - -#ifdef CONFIG_64BIT -# ifdef CONFIG_SYS_LITTLE_ENDIAN -# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) -# else -# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) -# endif -# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) -# define STATUS_SET ST0_KX -#endif - - /* - * For the moment disable interrupts, mark the kernel mode and - * set ST0_KX so that the CPU does not spit fire when using - * 64-bit addresses. - */ - .macro setup_c0_status set clr - .set push - mfc0 t0, CP0_STATUS - or t0, ST0_CU0 | \set | 0x1f | \clr - xor t0, 0x1f | \clr - mtc0 t0, CP0_STATUS - .set noreorder - sll zero, 3 # ehb - .set pop - .endm - - .set noreorder - - .globl _start - .text -_start: - /* U-boot entry point */ - b reset - nop - - .org 0x10 -#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) - /* - * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to - * access external NOR flashes. If the board boots from NOR flash the - * internal BootROM does a blind read at address 0xB0000010 to read the - * initial configuration for that EBU in order to access the flash - * device with correct parameters. This config option is board-specific. - */ - .word CONFIG_SYS_XWAY_EBU_BOOTCFG - .word 0x0 -#elif defined(CONFIG_MALTA) - /* - * Linux expects the Board ID here. - */ - .word 0x00000420 # 0x420 (Malta Board with CoreLV) - .word 0x00000000 -#endif - - .org 0x200 - /* TLB refill, 32 bit task */ -1: b 1b - nop - - .org 0x280 - /* XTLB refill, 64 bit task */ -1: b 1b - nop - - .org 0x300 - /* Cache error exception */ -1: b 1b - nop - - .org 0x380 - /* General exception */ -1: b 1b - nop - - .org 0x400 - /* Catch interrupt exceptions */ -1: b 1b - nop - - .org 0x480 - /* EJTAG debug exception */ -1: b 1b - nop - - .align 4 -reset: - - /* Clear watch registers */ - MTC0 zero, CP0_WATCHLO - MTC0 zero, CP0_WATCHHI - - /* WP(Watch Pending), SW0/1 should be cleared */ - mtc0 zero, CP0_CAUSE - - setup_c0_status STATUS_SET 0 - - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - li t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG -#endif - - /* - * Initialize $gp, force pointer sized alignment of bal instruction to - * forbid the compiler to put nop's between bal and _gp. This is - * required to keep _gp and ra aligned to 8 byte. - */ - .align PTRLOG - bal 1f - nop - PTR _gp -1: - PTR_L gp, 0(ra) - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* Initialize any external memory */ - PTR_LA t9, lowlevel_init - jalr t9 - nop - - /* Initialize caches... */ - PTR_LA t9, mips_cache_reset - jalr t9 - nop - - /* ... and enable them */ - li t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG -#endif - - /* Set up temporary stack */ - PTR_LI t0, -16 - PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR - and sp, t1, t0 # force 16 byte alignment - PTR_SUB sp, sp, GD_SIZE # reserve space for gd - and sp, sp, t0 # force 16 byte alignment - move k0, sp # save gd pointer -#ifdef CONFIG_SYS_MALLOC_F_LEN - PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN - PTR_SUB sp, sp, t2 # reserve space for early malloc - and sp, sp, t0 # force 16 byte alignment -#endif - move fp, sp - - /* Clear gd */ - move t0, k0 -1: - sw zero, 0(t0) - blt t0, t1, 1b - PTR_ADDI t0, 4 - -#ifdef CONFIG_SYS_MALLOC_F_LEN - PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset - sw sp, 0(t0) -#endif - - PTR_LA t9, board_init_f - jr t9 - move ra, zero - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - move fp, sp - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - PTR_LI t0, CONFIG_SYS_MONITOR_BASE - PTR_SUB s1, s2, t0 # s1 <-- relocation offset - - PTR_LA t3, in_ram - PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end - move t1, a2 - - PTR_ADD gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - PTR_ADDU t0, 4 - blt t0, t2, 1b - PTR_ADDU t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - PTR_SUB a1, t1, s2 # a1 <-- size - PTR_LA t9, flush_cache - jalr t9 - move a0, s2 # a0 <-- destination address - - /* Jump to where we've relocated ourselves */ - PTR_ADDI t0, s2, in_ram - _start - jr t0 - nop - - PTR __rel_dyn_end - PTR __rel_dyn_start - PTR __image_copy_end - PTR _GLOBAL_OFFSET_TABLE_ - PTR num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries - PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_ - PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries - PTR_LI t2, 2 -1: - PTR_L t1, 0(t8) - beqz t1, 2f - PTR_ADD t1, s1 - PTR_S t1, 0(t8) -2: - PTR_ADDI t2, 1 - blt t2, t3, 1b - PTR_ADDI t8, PTRSIZE - - /* Update dynamic relocations */ - PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start - PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - PTR_ADDI t1, 2 * PTRSIZE - -1: - lw t8, -4(t1) # t8 <-- relocation info - - PTR_LI t3, MIPS_RELOC - bne t8, t3, 2f # skip non-MIPS_RELOC entries - nop - - PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH - - PTR_L t8, 0(t3) # t8 <-- original pointer - PTR_ADD t8, s1 # t8 <-- adjusted pointer - - PTR_ADD t3, s1 # t3 <-- location to fix up in RAM - PTR_S t8, 0(t3) - -2: - blt t1, t2, 1b - PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - PTR_LA t1, __bss_start # t1 <-- __bss_start - PTR_LA t2, __bss_end # t2 <-- __bss_end - -1: - PTR_S zero, 0(t1) - blt t1, t2, 1b - PTR_ADDI t1, PTRSIZE - - move a0, s0 # a0 <-- gd - move a1, s2 - PTR_LA t9, board_init_r - jr t9 - move ra, zero - - .end relocate_code diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c deleted file mode 100644 index 553da5f..0000000 --- a/arch/mips/cpu/mips32/time.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mipsregs.h> - -unsigned long notrace timer_read_counter(void) -{ - return read_c0_count(); -} - -ulong notrace get_tbclk(void) -{ - return CONFIG_SYS_MIPS_TIMER_FREQ; -} diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile deleted file mode 100644 index cb4db9c..0000000 --- a/arch/mips/cpu/mips64/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cpu.o interrupts.o time.o diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c deleted file mode 100644 index 1d32705..0000000 --- a/arch/mips/cpu/mips64/cpu.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <asm/mipsregs.h> -#include <asm/reboot.h> - -void __attribute__((weak)) _machine_restart(void) -{ - fprintf(stderr, "*** reset failed ***\n"); - - while (1) - /* NOP */; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - return 0; -} - -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); - tlb_write_indexed(); -} diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c deleted file mode 100644 index 275fcf5..0000000 --- a/arch/mips/cpu/mips64/interrupts.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -int interrupt_init(void) -{ - return 0; -} - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S deleted file mode 100644 index 471bc1e..0000000 --- a/arch/mips/cpu/mips64/start.S +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Startup Code for MIPS64 CPU-core - * - * Copyright (c) 2003 Wolfgang Denk <wd(a)denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> - -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) -#endif - -#ifdef CONFIG_SYS_LITTLE_ENDIAN -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) -#else -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) -#endif - - /* - * For the moment disable interrupts, mark the kernel mode and - * set ST0_KX so that the CPU does not spit fire when using - * 64-bit addresses. - */ - .macro setup_c0_status set clr - .set push - mfc0 t0, CP0_STATUS - or t0, ST0_CU0 | \set | 0x1f | \clr - xor t0, 0x1f | \clr - mtc0 t0, CP0_STATUS - .set noreorder - sll zero, 3 # ehb - .set pop - .endm - - .set noreorder - - .globl _start - .text -_start: - /* U-boot entry point */ - b reset - nop - - .org 0x200 - /* TLB refill, 32 bit task */ -1: b 1b - nop - - .org 0x280 - /* XTLB refill, 64 bit task */ -1: b 1b - nop - - .org 0x300 - /* Cache error exception */ -1: b 1b - nop - - .org 0x380 - /* General exception */ -1: b 1b - nop - - .org 0x400 - /* Catch interrupt exceptions */ -1: b 1b - nop - - .org 0x480 - /* EJTAG debug exception */ -1: b 1b - nop - - .align 4 -reset: - - /* Clear watch registers */ - dmtc0 zero, CP0_WATCHLO - dmtc0 zero, CP0_WATCHHI - - /* WP(Watch Pending), SW0/1 should be cleared */ - mtc0 zero, CP0_CAUSE - - setup_c0_status ST0_KX 0 - - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - dli t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG -#endif - - /* - * Initialize $gp, force 8 byte alignment of bal instruction to forbid - * the compiler to put nop's between bal and _gp. This is required to - * keep _gp and ra aligned to 8 byte. - */ - .align 3 - bal 1f - nop - .dword _gp -1: - ld gp, 0(ra) - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* Initialize any external memory */ - dla t9, lowlevel_init - jalr t9 - nop - - /* Initialize caches... */ - dla t9, mips_cache_reset - jalr t9 - nop - - /* ... and enable them */ - dli t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG -#endif - - /* Set up temporary stack */ - dli t0, -16 - dli t1, CONFIG_SYS_INIT_SP_ADDR - and sp, t1, t0 # force 16 byte alignment - dsub sp, sp, GD_SIZE # reserve space for gd - and sp, sp, t0 # force 16 byte alignment - move k0, sp # save gd pointer -#ifdef CONFIG_SYS_MALLOC_F_LEN - dli t2, CONFIG_SYS_MALLOC_F_LEN - dsub sp, sp, t2 # reserve space for early malloc - and sp, sp, t0 # force 16 byte alignment -#endif - move fp, sp - - /* Clear gd */ - move t0, k0 -1: - sw zero, 0(t0) - blt t0, t1, 1b - daddi t0, 4 - -#ifdef CONFIG_SYS_MALLOC_F_LEN - daddu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset - sw sp, 0(t0) -#endif - - dla t9, board_init_f - jr t9 - move ra, zero - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - move fp, sp - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - dli t0, CONFIG_SYS_MONITOR_BASE - dsub s1, s2, t0 # s1 <-- relocation offset - - dla t3, in_ram - ld t2, -24(t3) # t2 <-- __image_copy_end - move t1, a2 - - dadd gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - daddu t0, 4 - blt t0, t2, 1b - daddu t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - dsub a1, t1, s2 # a1 <-- size - dla t9, flush_cache - jalr t9 - move a0, s2 # a0 <-- destination address - - /* Jump to where we've relocated ourselves */ - daddi t0, s2, in_ram - _start - jr t0 - nop - - .dword __rel_dyn_end - .dword __rel_dyn_start - .dword __image_copy_end - .dword _GLOBAL_OFFSET_TABLE_ - .dword num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - ld t3, -8(t0) # t3 <-- num_got_entries - ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - dadd t8, s1 # t8 now holds relocated _G_O_T_ - daddi t8, t8, 16 # skipping first two entries - dli t2, 2 -1: - ld t1, 0(t8) - beqz t1, 2f - dadd t1, s1 - sd t1, 0(t8) -2: - daddi t2, 1 - blt t2, t3, 1b - daddi t8, 8 - - /* Update dynamic relocations */ - ld t1, -32(t0) # t1 <-- __rel_dyn_start - ld t2, -40(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - daddi t1, 16 - -1: - lw t8, -4(t1) # t8 <-- relocation info - - dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) - bne t8, t3, 2f # skip non R_MIPS_REL32 entries - nop - - ld t3, -16(t1) # t3 <-- location to fix up in FLASH - - ld t8, 0(t3) # t8 <-- original pointer - dadd t8, s1 # t8 <-- adjusted pointer - - dadd t3, s1 # t3 <-- location to fix up in RAM - sd t8, 0(t3) - -2: - blt t1, t2, 1b - daddi t1, 16 # each rel.dyn entry is 16 bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - dla t1, __bss_start # t1 <-- __bss_start - dla t2, __bss_end # t2 <-- __bss_end - -1: - sd zero, 0(t1) - blt t1, t2, 1b - daddi t1, 8 - - move a0, s0 # a0 <-- gd - move a1, s2 - dla t9, board_init_r - jr t9 - move ra, zero - - .end relocate_code diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c deleted file mode 100644 index 553da5f..0000000 --- a/arch/mips/cpu/mips64/time.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mipsregs.h> - -unsigned long notrace timer_read_counter(void) -{ - return read_c0_count(); -} - -ulong notrace get_tbclk(void) -{ - return CONFIG_SYS_MIPS_TIMER_FREQ; -} diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S new file mode 100644 index 0000000..3b5b622 --- /dev/null +++ b/arch/mips/cpu/start.S @@ -0,0 +1,320 @@ +/* + * Startup Code for MIPS32 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk <wd(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + +#ifndef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_SP_OFFSET) +#endif + +#ifdef CONFIG_32BIT +# define MIPS_RELOC 3 +# define STATUS_SET 0 +#endif + +#ifdef CONFIG_64BIT +# ifdef CONFIG_SYS_LITTLE_ENDIAN +# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ + (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) +# else +# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ + ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) +# endif +# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) +# define STATUS_SET ST0_KX +#endif + + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .set noreorder + + .globl _start + .text +_start: + /* U-boot entry point */ + b reset + nop + + .org 0x10 +#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) + /* + * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to + * access external NOR flashes. If the board boots from NOR flash the + * internal BootROM does a blind read at address 0xB0000010 to read the + * initial configuration for that EBU in order to access the flash + * device with correct parameters. This config option is board-specific. + */ + .word CONFIG_SYS_XWAY_EBU_BOOTCFG + .word 0x0 +#elif defined(CONFIG_MALTA) + /* + * Linux expects the Board ID here. + */ + .word 0x00000420 # 0x420 (Malta Board with CoreLV) + .word 0x00000000 +#endif + + .org 0x200 + /* TLB refill, 32 bit task */ +1: b 1b + nop + + .org 0x280 + /* XTLB refill, 64 bit task */ +1: b 1b + nop + + .org 0x300 + /* Cache error exception */ +1: b 1b + nop + + .org 0x380 + /* General exception */ +1: b 1b + nop + + .org 0x400 + /* Catch interrupt exceptions */ +1: b 1b + nop + + .org 0x480 + /* EJTAG debug exception */ +1: b 1b + nop + + .align 4 +reset: + + /* Clear watch registers */ + MTC0 zero, CP0_WATCHLO + MTC0 zero, CP0_WATCHHI + + /* WP(Watch Pending), SW0/1 should be cleared */ + mtc0 zero, CP0_CAUSE + + setup_c0_status STATUS_SET 0 + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG +#endif + + /* + * Initialize $gp, force pointer sized alignment of bal instruction to + * forbid the compiler to put nop's between bal and _gp. This is + * required to keep _gp and ra aligned to 8 byte. + */ + .align PTRLOG + bal 1f + nop + PTR _gp +1: + PTR_L gp, 0(ra) + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* Initialize any external memory */ + PTR_LA t9, lowlevel_init + jalr t9 + nop + + /* Initialize caches... */ + PTR_LA t9, mips_cache_reset + jalr t9 + nop + + /* ... and enable them */ + li t0, CONFIG_SYS_MIPS_CACHE_MODE + mtc0 t0, CP0_CONFIG +#endif + + /* Set up temporary stack */ + PTR_LI t0, -16 + PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR + and sp, t1, t0 # force 16 byte alignment + PTR_SUB sp, sp, GD_SIZE # reserve space for gd + and sp, sp, t0 # force 16 byte alignment + move k0, sp # save gd pointer +#ifdef CONFIG_SYS_MALLOC_F_LEN + PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN + PTR_SUB sp, sp, t2 # reserve space for early malloc + and sp, sp, t0 # force 16 byte alignment +#endif + move fp, sp + + /* Clear gd */ + move t0, k0 +1: + sw zero, 0(t0) + blt t0, t1, 1b + PTR_ADDI t0, 4 + +#ifdef CONFIG_SYS_MALLOC_F_LEN + PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset + sw sp, 0(t0) +#endif + + PTR_LA t9, board_init_f + jr t9 + move ra, zero + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl relocate_code + .ent relocate_code +relocate_code: + move sp, a0 # set new stack pointer + move fp, sp + + move s0, a1 # save gd in s0 + move s2, a2 # save destination address in s2 + + PTR_LI t0, CONFIG_SYS_MONITOR_BASE + PTR_SUB s1, s2, t0 # s1 <-- relocation offset + + PTR_LA t3, in_ram + PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end + move t1, a2 + + PTR_ADD gp, s1 # adjust gp + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ +1: + lw t3, 0(t0) + sw t3, 0(t1) + PTR_ADDU t0, 4 + blt t0, t2, 1b + PTR_ADDU t1, 4 + + /* If caches were enabled, we would have to flush them here. */ + PTR_SUB a1, t1, s2 # a1 <-- size + PTR_LA t9, flush_cache + jalr t9 + move a0, s2 # a0 <-- destination address + + /* Jump to where we've relocated ourselves */ + PTR_ADDI t0, s2, in_ram - _start + jr t0 + nop + + PTR __rel_dyn_end + PTR __rel_dyn_start + PTR __image_copy_end + PTR _GLOBAL_OFFSET_TABLE_ + PTR num_got_entries + +in_ram: + /* + * Now we want to update GOT. + * + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object + * generated by GNU ld. Skip these reserved entries from relocation. + */ + PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries + PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_ + PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries + PTR_LI t2, 2 +1: + PTR_L t1, 0(t8) + beqz t1, 2f + PTR_ADD t1, s1 + PTR_S t1, 0(t8) +2: + PTR_ADDI t2, 1 + blt t2, t3, 1b + PTR_ADDI t8, PTRSIZE + + /* Update dynamic relocations */ + PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start + PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end + + b 2f # skip first reserved entry + PTR_ADDI t1, 2 * PTRSIZE + +1: + lw t8, -4(t1) # t8 <-- relocation info + + PTR_LI t3, MIPS_RELOC + bne t8, t3, 2f # skip non-MIPS_RELOC entries + nop + + PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH + + PTR_L t8, 0(t3) # t8 <-- original pointer + PTR_ADD t8, s1 # t8 <-- adjusted pointer + + PTR_ADD t3, s1 # t3 <-- location to fix up in RAM + PTR_S t8, 0(t3) + +2: + blt t1, t2, 1b + PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes + + /* + * Clear BSS + * + * GOT is now relocated. Thus __bss_start and __bss_end can be + * accessed directly via $gp. + */ + PTR_LA t1, __bss_start # t1 <-- __bss_start + PTR_LA t2, __bss_end # t2 <-- __bss_end + +1: + PTR_S zero, 0(t1) + blt t1, t2, 1b + PTR_ADDI t1, PTRSIZE + + move a0, s0 # a0 <-- gd + move a1, s2 + PTR_LA t9, board_init_r + jr t9 + move ra, zero + + .end relocate_code diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c new file mode 100644 index 0000000..553da5f --- /dev/null +++ b/arch/mips/cpu/time.c @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mipsregs.h> + +unsigned long notrace timer_read_counter(void) +{ + return read_c0_count(); +} + +ulong notrace get_tbclk(void) +{ + return CONFIG_SYS_MIPS_TIMER_FREQ; +} -- 1.9.1

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[U-Boot] [PATCH] MIPS: move au1x00 SoC code to arch/mips/mach-au1x00
by Daniel Schwierzeck 29 Jan '15

29 Jan '15

Move all au1x00 code out of arch/mips/cpu/mips32 to allow unification of CPU code in a later patch. The reorganization of the SoC specific header files will be done in a later patch series. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Paul Burton <paul.burton(a)imgtec.com> --- arch/mips/Makefile | 2 ++ arch/mips/cpu/mips32/Makefile | 2 -- arch/mips/cpu/mips32/cpu.c | 8 -------- arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/Makefile | 0 arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_eth.c | 6 ++++++ arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_ide.c | 0 arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_serial.c | 0 arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_usb_ohci.c | 0 arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_usb_ohci.h | 0 arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/config.mk | 0 10 files changed, 8 insertions(+), 10 deletions(-) rename arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/Makefile (100%) rename arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_eth.c (98%) rename arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_ide.c (100%) rename arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_serial.c (100%) rename arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_usb_ohci.c (100%) rename arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/au1x00_usb_ohci.h (100%) rename arch/mips/{cpu/mips32/au1x00 => mach-au1x00}/config.mk (100%) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0a9e7e6..ff01bfe 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -8,3 +8,5 @@ head-$(CONFIG_CPU_MIPS64) := arch/mips/cpu/mips64/start.o libs-$(CONFIG_CPU_MIPS32) += arch/mips/cpu/mips32/ libs-$(CONFIG_CPU_MIPS64) += arch/mips/cpu/mips64/ libs-y += arch/mips/lib/ + +libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index 19d316a..cb4db9c 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -7,5 +7,3 @@ extra-y = start.o obj-y = cpu.o interrupts.o time.o - -obj-$(CONFIG_SOC_AU1X00) += au1x00/ diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c index 8e1cc4e..07deca8 100644 --- a/arch/mips/cpu/mips32/cpu.c +++ b/arch/mips/cpu/mips32/cpu.c @@ -32,11 +32,3 @@ void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) write_c0_index(index); tlb_write_indexed(); } - -int cpu_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SOC_AU1X00 - au1x00_enet_initialize(bis); -#endif - return 0; -} diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/mach-au1x00/Makefile similarity index 100% rename from arch/mips/cpu/mips32/au1x00/Makefile rename to arch/mips/mach-au1x00/Makefile diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c similarity index 98% rename from arch/mips/cpu/mips32/au1x00/au1x00_eth.c rename to arch/mips/mach-au1x00/au1x00_eth.c index 4770f56..39c5b6b 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c +++ b/arch/mips/mach-au1x00/au1x00_eth.c @@ -294,3 +294,9 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } + +int cpu_eth_init(bd_t *bis) +{ + au1x00_enet_initialize(bis); + return 0; +} diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_ide.c b/arch/mips/mach-au1x00/au1x00_ide.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00/au1x00_ide.c rename to arch/mips/mach-au1x00/au1x00_ide.c diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/arch/mips/mach-au1x00/au1x00_serial.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00/au1x00_serial.c rename to arch/mips/mach-au1x00/au1x00_serial.c diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c similarity index 100% rename from arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c rename to arch/mips/mach-au1x00/au1x00_usb_ohci.c diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h b/arch/mips/mach-au1x00/au1x00_usb_ohci.h similarity index 100% rename from arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h rename to arch/mips/mach-au1x00/au1x00_usb_ohci.h diff --git a/arch/mips/cpu/mips32/au1x00/config.mk b/arch/mips/mach-au1x00/config.mk similarity index 100% rename from arch/mips/cpu/mips32/au1x00/config.mk rename to arch/mips/mach-au1x00/config.mk -- 1.9.1

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[U-Boot] [PATCH 0/4] malta: IDE support, reset fix, config updates
by Paul Burton 29 Jan '15

29 Jan '15

This series includes a few assorted improvements to the MIPS Malta board support. Paul Burton (4): malta: IDE support malta: delay after reset malta: enable HUSH parser malta: enable ELF loading arch/mips/include/asm/malta.h | 5 +++++ board/imgtec/malta/malta.c | 20 ++++++++++++++++++++ include/configs/malta.h | 13 +++++++++++++ 3 files changed, 38 insertions(+) -- 2.2.2

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[U-Boot] [PATCH v2 0/8] MIPS cache code cleanup
by Paul Burton 29 Jan '15

29 Jan '15

This series cleans up the MIPS cache code somewhat, and unifies the mips32 & mips64 implementations of it. This is largely in preparation for further patches adding L2 cache support. The final patch of this series fixes a bug encountered with recent cores on Malta boards. Paul Burton (8): MIPS: avoid .set ISA for cache operations MIPS: unify cache maintenance functions MIPS: unify cache initialization code MIPS: refactor L1 cache config reads to a macro MIPS: refactor cache loops to a macro MIPS: inline mips_init_[id]cache functions MIPS: allow systems to skip loads during cache init MIPS: clear TagLo select 2 during cache init arch/mips/Kconfig | 6 + arch/mips/cpu/mips32/Makefile | 3 +- arch/mips/cpu/mips32/cpu.c | 119 ----------- arch/mips/cpu/mips64/Makefile | 2 +- arch/mips/cpu/mips64/cache.S | 213 -------------------- arch/mips/cpu/mips64/cpu.c | 58 ------ arch/mips/include/asm/cacheops.h | 13 ++ arch/mips/lib/Makefile | 2 + arch/mips/lib/cache.c | 118 +++++++++++ arch/mips/{cpu/mips32/cache.S => lib/cache_init.S} | 222 +++++++++------------ 10 files changed, 232 insertions(+), 524 deletions(-) delete mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/lib/cache.c rename arch/mips/{cpu/mips32/cache.S => lib/cache_init.S} (59%) -- 2.2.2

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[U-Boot] [PATCH v2] net: configure DWMAC DMA by default AXI burst length
by Sonic Zhang 29 Jan '15

29 Jan '15

From: Sonic Zhang <sonic.zhang(a)analog.com> Board can define its own AXI burst length to improve DWMAC DMA performance. v2-changes: - Avoid write burst len register when the Macro is not defined. Signed-off-by: Sonic Zhang <sonic.zhang(a)analog.com> --- drivers/net/designware.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9ded895..51eff85 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -256,6 +256,10 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); +#ifdef CONFIG_DW_AXI_BURST_LEN + writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); +#endif + /* Start up the PHY */ if (phy_startup(priv->phydev)) { printf("Could not initialize PHY %s\n", -- 1.7.9.5

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[U-Boot] [PATCH] net: configure DWMAC DMA by default AXI burst length
by sonic.adi＠gmail.com 29 Jan '15

29 Jan '15

From: Sonic Zhang <sonic.zhang(a)analog.com> Board can define its own AXI burst length to improve DWMAC DMA performance. Signed-off-by: Sonic Zhang <sonic.zhang(a)analog.com> --- drivers/net/designware.c | 2 ++ drivers/net/designware.h | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9ded895..d8d6792 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -256,6 +256,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); + writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); + /* Start up the PHY */ if (phy_startup(priv->phydev)) { printf("Could not initialize PHY %s\n", diff --git a/drivers/net/designware.h b/drivers/net/designware.h index ce51102..d8bd84d 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -102,6 +102,11 @@ struct eth_dma_regs { #define TXSECONDFRAME (1 << 2) #define RXSTART (1 << 1) +/* Default AXI BUS Burst length */ +#ifndef CONFIG_DW_AXI_BURST_LEN +#define CONFIG_DW_AXI_BURST_LEN 0 +#endif + /* Descriptior related definitions */ #define MAC_MAX_FRAME_SZ (1600) -- 1.7.9.5

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[U-Boot] [RFC PATCH 0/6] x86: New Intel Quark SoC support
by Bin Meng 29 Jan '15

29 Jan '15

This series adds the first step of bare support for the Intel Quark SoC support which can be validated on Intel Galileo board. Intel Quark is a line of 32-bit x86 SoCs by Intel, designed for small size and low power consumption, and targeted at new markets including wearable devices. They are smaller and slower than Atom processors and consume less power. They lack support for SIMD instruction sets (such as MMX and SSE) and only support embedded operating systems. Quark powers the Intel Galileo developer microcontroller board. The CPU instruction set is the same as Pentium (P54C/i586) CPU. Intel decided to completely publish Quark's hardware specification to software developers, which includes an SoC datasheet, a UEFI Firmware Writer's Guide, and a complete reference source code for the UEFI BIOS which is pre-flahsed on the Galileo board. As of today, the only BIOS for Galileo is the Intel one with UEFI inteface only. There is no CSM support yet in that BIOS, neither any 3rd party BIOS vendor provides support to Quark SoC. Note there are two generation of Galileo boards, aka gen1 and gen2. Currently the development work is on gen2, but once we get it boot, we can easily add the gen1 board (old version). With this patch series, the generated u-boot.rom could boot the Intel Galileo board up to fdt relocate, where U-Boot hangs because the DRAM is not initializaed yet. A follow up patch series will be sent soon to add support for Memory Reference Code (MRC). Note this patch series may need rebase after Simon's Minnowmax support patch series is applied. Bin Meng (6): x86: Add header files for Intel Quark SoC defines x86: quark: Add routines to access message bus registers x86: quark: Add Cache-As-RAM initialization x86: Add basic Intel Quark processor support x86: Add basic Intel Galileo board support x86: Enable the Intel quark/galileo build arch/x86/Kconfig | 17 +++++ arch/x86/cpu/Makefile | 1 + arch/x86/cpu/quark/Kconfig | 63 +++++++++++++++++ arch/x86/cpu/quark/Makefile | 8 +++ arch/x86/cpu/quark/car.S | 105 +++++++++++++++++++++++++++++ arch/x86/cpu/quark/dram.c | 39 +++++++++++ arch/x86/cpu/quark/msg_port.c | 76 +++++++++++++++++++++ arch/x86/cpu/quark/pci.c | 70 +++++++++++++++++++ arch/x86/cpu/quark/quark.c | 44 ++++++++++++ arch/x86/dts/Makefile | 3 +- arch/x86/dts/galileo.dts | 43 ++++++++++++ arch/x86/include/asm/arch-quark/device.h | 28 ++++++++ arch/x86/include/asm/arch-quark/gpio.h | 13 ++++ arch/x86/include/asm/arch-quark/msg_port.h | 93 +++++++++++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 57 ++++++++++++++++ board/intel/galileo/Kconfig | 21 ++++++ board/intel/galileo/MAINTAINERS | 6 ++ board/intel/galileo/Makefile | 7 ++ board/intel/galileo/galileo.c | 19 ++++++ board/intel/galileo/start.S | 9 +++ configs/galileo_defconfig | 6 ++ include/configs/galileo.h | 53 +++++++++++++++ 22 files changed, 780 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/quark/Kconfig create mode 100644 arch/x86/cpu/quark/Makefile create mode 100644 arch/x86/cpu/quark/car.S create mode 100644 arch/x86/cpu/quark/dram.c create mode 100644 arch/x86/cpu/quark/msg_port.c create mode 100644 arch/x86/cpu/quark/pci.c create mode 100644 arch/x86/cpu/quark/quark.c create mode 100644 arch/x86/dts/galileo.dts create mode 100644 arch/x86/include/asm/arch-quark/device.h create mode 100644 arch/x86/include/asm/arch-quark/gpio.h create mode 100644 arch/x86/include/asm/arch-quark/msg_port.h create mode 100644 arch/x86/include/asm/arch-quark/quark.h create mode 100644 board/intel/galileo/Kconfig create mode 100644 board/intel/galileo/MAINTAINERS create mode 100644 board/intel/galileo/Makefile create mode 100644 board/intel/galileo/galileo.c create mode 100644 board/intel/galileo/start.S create mode 100644 configs/galileo_defconfig create mode 100644 include/configs/galileo.h -- 1.8.2.1

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Re: [U-Boot] [RFC PATCH 7/7] net: Add ARP and PING response to sandbox driver
by Simon Glass 29 Jan '15

29 Jan '15

Hi Joe, On 28 January 2015 at 03:36, Joe Hershberger <joe.hershberger(a)gmail.com> wrote: > On Tue, Jan 27, 2015 at 8:34 PM, Simon Glass <sjg(a)chromium.org> wrote: >> >> Hi Joe, >> >> On 27 January 2015 at 16:27, Joe Hershberger <joe.hershberger(a)ni.com> >> wrote: >> > The sandbox driver will now generate response traffic to exercise the >> > ping command even when no network exists. This allows the basic data >> > pathways of the DM to be tested. >> > >> > Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> >> > --- >> >> Looks like this can support ping. Very nice. > > I looked at other ways to test the network stack in sandbox, create tests in > the test/ dir, etc., but this seemed like the best and most straightforward > way to exercise it without tons of extra code, so I went for this approach. Well we still need tests in the test/ directory - every uclass should have tests. In this case the tests could start up a few devices and try ping. Also the environment variable logic needs tests. > >> > >> > drivers/net/sandbox.c | 75 >> > +++++++++++++++++++++++++++++++++++++++++++++++++++ >> > 1 file changed, 75 insertions(+) >> > >> > diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c >> > index e1ee69b..49413f2 100644 >> > --- a/drivers/net/sandbox.c >> > +++ b/drivers/net/sandbox.c >> > @@ -20,6 +20,11 @@ struct eth_sandbox_priv { >> > int sd; >> > }; >> > >> > +static uchar fake_host_hwaddr[ARP_HLEN] = {0x00, 0x00, 0x66, 0x44, >> > 0x22, 0x00}; >> > +static IPaddr_t fake_host_ipaddr; >> > +static uchar recv_packet_buffer[PKTSIZE]; >> > +static int recv_packet_length; >> >> This could go in the driver's priv area (then we could support >> multiple sandbox devices). > > Good idea. > > >> > + >> > int sb_eth_init(struct udevice *dev, bd_t *bis) >> > { >> > printf("eth_sandbox: Init\n"); >> > @@ -31,12 +36,82 @@ int sb_eth_send(struct udevice *dev, void *packet, >> > int length) >> > { >> > printf("eth_sandbox: Send packet %d\n", length); >> > >> > + struct ethernet_hdr *eth = packet; >> > + if (ntohs(eth->et_protlen) == PROT_ARP) { >> > + struct arp_hdr *arp = packet + ETHER_HDR_SIZE; >> > + if (ntohs(arp->ar_op) == ARPOP_REQUEST) { >> > + /* store this as the assumed IP of the fake host >> > */ >> > + fake_host_ipaddr = NetReadIP(&arp->ar_tpa); >> > + /* Formulate a fake response */ >> > + struct ethernet_hdr *eth_recv = >> > + (void *)recv_packet_buffer; >> > + memcpy(eth_recv->et_dest, eth->et_src, >> > ARP_HLEN); >> > + memcpy(eth_recv->et_src, fake_host_hwaddr, >> > ARP_HLEN); >> > + eth_recv->et_protlen = htons(PROT_ARP); >> > + >> > + struct arp_hdr *arp_recv = (void >> > *)recv_packet_buffer + >> > + ETHER_HDR_SIZE; >> > + arp_recv->ar_hrd = htons(ARP_ETHER); >> > + arp_recv->ar_pro = htons(PROT_IP); >> > + arp_recv->ar_hln = ARP_HLEN; >> > + arp_recv->ar_pln = ARP_PLEN; >> > + arp_recv->ar_op = htons(ARPOP_REPLY); >> > + memcpy(&arp_recv->ar_sha, fake_host_hwaddr, >> > ARP_HLEN); >> > + NetWriteIP(&arp_recv->ar_spa, fake_host_ipaddr); >> > + memcpy(&arp_recv->ar_tha, &arp->ar_sha, >> > ARP_HLEN); >> > + NetCopyIP(&arp_recv->ar_tpa, &arp->ar_spa); >> > + >> > + recv_packet_length = ETHER_HDR_SIZE + >> > ARP_HDR_SIZE; >> > + } >> > + } else if (ntohs(eth->et_protlen) == PROT_IP) { >> > + struct ip_udp_hdr *ip = packet + ETHER_HDR_SIZE; >> > + if (ip->ip_p == IPPROTO_ICMP) { >> > + struct icmp_hdr *icmp = (struct icmp_hdr >> > *)&ip->udp_src; >> > + if (icmp->type == ICMP_ECHO_REQUEST) { >> > + /* reply to the ping */ >> > + memcpy(recv_packet_buffer, packet, >> > length); >> > + struct ethernet_hdr *eth_recv = >> > + (void *)recv_packet_buffer; >> > + struct ip_udp_hdr *ipr = >> > + (void *)recv_packet_buffer + >> > + ETHER_HDR_SIZE; >> > + struct icmp_hdr *icmpr = >> > + (struct icmp_hdr >> > *)&ipr->udp_src; >> > + memcpy(eth_recv->et_dest, eth->et_src, >> > + ARP_HLEN); >> > + memcpy(eth_recv->et_src, >> > fake_host_hwaddr, >> > + ARP_HLEN); >> > + ipr->ip_sum = 0; >> > + ipr->ip_off = 0; >> > + NetCopyIP((void *)&ipr->ip_dst, >> > &ip->ip_src); >> > + NetWriteIP((void *)&ipr->ip_src, >> > + fake_host_ipaddr); >> > + ipr->ip_sum = ~NetCksum((uchar *)ipr, >> > + IP_HDR_SIZE >> 1); >> > + >> > + icmpr->type = ICMP_ECHO_REPLY; >> > + icmpr->checksum = 0; >> > + icmpr->checksum = ~NetCksum((uchar >> > *)icmpr, >> > + (length - ETHER_HDR_SIZE - >> > + IP_HDR_SIZE) >> 1); >> > + >> > + recv_packet_length = length; >> > + } >> > + } >> > + } >> > + >> > return 0; >> > #endif >> > } >> > >> > int sb_eth_recv(struct udevice *dev) >> > { >> > + if (recv_packet_length) { >> > + int lcl_recv_packet_length = recv_packet_length; >> > + printf("eth_sandbox: received packet %d\n", >> > recv_packet_length); >> > + recv_packet_length = 0; >> > + NetReceive((void *)recv_packet_buffer, >> > lcl_recv_packet_length); >> > + } >> > return 0; >> > } >> > >> >> Looks good. > > Thanks. Regards, Simon

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