January 2015 - U-Boot

[U-Boot] [PATCH] pci: tegra: Fix port information parsing
by Sjoerd Simons 31 Jan '15

31 Jan '15

commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the new fdtdec pci helpers. To get the device index of the root port, the "reg" property should be parsed from the dtb (as was previously the case). With this patch i can successfully network boot my jetson tk1 Signed-off-by: Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> --- drivers/pci/pci_tegra.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index f9e05ad..67b5fdf 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -459,7 +459,6 @@ static int tegra_pcie_parse_port_info(const void *fdt, int node, unsigned int *lanes) { struct fdt_pci_addr addr; - pci_dev_t bdf; int err; err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); @@ -470,13 +469,13 @@ static int tegra_pcie_parse_port_info(const void *fdt, int node, *lanes = err; - err = fdtdec_get_pci_bdf(fdt, node, &addr, &bdf); + err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); if (err < 0) { error("failed to parse \"reg\" property"); return err; } - *index = PCI_DEV(bdf) - 1; + *index = PCI_DEV(addr.phys_hi) - 1; return 0; } -- 2.1.4

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[U-Boot] [PATCH RFT] gpio: at91: Fix getting addres of private data
by Axel Lin 31 Jan '15

31 Jan '15

Use dev_get_priv() rather than dev_get_platdata() to get correct address of private data. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- Hi Simon, I don't have this h/w, so please test if you think this patch is ok. Thanks, Axel drivers/gpio/at91_gpio.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 6129c02..22fbd63 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -451,7 +451,7 @@ struct at91_port_priv { /* set GPIO pin 'gpio' as an input */ static int at91_gpio_direction_input(struct udevice *dev, unsigned offset) { - struct at91_port_priv *port = dev_get_platdata(dev); + struct at91_port_priv *port = dev_get_priv(dev); at91_set_port_input(port->regs, offset, 0); @@ -462,7 +462,7 @@ static int at91_gpio_direction_input(struct udevice *dev, unsigned offset) static int at91_gpio_direction_output(struct udevice *dev, unsigned offset, int value) { - struct at91_port_priv *port = dev_get_platdata(dev); + struct at91_port_priv *port = dev_get_priv(dev); at91_set_port_output(port->regs, offset, value); @@ -472,7 +472,7 @@ static int at91_gpio_direction_output(struct udevice *dev, unsigned offset, /* read GPIO IN value of pin 'gpio' */ static int at91_gpio_get_value(struct udevice *dev, unsigned offset) { - struct at91_port_priv *port = dev_get_platdata(dev); + struct at91_port_priv *port = dev_get_priv(dev); return at91_get_port_value(port->regs, offset); } @@ -481,7 +481,7 @@ static int at91_gpio_get_value(struct udevice *dev, unsigned offset) static int at91_gpio_set_value(struct udevice *dev, unsigned offset, int value) { - struct at91_port_priv *port = dev_get_platdata(dev); + struct at91_port_priv *port = dev_get_priv(dev); at91_set_port_value(port->regs, offset, value); @@ -490,7 +490,7 @@ static int at91_gpio_set_value(struct udevice *dev, unsigned offset, static int at91_gpio_get_function(struct udevice *dev, unsigned offset) { - struct at91_port_priv *port = dev_get_platdata(dev); + struct at91_port_priv *port = dev_get_priv(dev); /* GPIOF_FUNC is not implemented yet */ if (at91_get_port_output(port->regs, offset)) -- 1.9.1

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[U-Boot] Imx6 u-boot clock frequency and wrong lpj in the kernel
by Andy Ng 31 Jan '15

31 Jan '15

Dear colleagues, I faced a problem lately with the udelay function in the Linux kernel. udelay uses loops_per_jiffy constant for its loops. lpj is calculated during the init phase of the kernel, and then the calibrate function is removed. The boot loader uses 792MHz and when the kernel comes up dvfs framework adjusts the frequency to 1GHz, too late, and then the system keeps using lpj that was calculated at 792MHz. Ideally we need to get the uboot to clock the imx6 at 1GHz. Is there any special reason that u-boot does not pumps the clock up? Is there any patch out there that enables u-boot to start at 1GHz? Thank you Andy

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[U-Boot] [PATCH 00/12] arm: socfpga: Arria V support and fixes
by Marek Vasut 30 Jan '15

30 Jan '15

This series brings in a couple of minor fixes (mostly coding style and sync with rocketboards u-boot) and improvements (USB UMS and DFU support for Cyclone V SoC DK). There are also fixes for DT properties in this series to make those compatible with Linux. This series also adds Arria V SoC DK support. By adding the Arria V support, the pieces of code which are specific to a particular CPU model are now clearly isolated by an #ifdef. These #ifdef mark code which should be easy to dissolve and migrate into DT in the next step. While at this, the SoCFPGA platform is made dependent on having a proper Device Tree available (attached at the end of U-Boot binary). The board name is no longer hard-coded into the U-Boot binary, but is instead extracted from the DT ; this is the first step toward moving to DT altogether. At this point, no new SoCFPGA platform without DT is accepted anymore. Note: The DT files imported in this series come from Linux 3.18 mainline. Marek Vasut (12): arm: socfpga: Minor coding style fix arm: socfpga: Sync Cyclone V DK pinmux configuration arm: socfpga: Sync Cyclone V DK PLL configuration arm: socfpga: Add USB and UDC support for Cyclone V DK arm: socfpga: Drop cyclone5 suffix from board file name arm: socfpga: Add Altera Arria V DK support dt: socfpga: Rename snps,dw-spi-mmio to snps,dw-apb-ssi dt: socfpga: Replace num-chipselect with num-cs dt: socfpga: Import and enable Cyclone V DK DTS dt: socfpga: Import and enable Arria V DK DTS arm: socfpga: Zap checkboard() arm: socfpga: Zap board_early_init_f() arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/socfpga.dtsi | 10 +- arch/arm/dts/socfpga_arria5.dtsi | 34 + arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 +++ board/altera/socfpga/Kconfig | 16 + board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 17 +- board/altera/socfpga/pinmux_config.c | 403 +++++++++--- board/altera/socfpga/pinmux_config.h | 14 +- board/altera/socfpga/pll_config.h | 34 +- .../socfpga/{socfpga_cyclone5.c => socfpga.c} | 17 - configs/socfpga_arria5_defconfig | 5 + configs/socfpga_cyclone5_defconfig | 2 + drivers/spi/designware_spi.c | 2 +- include/configs/socfpga_arria5.h | 107 ++++ include/configs/socfpga_common.h | 3 +- include/configs/socfpga_cyclone5.h | 9 + 20 files changed, 1371 insertions(+), 155 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (86%) create mode 100644 configs/socfpga_arria5_defconfig create mode 100644 include/configs/socfpga_arria5.h Cc: Chin Liang See <clsee(a)opensource.altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vince Bridgers <vbridger(a)opensource.altera.com> -- 2.1.3

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[U-Boot] [PATCH] net/designware: add error message on DMA reset timeout
by Alexey Brodkin 30 Jan '15

30 Jan '15

If for some reason DMA module fails to reset user oserves only this: --->--- # dhcp Trying dwmac.e0018000 FAIL --->--- This message makes not much sense. With proposed change error message will be more helpful: --->--- # dhcp Trying dwmac.e0018000 DMA reset timeout FAIL --->--- For example user may do power toggle to recover board functionality. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Tom Rini <trini(a)ti.com> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Pavel Machek <pavel(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Ian Campbell <ijc(a)hellion.org.uk> Cc: Marek Vasut <marex(a)denx.de> --- drivers/net/designware.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9ded895..c03e935 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -236,8 +236,10 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) start = get_timer(0); while (readl(&dma_p->busmode) & DMAMAC_SRST) { - if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { + printf("DMA reset timeout\n"); return -1; + } mdelay(100); }; -- 2.1.0

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[U-Boot] [PATCH] net: phy: micrel: add support for KSZ8895 switch in SMI mode
by Philippe De Muyter 30 Jan '15

30 Jan '15

This patch adds a phy driver for the Micrel KSZ8895 switch. As the SoC MAC is directly connected to the switch MAC the link to the switch is always up. But the KSZ8895 switch can be hardwired in three configuration modes : - not configurable with eventually an eeprom-stored configuration - configurable by the mdio/mdc connection (SMI protocol) - configurable by a SPI connection. In not configurable mode, the switch starts automatically, but in the other modes, it must be started programmatically, by writing 1 in configuration register 1. We only support the not configurable and mdio/mdc (aka SMI) modes here. Signed-off-by: Philippe De Muyter <phdm(a)macqel.be> Cc: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- drivers/net/phy/micrel.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 58 insertions(+), 0 deletions(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5d7e3be..8fbd7d5 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -22,6 +22,63 @@ static struct phy_driver KSZ804_driver = { .shutdown = &genphy_shutdown, }; +/** + * KSZ8895 + */ + +static unsigned short smireg_to_phy(unsigned short reg) +{ + return ((reg & 0xc0) >> 3) + 0x06 + ((reg & 0x20) >> 5); +} + +static unsigned short smireg_to_reg(unsigned short reg) +{ + return reg & 0x1F; +} + +static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val) +{ + phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, + smireg_to_reg(smireg), val); +} + +#if 0 +static int ksz8895_read_smireg(struct phy_device *phydev, int smireg) +{ + return phydev->bus->read(phydev->bus, smireg_to_phy(smireg), + MDIO_DEVAD_NONE, smireg_to_reg(smireg)); +} +#endif + +int ksz8895_config(struct phy_device *phydev) +{ + /* we are connected directly to the switch without + * dedicated PHY. SCONF1 == 001 */ + phydev->link = 1; + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_100; + + /* Force the switch to start */ + ksz8895_write_smireg(phydev, 1, 1); + + return 0; +} + +static int ksz8895_startup(struct phy_device *phydev) +{ + return 0; +} + +static struct phy_driver ksz8895_driver = { + .name = "Micrel KSZ8895/KSZ8864", + .uid = 0x221450, + .mask = 0xffffe1, + .features = PHY_BASIC_FEATURES, + .config = &ksz8895_config, + .startup = &ksz8895_startup, + .shutdown = &genphy_shutdown, +}; + #ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number @@ -222,5 +279,6 @@ int phy_micrel_init(void) phy_register(&KS8721_driver); #endif phy_register(&ksz9031_driver); + phy_register(&ksz8895_driver); return 0; } -- 1.7.5.3

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[U-Boot] [PATCH v2 0/6] Add target board MS7206SE
by Yoshinori Sato 30 Jan '15

30 Jan '15

Hi. I updated MS7206SE support. Please review and comment Changes v2 cleanup for checkpatch.pl Yoshinori Sato (6): Add MS7206SE support Add MS7206SE ethernet support Add SH7206 support SH2A cache support Module enabler cleanup Various update arch/sh/config.mk | 3 + arch/sh/cpu/sh2/Makefile | 6 ++ arch/sh/cpu/sh2/cache-sh2a.c | 145 +++++++++++++++++++++++++++++++++ arch/sh/cpu/sh2/config.mk | 4 +- arch/sh/cpu/sh2/cpu.c | 58 +++---------- arch/sh/cpu/sh2/nocache.c | 36 ++++++++ arch/sh/cpu/sh2/start.S | 2 +- arch/sh/include/asm/cpu_sh2.h | 15 ++-- arch/sh/include/asm/cpu_sh2a.h | 16 ++++ arch/sh/include/asm/cpu_sh7206.h | 75 +++++++++++++++++ board/renesas/ms7206se/Makefile | 10 +++ board/renesas/ms7206se/lowlevel_init.S | 124 ++++++++++++++++++++++++++++ board/renesas/ms7206se/ms7206se.c | 43 ++++++++++ boards.cfg | 1 + drivers/net/smc91111.h | 31 ++++++- include/configs/ms7206se.h | 95 +++++++++++++++++++++ 16 files changed, 605 insertions(+), 59 deletions(-) create mode 100644 arch/sh/cpu/sh2/cache-sh2a.c create mode 100644 arch/sh/cpu/sh2/nocache.c create mode 100644 arch/sh/include/asm/cpu_sh2a.h create mode 100644 arch/sh/include/asm/cpu_sh7206.h create mode 100644 board/renesas/ms7206se/Makefile create mode 100644 board/renesas/ms7206se/lowlevel_init.S create mode 100644 board/renesas/ms7206se/ms7206se.c create mode 100644 include/configs/ms7206se.h -- 1.8.5.3

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[U-Boot] [PATCH 1/2] net: tsec: Fix NULL access in case init_phy() fails
by Claudiu Manoil 30 Jan '15

30 Jan '15

If the PHY is not recognized don't access phydev (NULL) and return 0 to signal failure. Signed-off-by: Claudiu Manoil <claudiu.manoil(a)freescale.com> --- drivers/net/tsec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e9138f0..65fb2b0 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -590,6 +590,8 @@ static int init_phy(struct eth_device *dev) tsec_configure_serdes(priv); phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + if (!phydev) + return 0; phydev->supported &= supported; phydev->advertising = phydev->supported; -- 1.7.11.7

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[U-Boot] net: tsec: Pending patches
by Claudiu Manoil 30 Jan '15

30 Jan '15

Hello, Would you please consider applying these two "net" tree patches? http://patchwork.ozlabs.org/patch/299620/ (net: Merge asm/fsl_enet.h into fsl_mdio.h) http://patchwork.ozlabs.org/patch/299447/ (net: tsec: Fix NULL access in case init_phy() fails) Thanks, Claudiu

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[U-Boot] [PATCH 01/14] microblaze: Fix stack usage in interrupt handler
by Michal Simek 30 Jan '15

30 Jan '15

Do not save registers below r1 stack pointer because it is not checked by stack undeflow is not able to detect it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/microblaze/cpu/irq.S | 121 +++++++++++++++++++++++----------------------- 1 file changed, 60 insertions(+), 61 deletions(-) diff --git a/arch/microblaze/cpu/irq.S b/arch/microblaze/cpu/irq.S index 24015898b0aa..5cfe1516bfcd 100644 --- a/arch/microblaze/cpu/irq.S +++ b/arch/microblaze/cpu/irq.S @@ -11,71 +11,70 @@ .text .global _interrupt_handler _interrupt_handler: - swi r2, r1, -4 - swi r3, r1, -8 - swi r4, r1, -12 - swi r5, r1, -16 - swi r6, r1, -20 - swi r7, r1, -24 - swi r8, r1, -28 - swi r9, r1, -32 - swi r10, r1, -36 - swi r11, r1, -40 - swi r12, r1, -44 - swi r13, r1, -48 - swi r14, r1, -52 - swi r15, r1, -56 - swi r16, r1, -60 - swi r17, r1, -64 - swi r18, r1, -68 - swi r19, r1, -72 - swi r20, r1, -76 - swi r21, r1, -80 - swi r22, r1, -84 - swi r23, r1, -88 - swi r24, r1, -92 - swi r25, r1, -96 - swi r26, r1, -100 - swi r27, r1, -104 - swi r28, r1, -108 - swi r29, r1, -112 - swi r30, r1, -116 - swi r31, r1, -120 addik r1, r1, -124 + swi r2, r1, 4 + swi r3, r1, 8 + swi r4, r1, 12 + swi r5, r1, 16 + swi r6, r1, 20 + swi r7, r1, 24 + swi r8, r1, 28 + swi r9, r1, 32 + swi r10, r1, 36 + swi r11, r1, 40 + swi r12, r1, 44 + swi r13, r1, 48 + swi r14, r1, 52 + swi r15, r1, 56 + swi r16, r1, 60 + swi r17, r1, 64 + swi r18, r1, 68 + swi r19, r1, 72 + swi r20, r1, 76 + swi r21, r1, 80 + swi r22, r1, 84 + swi r23, r1, 88 + swi r24, r1, 92 + swi r25, r1, 96 + swi r26, r1, 100 + swi r27, r1, 104 + swi r28, r1, 108 + swi r29, r1, 112 + swi r30, r1, 116 + swi r31, r1, 120 brlid r15, interrupt_handler nop + lwi r31, r1, 120 + lwi r30, r1, 116 + lwi r29, r1, 112 + lwi r28, r1, 108 + lwi r27, r1, 104 + lwi r26, r1, 100 + lwi r25, r1, 96 + lwi r24, r1, 92 + lwi r23, r1, 88 + lwi r22, r1, 84 + lwi r21, r1, 80 + lwi r20, r1, 76 + lwi r19, r1, 72 + lwi r18, r1, 68 + lwi r17, r1, 64 + lwi r16, r1, 60 + lwi r15, r1, 56 + lwi r14, r1, 52 + lwi r13, r1, 48 + lwi r12, r1, 44 + lwi r11, r1, 40 + lwi r10, r1, 36 + lwi r9, r1, 32 + lwi r8, r1, 28 + lwi r7, r1, 24 + lwi r6, r1, 20 + lwi r5, r1, 16 + lwi r4, r1, 12 + lwi r3, r1, 8 + lwi r2, r1, 4 addik r1, r1, 124 - lwi r31, r1, -120 - lwi r30, r1, -116 - lwi r29, r1, -112 - lwi r28, r1, -108 - lwi r27, r1, -104 - lwi r26, r1, -100 - lwi r25, r1, -96 - lwi r24, r1, -92 - lwi r23, r1, -88 - lwi r22, r1, -84 - lwi r21, r1, -80 - lwi r20, r1, -76 - lwi r19, r1, -72 - lwi r18, r1, -68 - lwi r17, r1, -64 - lwi r16, r1, -60 - lwi r15, r1, -56 - lwi r14, r1, -52 - lwi r13, r1, -48 - lwi r12, r1, -44 - lwi r11, r1, -40 - lwi r10, r1, -36 - lwi r9, r1, -32 - lwi r8, r1, -28 - lwi r7, r1, -24 - lwi r6, r1, -20 - lwi r5, r1, -16 - lwi r4, r1, -12 - lwi r3, r1, -8 - lwi r2, r1, -4 - rtid r14, 0 nop .size _interrupt_handler,.-_interrupt_handler -- 1.8.2.3

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