August 2014 - U-Boot

[U-Boot] [PATCH V4 00/19] Introduce cm-fx6 board
by Nikita Kiryanov 09 Sep '14

09 Sep '14

This patch series introduces the mx6 based cm-fx6 board. cm-fx6 comes with either single, dual, or quad core mx6 soc, and various dram configurations. First 12 patches are preparatory steps which include: - Cleanups and bug fixes for the mx6 dram config code - New functions and macros for enabling clocks, i2c setup, querying the status of sata port, and more - Support for M25PE16 and M25PX16 spi flashes - sf probe command fix when using mxc_spi driver NOTE: the correctness of this series depends on https://patchwork.ozlabs.org/patch/376095/ Changes in V4: - Rebase whole series over latest code (commit e49f14af1349eef94e41b636320bbfcace7403b5) - Patch "arm: mx6: add get_cpu_type()" is new to the series. - Adapt to use Kconfig - Initialize all ddr related structs statically - Don't #define CONFIG_SYS_L2CACHE_OFF for cm_fx6 - Use load instead of fatload in environment scripts - Refactoring across board support patches (introduce some functions in later patches, move/remove variables, coding style, etc. etc.); Details in the patches Changes in V3: - Remove CONFIG_SYS_TEXT_BASE from config file to not clash with the one supplied by imx6_spl.h - Use (clr|set)bits_le32() where possible Changes in V2: - Patch "spl: improve spi configuration" is replaced with "spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*", which kills CONFIG_SPL_SPI_* defines in favor of using CONFIG_SF_DEFAULT_*. - Updated commit message of "sf: fix sf probe", renaming it in the process to "spi: mxc: fix sf probe when using mxc_spi". - Return value handling. - Update commit message of "arm: mx6: ddr: configure MMDC for slow_pd" - Remove unnecessary line removal from arch/arm/cpu/armv7/mx6/ddr.c - Move probe_mmdc_config() code straight to dram_init() - Use imx6_spl.h - Use imx_ddr_size() Cc: Igor Grinberg <grinberg(a)compulab.co.il> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Nikita Kiryanov (19): spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_* mx6: add clock enabling functions spi: mxc: fix sf probe when using mxc_spi mtd: spi: add support for M25PE16 and M25PX16 compulab: eeprom: add support for defining eeprom i2c bus sata: dwc_ahsata: implement sata_port_status i2c: imx: add macros to setup pads for multiple SoC types arm: mx6: ddr: cleanup arm: mx6: ddr: do not write into reserved bit arm: mx6: ddr: configure MMDC for slow_pd arm: mx6: ddr: fix cs0_end calculation arm: mx6: add get_cpu_type() arm: mx6: add support for Compulab cm-fx6 CoM arm: mx6: cm_fx6: add nand support arm: mx6: cm_fx6: add ethernet support arm: mx6: cm_fx6: add usb support arm: mx6: cm_fx6: add i2c support arm: mx6: cm_fx6: use eeprom arm: mx6: cm_fx6: add sata support arch/arm/Kconfig | 4 + arch/arm/cpu/armv7/mx6/clock.c | 90 +++++ arch/arm/cpu/armv7/mx6/ddr.c | 271 +++++++-------- arch/arm/include/asm/arch-mx6/clock.h | 5 + arch/arm/include/asm/arch-mx6/sys_proto.h | 5 +- arch/arm/include/asm/imx-common/mxc_i2c.h | 33 ++ board/boundary/nitrogen6x/nitrogen6x.c | 5 + board/compulab/cm_fx6/Kconfig | 23 ++ board/compulab/cm_fx6/MAINTAINERS | 6 + board/compulab/cm_fx6/Makefile | 12 + board/compulab/cm_fx6/cm_fx6.c | 483 ++++++++++++++++++++++++++ board/compulab/cm_fx6/common.c | 84 +++++ board/compulab/cm_fx6/common.h | 37 ++ board/compulab/cm_fx6/imximage.cfg | 8 + board/compulab/cm_fx6/spl.c | 366 +++++++++++++++++++ board/compulab/common/eeprom.c | 13 +- board/embest/mx6boards/mx6boards.c | 5 + board/freescale/mx6qsabreauto/mx6qsabreauto.c | 7 + board/freescale/mx6sabresd/mx6sabresd.c | 7 + board/freescale/mx6slevk/mx6slevk.c | 5 + board/gateworks/gw_ventana/gw_ventana.c | 7 +- board/genesi/mx51_efikamx/efikamx.c | 5 + board/ttcontrol/vision2/vision2.c | 5 + common/cmd_sf.c | 13 - configs/cm_fx6_defconfig | 4 + drivers/block/dwc_ahsata.c | 17 + drivers/mtd/spi/sf_params.c | 2 + drivers/mtd/spi/spi_spl_load.c | 6 +- drivers/spi/mxc_spi.c | 48 +-- include/configs/am335x_evm.h | 2 - include/configs/cm_fx6.h | 290 ++++++++++++++++ include/configs/cm_t335.h | 1 + include/configs/cm_t35.h | 1 + include/configs/cm_t54.h | 1 + include/configs/da850evm.h | 4 - include/configs/dra7xx_evm.h | 2 - include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/ks2_evm.h | 2 - include/configs/mx51_efikamx.h | 4 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/pcm051.h | 2 - include/configs/sama5d3xek.h | 2 - include/configs/siemens-am33x-common.h | 2 - include/configs/tseries.h | 2 - include/configs/vision2.h | 4 +- include/configs/zynq-common.h | 2 - include/sata.h | 1 + include/spi_flash.h | 13 + 51 files changed, 1712 insertions(+), 209 deletions(-) create mode 100644 board/compulab/cm_fx6/Kconfig create mode 100644 board/compulab/cm_fx6/MAINTAINERS create mode 100644 board/compulab/cm_fx6/Makefile create mode 100644 board/compulab/cm_fx6/cm_fx6.c create mode 100644 board/compulab/cm_fx6/common.c create mode 100644 board/compulab/cm_fx6/common.h create mode 100644 board/compulab/cm_fx6/imximage.cfg create mode 100644 board/compulab/cm_fx6/spl.c create mode 100644 configs/cm_fx6_defconfig create mode 100644 include/configs/cm_fx6.h -- 1.9.1

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[U-Boot] [PATCH] imx: nitrogen6x: Replace 'fatload' by 'load' command in env settings to be filesystem independent
by Guillaume GARDET 09 Sep '14

09 Sep '14

nitrogen6x.h file defines CONFIG_CMD_FS_GENERIC, so we are able to use generic 'load' command instead of 'fatload'. It allows to use ext filesystem and keep compatibilty with fat filesystem. Signed-off-by: Guillaume GARDET <guillaume.gardet(a)free.fr> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/nitrogen6x.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index b2b17ce..d4b0ac9 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -192,11 +192,11 @@ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loaduimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ -- 1.8.4.5

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[U-Boot] [PATCH] mx6dlsabresd: Use its own DCD table
by Fabio Estevam 09 Sep '14

09 Sep '14

Currently mx6dlsabresd shares the same DCD settings with the nitrogen board. Provide a DCD configuration file specific to mx6dlsabresd with the settings recommended by the Freescale hardware team. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sabresd/mx6dlsabresd.cfg | 131 ++++++++++++++++++++++++++++ configs/mx6dlsabresd_defconfig | 2 +- 2 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 board/freescale/mx6sabresd/mx6dlsabresd.cfg diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg new file mode 100644 index 0000000..c3a8556 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000030 +DATA 4 0x020e04c0 0x00000030 +DATA 4 0x020e04c4 0x00000030 +DATA 4 0x020e04c8 0x00000030 +DATA 4 0x020e04cc 0x00000030 +DATA 4 0x020e04d0 0x00000030 +DATA 4 0x020e04d4 0x00000030 +DATA 4 0x020e04d8 0x00000030 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000030 +DATA 4 0x020e0770 0x00000030 +DATA 4 0x020e0778 0x00000030 +DATA 4 0x020e077c 0x00000030 +DATA 4 0x020e0780 0x00000030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e0470 0x00000030 +DATA 4 0x020e0474 0x00000030 +DATA 4 0x020e0478 0x00000030 +DATA 4 0x020e047c 0x00000030 +DATA 4 0x020e0480 0x00000030 +DATA 4 0x020e0484 0x00000030 +DATA 4 0x020e0488 0x00000030 +DATA 4 0x020e048c 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x4220021F +DATA 4 0x021b0840 0x0207017E +DATA 4 0x021b483c 0x4201020C +DATA 4 0x021b4840 0x01660172 +DATA 4 0x021b0848 0x4A4D4E4D +DATA 4 0x021b4848 0x4A4F5049 +DATA 4 0x021b0850 0x3F3C3D31 +DATA 4 0x021b4850 0x3238372B +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x3F435313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00431023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index 9ce960e..7f6cdff 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y -- 1.9.1

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[U-Boot] [PATCH 1/2] arm: vf610: lpuart: fix status register handling
by Stefan Agner 09 Sep '14

09 Sep '14

The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan(a)agner.ch> --- drivers/serial/serial_lpuart.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index da5f9a2..96173ca 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -14,6 +14,7 @@ #define US1_TDRE (1 << 7) #define US1_RDRF (1 << 5) +#define US1_OR (1 << 3) #define UC2_TE (1 << 3) #define UC2_RE (1 << 2) @@ -38,14 +39,10 @@ static void lpuart_serial_setbrg(void) static int lpuart_serial_getc(void) { - u8 status; - - while (!(__raw_readb(&base->us1) & US1_RDRF)) + while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) WATCHDOG_RESET(); - status = __raw_readb(&base->us1); - status |= US1_RDRF; - __raw_writeb(status, &base->us1); + barrier(); return __raw_readb(&base->ud); } -- 2.0.4

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[U-Boot] [PATCH] mx6: Fix ECSPI typo in soc_boot_modes
by picmaster＠mail.bg 09 Sep '14

09 Sep '14

From: Nikolay Dimitrov <picmaster(a)mail.bg> Signed-off-by: Nikolay Dimitrov <picmaster(a)mail.bg> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/armv7/mx6/soc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index f2dee76..99b7c86 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -318,10 +318,10 @@ const struct boot_mode soc_boot_modes[] = { /* reserved value should start rom usb */ {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, - {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, - {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, - {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, - {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, + {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, + {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, + {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, + {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, /* 4 bit bus width */ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, -- 1.7.10.4

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[U-Boot] [PATCH] imximage: Fix imximage IVT bug for EIM-NOR boot
by Ye.Li 09 Sep '14

09 Sep '14

From: "Ye.Li" <Ye.Li(a)freescale.com> The load region size of EIM-NOR are defined to 0. For this case, the parameter "imximage_init_loadsize" must be calculated. The imximage tool implements the calculation in the "imximage_generate" function, but the following function "imximage_set_header" resets the value and not calculate. This bug cause some fields of IVT head are not correct, for example the boot_data and DCD overlay the application area. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- tools/imximage.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/imximage.c b/tools/imximage.c index 18dc051..faba238 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -568,6 +568,13 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, /* Parse dcd configuration file */ dcd_len = parse_cfg_file(imxhdr, params->imagename); + if (imximage_version == IMXIMAGE_V2) { + if (imximage_init_loadsize < imximage_ivt_offset + + sizeof(imx_header_v2_t)) + imximage_init_loadsize = imximage_ivt_offset + + sizeof(imx_header_v2_t); + } + /* Set the imx header */ (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset); -- 1.7.9.5

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[U-Boot] [PATCH] iMX6: Disable the L2 before chaning the PL310 latency
by Ye.Li 09 Sep '14

09 Sep '14

From: "Ye.Li" <Ye.Li(a)freescale.com> The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li(a)freescale.com> --- arch/arm/cpu/armv7/mx6/soc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index f20bdeb..cc2231a 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -394,6 +394,9 @@ void v7_outer_cache_enable(void) } #endif + /* Must disable the L2 before changing the latency parameters */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl); -- 1.7.9.5

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[U-Boot] [PATCH] imx: ventana: Avoid undefined behaviour
by Thierry Reding 09 Sep '14

09 Sep '14

From: Thierry Reding <treding(a)nvidia.com> The leds array within struct ventana has space for 3 elements, but the setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent versions of GCC complain about that: board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio': board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations] if (gpio_cfg[board].leds[i]) ^ board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop for (i = 0; i < 4; i++) { ^ Fix this by making the upper bound of the loop match the array size. Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- board/gateworks/gw_ventana/gw_ventana.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 9d2651f0cbf1..01212367c396 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -983,7 +983,7 @@ static void setup_board_gpio(int board) gpio_direction_output(gpio_cfg[board].pcie_rst, 0); /* turn off (active-high) user LED's */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { if (gpio_cfg[board].leds[i]) gpio_direction_output(gpio_cfg[board].leds[i], 1); } -- 2.0.4

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[U-Boot] [PATCH 0/2] imx: ventana: Add pci fixup for PLX switch
by Tim Harvey 09 Sep '14

09 Sep '14

Many of the Gateworks Ventana boards have a PLX PCIe switch where GPIO on the switch is used as the PERST# of the downstream ports. In the Linux kernel there is a PCI fixup that asserts these properly when the upstream port is enumerated. The first patch in this serial adds a board_pci_fixup_dev function define to allow hooking similarly to the kernel pci fixup functionality. The second patch uses the board_pci_fixup_dev function to perform the GPIO configuration on the switch for the downstream ports. Tim Harvey (2): pci: add support for board_pci_fixup_dev function imx: ventana: add pci fixup for PLX PEX860x switch GPIO board/gateworks/gw_ventana/gw_ventana.c | 30 ++++++++++++++++++++++++++++++ drivers/pci/pci.c | 4 ++++ include/configs/gw_ventana.h | 1 + include/pci.h | 7 +++++++ 4 files changed, 42 insertions(+) -- 1.8.3.2

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[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox
by Fabio Estevam 09 Sep '14

09 Sep '14

mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v6: - Only use FEC_DMA_RX_MINALIGN for the RX buffers Changes since v5: - Add Stefan's Ack Changes since v4: - None Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- drivers/net/fec_mxc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cefda4..d310016 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000 +/* + * The standard 32-byte DMA alignment does not work on mx6solox, which requires + * 64-byte alignment in the DMA RX FEC buffer. + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also + * satisfies the alignment on other SoCs (32-bytes) + */ +#define FEC_DMA_RX_MINALIGN 64 + #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@ -881,9 +889,9 @@ static int fec_alloc_descs(struct fec_priv *fec) /* Allocate RX buffers. */ /* Maximum RX buffer size. */ - size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN); + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); for (i = 0; i < FEC_RBD_NUM; i++) { - data = memalign(ARCH_DMA_MINALIGN, size); + data = memalign(FEC_DMA_RX_MINALIGN, size); if (!data) { printf("%s: error allocating rxbuf %d\n", __func__, i); goto err_ring; -- 1.9.1

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