August 2014 - U-Boot

[U-Boot] [PATCH 00/11] imx: ventana: misc patches
by Tim Harvey 09 Sep '14

09 Sep '14

This is a series of patches in my queue for the Gateworks Ventana family of boards. Tim Harvey (11): imx: ventana: set dynamic env var for flash layout imx: ventana: added cputype env var imx: ventana: remove caam disable per eeprom bit imx: ventana: add appropriate delay following GSC i2c write imx: ventana: add econfig command imx: ventana: add video enable gpio pinmux for GW54xx imx: ventana: add missing crlf to print imx: ventana: configure i2c_dis# pin properly for gw53xx imx: ventana: enable SION bit on gpio outputs imx: ventana: add iomux for PCISKT_WDIS# gpio imx: ventana: leave PCI reset de-asserted if PCI enabled board/gateworks/gw_ventana/eeprom.c | 168 ++++++++++++++++- board/gateworks/gw_ventana/gsc.c | 2 +- board/gateworks/gw_ventana/gw_ventana.c | 267 ++++++++++++---------------- board/gateworks/gw_ventana/ventana_eeprom.h | 11 ++ include/configs/gw_ventana.h | 5 +- 5 files changed, 297 insertions(+), 156 deletions(-) -- 1.8.3.2

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[U-Boot] [PATCH] imx: ventana: add GW5520 support
by Tim Harvey 09 Sep '14

09 Sep '14

The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as: * 2x MiniPCIe sockets * 2x USB host sockets * 2x i210 GigE * HDMI out * digital I/O expansion Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/gw_ventana/eeprom.c | 3 ++ board/gateworks/gw_ventana/gsc.c | 4 ++ board/gateworks/gw_ventana/gw_ventana.c | 80 ++++++++++++++++++++++++++--- board/gateworks/gw_ventana/ventana_eeprom.h | 1 + 4 files changed, 81 insertions(+), 7 deletions(-) diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index 3edc915..ab3bab8 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -80,6 +80,9 @@ read_eeprom(int bus, struct ventana_board_info *info) case '4': type = GW54xx; break; + case '5': + type = GW552x; + break; default: printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); type = GW_UNKNOWN; diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 1cf38d4..a34a9a8 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -117,6 +117,10 @@ int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10)); read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); break; + case '5': /* GW55xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + break; } return 0; } diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 2610e0a..452a905 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -299,6 +299,7 @@ int board_ehci_hcd_init(int port) /* Reset USB HUB (present on GW54xx/GW53xx) */ switch (info->model[3]) { case '3': /* GW53xx */ + case '5': /* GW552x */ SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 9), 0); mdelay(2); @@ -392,7 +393,8 @@ int board_eth_init(bd_t *bis) setup_iomux_enet(); #ifdef CONFIG_FEC_MXC - cpu_eth_init(bis); + if (board_type != GW552x) + cpu_eth_init(bis); #endif #ifdef CONFIG_CI_UDC @@ -614,15 +616,14 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* IOEXP_PWREN# */ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* GPS_SHDN */ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), /* VID_EN */ @@ -660,6 +661,30 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), }; +static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* MX6_DIO[4:9] */ + IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), + /* PCIEGBE1_OFF# */ + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), + /* PCIEGBE2_OFF# */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + /* * each baseboard has 4 user configurable Digital IO lines which can * be pinmuxed as a GPIO or in some cases a PWM @@ -908,6 +933,44 @@ struct ventana gpio_cfg[] = { .pcie_sson = IMX_GPIO_NR(1, 20), .wdis = IMX_GPIO_NR(5, 17), }, + + /* GW552x */ + { + .gpio_pads = gw552x_gpio_pads, + .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(2, 10), + { 0, 0 }, + 0 + }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + }, }; /* setup board specific PMIC */ @@ -1003,8 +1066,10 @@ static void setup_board_gpio(int board) } /* Expansion Mezzanine IO */ - gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); - gpio_direction_input(gpio_cfg[board].mezz_irq); + if (gpio_cfg[board].mezz_pwren) + gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); + if (gpio_cfg[board].mezz_irq) + gpio_direction_input(gpio_cfg[board].mezz_irq); /* RS485 Transmit Enable */ if (gpio_cfg[board].rs485en) @@ -1306,7 +1371,8 @@ int misc_init_r(void) sprintf(fdt, "%s-%s.dtb", cputype, str); setenv("fdt_file1", fdt); } - str[4] = 'x'; + if (board_type != GW552x) + str[4] = 'x'; str[5] = 'x'; str[6] = 0; if (!getenv("fdt_file2")) { diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index d64b910..af12711 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -109,6 +109,7 @@ enum { GW52xx, GW53xx, GW54xx, + GW552x, GW_UNKNOWN, GW_BADCRC, }; -- 1.8.3.2

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[U-Boot] [PATCH] imx: ventana: base SPL MMDC calibration on width and size not board
by Tim Harvey 09 Sep '14

09 Sep '14

The IMX6 MMDC calibration registers depend on propagation delay and capacitive loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the board layout varies little in trace-lengths such that propagation delays are irrelevant thus we can simply things by using calibration values obtained from various board layouts based on a common SoC and DDR chip configuration. This eliminates board-model from being needed allowing more flexibility. These values were tested on a large sample size of Gateworks Ventana boards ranging in layout, and memory configuration over the entire temperature range supported. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/gw_ventana/gw_ventana_spl.c | 189 ++++++++++++++++------------ 1 file changed, 109 insertions(+), 80 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index e943879..9fc253b 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -201,55 +201,79 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { .trasmin = 3500, }; -/* GW54xx specific calibration */ -static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = { +/* MT41K256M16HA-125 */ +static struct mx6_ddr3_cfg mt41k256m16ha_125 = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * calibration - these are the various CPU/DDR3 combinations we support + */ + +static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190018, - .p0_mpwldectrl1 = 0x0021001D, - .p1_mpwldectrl0 = 0x00160027, - .p1_mpwldectrl1 = 0x0012001E, + .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl1 = 0x00140026, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43370346, - .p0_mpdgctrl1 = 0x032A0321, - .p1_mpdgctrl0 = 0x433A034D, - .p1_mpdgctrl1 = 0x032F0235, + .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl1 = 0x433C034D, /* Read Calibration: DQS delay relative to DQ read access */ .p0_mprddlctl = 0x3C313539, - .p1_mprddlctl = 0x37333140, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x37393C38, - .p1_mpwrdlctl = 0x42334538, + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x003C003C, + .p0_mpwldectrl1 = 0x001F002A, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42410244, + .p0_mpdgctrl1 = 0x4234023A, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x484A4C4B, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x33342B32, }; -/* GW53xx specific calibration */ -static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = { +static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00160013, - .p0_mpwldectrl1 = 0x00090024, - .p1_mpwldectrl0 = 0x001F0018, - .p1_mpwldectrl1 = 0x000C001C, + .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl1 = 0x00140026, + .p1_mpwldectrl0 = 0x0021001C, + .p1_mpwldectrl1 = 0x0011001D, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x433A034C, - .p0_mpdgctrl1 = 0x0336032F, - .p1_mpdgctrl0 = 0x4343034A, - .p1_mpdgctrl1 = 0x03370222, + .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl1 = 0x433C034D, + .p1_mpdgctrl0 = 0x032C0324, + .p1_mpdgctrl1 = 0x03310232, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3F343638, - .p1_mprddlctl = 0x38373442, + .p0_mprddlctl = 0x3C313539, + .p1_mprddlctl = 0x37343141, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x343A3E39, - .p1_mpwrdlctl = 0x44344239, + .p0_mpwrdlctl = 0x36393C39, + .p1_mpwrdlctl = 0x42344438, }; -static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = { + +static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x003C003C, - .p0_mpwldectrl1 = 0x00330038, - .p1_mpwldectrl0 = 0x001F002A, + .p0_mpwldectrl1 = 0x001F002A, + .p1_mpwldectrl0 = 0x00330038, .p1_mpwldectrl1 = 0x0022003F, /* Read DQS Gating calibration */ .p0_mpdgctrl0 = 0x42410244, - .p0_mpdgctrl1 = 0x022D022D, - .p1_mpdgctrl0 = 0x4234023A, + .p0_mpdgctrl1 = 0x4234023A, + .p1_mpdgctrl0 = 0x022D022D, .p1_mpdgctrl1 = 0x021C0228, /* Read Calibration: DQS delay relative to DQ read access */ .p0_mprddlctl = 0x484A4C4B, @@ -259,51 +283,42 @@ static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = { .p1_mpwrdlctl = 0x3933332B, }; -/* GW52xx specific calibration */ -static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x0040003F, - .p0_mpwldectrl1 = 0x00370037, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x42420244, - .p0_mpdgctrl1 = 0x022F022F, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x49464B4A, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x32362C32, -}; - -/* GW51xx specific calibration */ -static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = { +static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00150016, - .p0_mpwldectrl1 = 0x001F0017, + .p0_mpwldectrl0 = 0x001E001A, + .p0_mpwldectrl1 = 0x0026001F, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x433D034D, - .p0_mpdgctrl1 = 0x033D032F, + .p0_mpdgctrl0 = 0x43370349, + .p0_mpdgctrl1 = 0x032D0327, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3F313639, + .p0_mprddlctl = 0x3D303639, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x33393F36, + .p0_mpwrdlctl = 0x32363934, }; -static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = { +static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x003D003F, - .p0_mpwldectrl1 = 0x002F0038, + .p0_mpwldectrl0 = 0X00220021, + .p0_mpwldectrl1 = 0X00200030, + .p1_mpwldectrl0 = 0X002D0027, + .p1_mpwldectrl1 = 0X00150026, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x423A023A, - .p0_mpdgctrl1 = 0x022A0228, + .p0_mpdgctrl0 = 0x43330342, + .p0_mpdgctrl1 = 0x0339034A, + .p1_mpdgctrl0 = 0x032F0325, + .p1_mpdgctrl1 = 0x032F022E, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x48494C4C, + .p0_mprddlctl = 0X3A2E3437, + .p1_mprddlctl = 0X35312F3F, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x34352D31, + .p0_mpwrdlctl = 0X33363B37, + .p1_mpwrdlctl = 0X40304239, }; -static void spl_dram_init(int width, int size, int board_model) +static void spl_dram_init(int width, int size_mb, int board_model) { - struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125; - struct mx6_mmdc_calibration *calib; + struct mx6_ddr3_cfg *mem = NULL; + struct mx6_mmdc_calibration *calib = NULL; struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ .dsize = width/32, @@ -329,29 +344,43 @@ static void spl_dram_init(int width, int size, int board_model) /* * MMDC Calibration requires the following data: * mx6_mmdc_calibration - board-specific calibration (routing delays) + * these calibration values depend on board routing, SoC, and DDR * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) * mx6_ddr_cfg - chip specific timing/layout details */ - switch (board_model) { - default: - case GW51xx: + if (width == 32 && size_mb == 512) { + mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &gw51xxq_mmdc_calib; + calib = &mx6dq_128x32_mmdc_calib; else - calib = &gw51xxdl_mmdc_calib; - break; - case GW52xx: - calib = &gw52xxdl_mmdc_calib; - break; - case GW53xx: + calib = &mx6sdl_128x32_mmdc_calib; + debug("2gB density\n"); + } else if (width == 64 && size_mb == 1024) { + mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &gw53xxq_mmdc_calib; + calib = &mx6dq_128x64_mmdc_calib; else - calib = &gw53xxdl_mmdc_calib; - break; - case GW54xx: - calib = &gw54xxq_mmdc_calib; - break; + calib = &mx6sdl_128x64_mmdc_calib; + debug("2gB density\n"); + } else if (width == 32 && size_mb == 1024) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x32_mmdc_calib; + debug("4gB density\n"); + } else if (width == 64 && size_mb == 2048) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x64_mmdc_calib; + debug("4gB density\n"); + } + + if (!mem) { + puts("Error: Invalid Memory Configuration\n"); + hang(); + } + if (!calib) { + puts("Error: Invalid Board Calibration Configuration\n"); + hang(); } if (is_cpu_type(MXC_CPU_MX6Q)) -- 1.8.3.2

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[U-Boot] [PATCH] imx: ventana: updated notes regarding NAND boot errata
by Tim Harvey 09 Sep '14

09 Sep '14

Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/gw_ventana/gw_ventana.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 2928ac1..2610e0a 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1342,10 +1342,11 @@ int misc_init_r(void) * The Gateworks System Controller implements a boot * watchdog (always enabled) as a workaround for IMX6 boot related * errata such as: - * ERR005768 - no fix - * ERR006282 - fixed in silicon r1.3 + * ERR005768 - no fix scheduled + * ERR006282 - fixed in silicon r1.2 * ERR007117 - fixed in silicon r1.3 * ERR007220 - fixed in silicon r1.3 + * ERR007926 - no fix scheduled * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf * * Disable the boot watchdog and display/clear the timeout flag if set -- 1.8.3.2

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[U-Boot] Recommended MIPS toolchain
by Vasili Galka 08 Sep '14

08 Sep '14

Hi, What is the recommended tool-chain to verify compilation of MIPS boards? I tried the one from https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ But it does not work, throws plenty of errors about hard/soft float. Regards, Vasili

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[U-Boot] Verified boot and Legacy Kernel Images
by Mike Pearce 07 Sep '14

07 Sep '14

Please help as I am confused. I implemented verified boot on 2014.04 using CONFIG_OF_SEPARATE and it works fine with FIT images. However it still boots the resident legacy kernal that has not been signed. This means that anyone wishing to circumvent the signed hash can do so by replacing the image file with a legacy one. That makes for a security hole and so I must have done something wrong. When I look at function bootm_find_os() from file cmd_bootm.c its switch statement provides this behaviour - case IMAGE_FORMAT_LEGACY: cool, its a go from me. Verify using an unsigned hash. break; #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: do the signed hash checks when loading the image. break; What I cannot find in the code is anything that I can compile in to prevent an unsigned legacy kernel from booting. The defines I already used include #define CONFIG_OF_LIBFDT #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY #define CONFIG_FIT_SIGNATURE #define CONFIG_RSA Thanks, Mike.

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[U-Boot] [PATCH v10 0/14] Add some missing buildman features and deprecate MAKEALL
by Simon Glass 06 Sep '14

06 Sep '14

Buildman has been around for a little over a year and is used by a fair number of U-Boot developers. However quite a few people still use MAKEALL. Buildman was intended to replace MAKEALL, so perhaps now is a good time to start that process. The reasons to deprecate MAKEALL are: - We don't want to maintain two build systems - Buildman is typically faster - Buildman has a lot more features This series adds a few features to buildman to fill some gaps, adds some information into the README on how to migrate from MAKEALL, and adds a deprecation message to MAKEALL. Changes in v10: - Remove the directory prefix more aggressively - Track prefixes and postfixes for warnings/errors Changes in v9: - Add new patch to avoid changing the order of tags - Add new patch to set the return code to indicate build result - Add new patch to allow make-flags variables to include '-' and '_' - Add new patch to implement --exclude option - Add new patch to remove the directory prefix from each error line - Add new patch to support showing which boards caused which errors - Add new patch to separate out display of warnings and errors - Add new patch to fix detection of git version Changes in v8: - Add new patch to disable the pager in git Changes in v7: - Add new patch to fix the 'reverse' bug - Remove already-applied patches from the series - Add the deprecation message at the end of the build also - Drop the 'colour' patch sadly Changes in v6: - Add new patch to fix indentation in teminal.py - Add new patch to fix patman unit tests - Add new patch to remove patman's -a option Changes in v5: - Drop patch to search for *cc instead of *gcc for the compiler Simon Glass (14): patman: Support the 'reverse' option for 'git log' patman: Fix indentation in terminal.py patman: Correct unit tests to run correctly patman: Remove the -a option patman: Use --no-pager' to stop git from forking a pager patman: Avoid changing the order of tags buildman: Set the return code to indicate build result buildman: Allow make-flags variables to include '-' and '_' buildman: Implement an option to exclude boards from the build buildman: Remove the directory prefix from each error line buildman: Add an option to show which boards caused which errors buildman: Separate out display of warnings and errors patman: Fix detection of git version RFC: Deprecate MAKEALL MAKEALL | 10 +++ tools/buildman/README | 27 ++++++-- tools/buildman/board.py | 31 +++++++-- tools/buildman/builder.py | 139 ++++++++++++++++++++++++++++++++++------ tools/buildman/builderthread.py | 4 +- tools/buildman/buildman.py | 8 ++- tools/buildman/control.py | 20 ++++-- tools/buildman/toolchain.py | 2 +- tools/patman/gitutil.py | 102 +++-------------------------- tools/patman/patchstream.py | 21 ++---- tools/patman/patman.py | 7 -- tools/patman/terminal.py | 112 +++++++++++++++++--------------- tools/patman/test.py | 13 ++-- 13 files changed, 286 insertions(+), 210 deletions(-) -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH 1/1] ARM: sheevaplug: fix uboot corruption
by Gerald Kerma 06 Sep '14

06 Sep '14

This patch move the environment offset in sheevaplug. The size of the u-boot binary is become too big. Saving environments will result of corrupting the u-boot. Signed-off-by: Gerald Kerma <drEagle(a)doukki.net> --- Changes in v1: - fix sheevaplug environment offset include/configs/sheevaplug.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 3d6ff09..85c6bc2 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -55,8 +55,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_ADDR 0x80000 +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ /* * Default environment variables -- 1.9.1

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[U-Boot] [PATCH V4 0/9] peach_pit: Add support for FIMD, DP and parade chip
by Ajay Kumar 05 Sep '14

05 Sep '14

Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html Patchset V2: https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html Patchset V3: http://lists.denx.de/pipermail/u-boot/2014-July/183096.html Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_is as per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY Changes from V2: [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c Removed TEST_ONLY patches. Changes from V3: [PATCH V4 1/9] : Fix comment style. [PATCH V4 3/9] : Use 'else if' clause instead of 'if'. Ajay Kumar (8): [PATCH V4 1/9] exynos_fb: Remove usage of static defines [PATCH V4 2/9] arm: exynos: Add RPLL for Exynos5420 [PATCH V4 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V4 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH V4 6/9] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V4 7/9] exynos5420: add callbacks needed for exynos_fb driver [PATCH V4 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V4 9/9] CONFIGS: peach-pit: Enable display for peach_pit board Vadim Bendebury (1): [PATCH V4 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge arch/arm/cpu/armv7/exynos/clock.c | 83 ++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 ++++ arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h | 1 + arch/arm/include/asm/arch-exynos/system.h | 4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 +++++--------- doc/device-tree-bindings/video/exynos-fb.txt | 6 + drivers/video/Makefile | 1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c | 43 +++++ drivers/video/parade.c | 220 ++++++++++++++++++++++++ include/configs/exynos5250-dt.h | 2 - include/configs/peach-pit.h | 10 ++ include/configs/s5pc210_universal.h | 3 - include/configs/trats.h | 3 - include/configs/trats2.h | 3 - include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 23 files changed, 492 insertions(+), 111 deletions(-) create mode 100644 drivers/video/parade.c -- 1.7.9.5

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[U-Boot] [PATCH] MAINTAINERS: update the maintainer of Arndale board
by Masahiro Yamada 05 Sep '14

05 Sep '14

Inderpal's email address is not working any more. Chander will be a new maintainer. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Chander Kashyap <k.chander(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- A new maintainer was assigned to Arndale board. But nobody wouldn't send a patch. Please see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/187338 board/samsung/arndale/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/samsung/arndale/MAINTAINERS b/board/samsung/arndale/MAINTAINERS index 0a01a07..7dc1785 100644 --- a/board/samsung/arndale/MAINTAINERS +++ b/board/samsung/arndale/MAINTAINERS @@ -1,5 +1,5 @@ ARNDALE BOARD -M: Inderpal Singh <inderpal.singh(a)linaro.org> +M: Chander Kashyap <k.chander(a)samsung.com> S: Maintained F: board/samsung/arndale/ F: include/configs/arndale.h -- 1.9.1

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