May 2014 - U-Boot

[U-Boot] Signed-off-by rules for U-Boot
by Stephen Warren 13 May '14

13 May '14

Does U-Boot follow the same Signed-off-by procedures as the Linux kernel, or is s-o-b only relevant in U-Boot for the initial patch submitter, and not maintainers? I ask because there are a bunch of patches of mine that got applied without the maintainer adding their S-o-b when applying them, which would be very unusual for Linux, but perhaps it's normal for U-Boot? Some likely non-exhaustive examples are: 2813006fecda usb: ci_udc: allow multiple buffer allocs per ep 66b88b07cdab usb: ums: add error handling for failed registration 264e0e591bbd config: enable CMD_BMP when API+LCD is enabled 53eb768dfb97 aes: make apply_cbc_chain_data non-static Yet others did get a maintainer s-o-b: d381294aef4a ARM: tegra: pack pinmux data tables tighter def816a2ba87 mmc: set rca to 1 for MMC cards 91171091c673 ARM: tegra: make use of negative ENV_OFFSET on NVIDIA... 6ab6a650a418 disk: initialize name/part fields when returning a whole... c75942c7b792 sf: winbond: fix page_size It seems like it mostly varies by maintainer.

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[U-Boot] [PATCH] boards.cfg: fix a configuration error of ep8248 board
by Masahiro Yamada 13 May '14

13 May '14

"make ep8248_config" fails with an error like this: $ make ep8248_config make: *** [ep8248_config] Error 1 Its cause is that there are two entries for "ep8248". The first is around line 652 of boards.cfg. (as Active) The second appears around line 1230. (as Orphan) This bug was accidentally introduced by commit e7e90901. But it is not the author's fault. He just intended to change IDS8247 board. The commiter added ep8248 entry by mistake when he resolved a conflict. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Kim Phillips <kim.phillips(a)linaro.org> --- Heiko's patch is correct. Compare http://patchwork.ozlabs.org/patch/314128/ and "git show -M e7e909010" You will easily understand what happened when Kim Phillips applied this patch. boards.cfg | 1 - 1 file changed, 1 deletion(-) diff --git a/boards.cfg b/boards.cfg index 983c657..c1d4b2d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -649,7 +649,6 @@ Active powerpc mpc8260 - - cpu86 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8260 - - cpu87 CPU87 - - Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - -Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli(a)arabellasw.com> Active powerpc mpc8260 - ids ids8247 IDS8247 - Heiko Schocher <hs(a)denx.de> Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg(a)denx.de> Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs(a)denx.de> -- 1.8.3.2

4 3

[U-Boot] [PATCH v4] qe: disable qe when qe-ucode fails to be uploaded for "deep sleep"
by Zhao Qiang 13 May '14

13 May '14

when qe-ucode fails to be uploaded, "deep sleep" will hang. if there is no qe-ucode, disable qe module for platforms which support "deep sleep" Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- Changes for v2: - add "#ifdef CONFIG_MPC85xx" Changes for v3: - modify commit msg Changes for v4: - modify "#ifdef CONFIG_MPC85xx" to "#ifdef CONFIG_DEEP_SLEEP" diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b1da75e..9c5fbd1 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -14,6 +14,8 @@ #include "asm/immap_qe.h" #include "qe.h" +#define MPC85xx_DEVDISR_QE_DISABLE 0x1 + qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; @@ -317,7 +319,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; - +#ifdef CONFIG_DEEP_SLEEP + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; @@ -330,6 +334,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif return -EPERM; } -- 1.8.5

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[U-Boot] [PATCH 0/5] PPC 85xx QEMU: Additional fixes
by Alexander Graf 13 May '14

13 May '14

After the initial round of the e500 QEMU machine patches got merged I realized that we were missing 2 pieces of the puzzle to make everything great: - KVM support - generic board file With this patch set I can successfully run u-boot inside of KVM on an e500v2 as well as an e500mc machine. I also no longer get warnings that I should convert the board to the generic board mechanism. Alex Alexander Graf (5): PPC 85xx QEMU: Always assume 1 core PPC 85xx QEMU: Don't use HID1 powerpc/mpc85xx: Update TLB CAMs in relocated mode powerpc/mpc85xx: Pass 0 flags to board_init_f PPC 85xx QEMU: Make a generic board file arch/powerpc/cpu/mpc85xx/cpu_init.c | 1 + arch/powerpc/cpu/mpc85xx/start.S | 3 ++- arch/powerpc/cpu/mpc8xxx/cpu.c | 4 ++-- board/freescale/qemu-ppce500/qemu-ppce500.c | 20 ++++++++++++++++++++ include/configs/qemu-ppce500.h | 1 + 5 files changed, 27 insertions(+), 4 deletions(-) -- 1.7.10.4

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[U-Boot] [PATCH 0/8] kmp204x patches for 2014.07
by Valentin Longchamp 13 May '14

13 May '14

Things have stabilized quite a lot on the u-boot front for the Keymile kmp204x/kmcoge4 board. There are a few remaining patches that should get merged to have a complete support of the architecture/board in u-boot. These include: - support for some additional functions of the QRIO board reset/control CPLD (LEDs, Factory Test signal) - better reset sequence according to the tests/problems noticed during the development - an update to the RCW (some external interrupts are unused and set as GPIOs now) - an additionnal workaround in the PBL file (with an implementation enhancement for a previous one). Stefan Bigler (2): kmp204x: Add support for the unit LEDs kmp204x: handle dip-switch for factory settings Valentin Longchamp (6): kmp204x: selftest/factory test pin support kmp204x: update the CONFIG_PRAM and CONFIG_KM_RESERVED_PRAM defines kmp204x: complete the reset sequence and PRST configuration kmp204x: update the RCW kmp204x: add workaround for A-004849 kmp204x: enable the errata command board/keymile/kmp204x/kmp204x.c | 75 ++++++++++++++++++++++++++++++----- board/keymile/kmp204x/kmp204x.h | 3 ++ board/keymile/kmp204x/pbi.cfg | 43 +++++++++++++++++--- board/keymile/kmp204x/pci.c | 17 ++++---- board/keymile/kmp204x/qrio.c | 29 +++++++++++++- board/keymile/kmp204x/rcw_kmp204x.cfg | 2 +- include/configs/km/kmp204x-common.h | 17 ++++---- 7 files changed, 151 insertions(+), 35 deletions(-) -- 1.8.0.1

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[U-Boot] [PATCH v2] powerpc/85xx: add T4080 SoC support
by Shengzhou Liu 13 May '14

13 May '14

The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- v2: add more comments. arch/powerpc/cpu/mpc85xx/Makefile | 2 ++ arch/powerpc/cpu/mpc85xx/cpu.c | 24 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++++++++- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 16 +++++++++++----- arch/powerpc/include/asm/fsl_errata.h | 2 ++ arch/powerpc/include/asm/immap_85xx.h | 6 ++++-- arch/powerpc/include/asm/processor.h | 1 + drivers/net/fm/Makefile | 1 + 11 files changed, 57 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4094785..ad26b43 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o obj-$(CONFIG_PPC_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_T4080) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o @@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o obj-$(CONFIG_PPC_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 12e8e10..684d400 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -77,6 +77,30 @@ int checkcpu (void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (SVR_SOC_VER(svr) == SVR_T4080) { + ccsr_rcpm_t *rcpm = + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || + FSL_CORENET_DEVDISR2_DTSEC1_9); + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); + + /* It needs SW to disable core4~7 as HW design sake on T4080 */ + for (i = 4; i < 8; i++) + cpu_disable(i); + + /* request core4~7 into PH20 state, prior to entering PCL10 + * state, all cores in cluster should be placed in PH20 state. + */ + setbits_be32(&rcpm->pcph20setr, 0xf0); + + /* put the 2nd cluster into PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, 1 << 1); + } +#endif + if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 36ef232..7e27464 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -462,10 +462,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); int enable_cluster_l2(void) { int i = 0; - u32 cluster; + u32 cluster, svr = get_svr(); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; + /* only the L2 of first cluster should be enabled as expected on T4080, + * but there is no EOC in the first cluster as HW sake, so return here + * to skip enabling L2 cache of the 2nd cluster. + */ + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d516d4e..3236f6a 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info) * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) if (SVR_MAJ(get_svr()) >= 2) mem_pll_rat *= 2; #endif diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index ff55e3c..1f99a0a 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 35795c4..dfedc53 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -62,6 +62,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), CPU_TYPE_ENTRY(T4160, T4160, 0), + CPU_TYPE_ENTRY(T4080, T4080, 4), CPU_TYPE_ENTRY(B4860, B4860, 0), CPU_TYPE_ENTRY(G4860, G4860, 0), CPU_TYPE_ENTRY(G4060, G4060, 0), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 864e74c..9bb0123 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -595,7 +595,8 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -611,13 +612,18 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #else -#define CONFIG_MAX_CPUS 8 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#if defined(CONFIG_PPC_T4160) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#elif defined(CONFIG_PPC_T4080) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } +#endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 4eba85c..1e548a0 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -16,6 +16,7 @@ static inline bool has_erratum_a006379(void) u32 svr = get_svr(); if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || @@ -49,6 +50,7 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T4240: case SVR_T4160: + case SVR_T4080: return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 741b861..eff573b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1748,7 +1748,8 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 72f30fe..a6f121e 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1111,6 +1111,7 @@ #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 +#define SVR_T4080 0x824102 #define SVR_C291 0x850000 #define SVR_C292 0x850020 #define SVR_C293 0x850030 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index ee5d768..5ae3b16 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_PPC_T2080) += t2080.o obj-$(CONFIG_PPC_T2081) += t2080.o obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o +obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o -- 1.8.0

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[U-Boot] [PATCH v2] powerpc/t208x: enable errata A006261, A006593, A006379
by Shengzhou Liu 13 May '14

13 May '14

Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- v2: rebase to latest 'master', and update has_erratum_a006261. arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_errata.h | 3 +++ include/configs/T208xRDB.h | 1 + 3 files changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 864e74c..0d6eb49 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -798,6 +798,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 4eba85c..d820121 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -52,6 +52,9 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); case SVR_P5040: return IS_SVR_REV(svr, 1, 0); } diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 73d82ed..ef22199 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -721,6 +721,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA #define CONFIG_CMD_MII #define CONFIG_CMD_I2C #define CONFIG_CMD_PING -- 1.8.0

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[U-Boot] [PATCH] powerpc/fman/memac: use default MDIO_HOLD value
by shh.xie＠gmail.com 13 May '14

13 May '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- drivers/net/fm/memac_phy.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 2f4bc11..de9c0e9 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); - setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) @@ -76,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); - setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) -- 1.8.0

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[U-Boot] [PATCH 2/2] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDB
by Aneesh Bansal 13 May '14

13 May '14

Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- arch/powerpc/include/asm/fsl_secure_boot.h | 1 + boards.cfg | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 9a0cb20..74c5d8f 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -20,6 +20,7 @@ #if defined(CONFIG_B4860QDS) || \ defined(CONFIG_T4240QDS) || \ defined(CONFIG_T2080QDS) || \ + defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ defined(CONFIG_T104xRDB) #define CONFIG_SYS_CPC_REINIT_F diff --git a/boards.cfg b/boards.cfg index aac8b10..831c35d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -969,6 +969,7 @@ Active powerpc mpc85xx - freescale t208xqds Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH - Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 - +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SECURE_BOOT T208xRDB:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -- 1.8.1.4

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[U-Boot] [PATCH 1/2] powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdb
by Aneesh Bansal 13 May '14

13 May '14

T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- arch/powerpc/include/asm/fsl_secure_boot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 29bef91..9a0cb20 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -21,7 +21,7 @@ defined(CONFIG_T4240QDS) || \ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T1040QDS) || \ - defined(CONFIG_T1040RDB) + defined(CONFIG_T104xRDB) #define CONFIG_SYS_CPC_REINIT_F #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 -- 1.8.1.4

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