May 2014 - U-Boot

[U-Boot] [PATCH v2 0/4] mpc8313: ids8313 board updates
by Heiko Schocher 15 May '14

15 May '14

- introduce CONFIG_IMAGE_FORMAT_LEGACY for enabling booting legacy image format. Disable this per default if CONFIG_FIT_SIGNATURE is defined. As the ids8313 board needs legacy image format and uses CONFIG_FIT_SIGNATURE, enable legacy image format for the ids8313 board - add CONFIG_SYS_GENERIC_BOARD to the ids8313 board, therefore fdtdec_get_int() is moved out of lib/fdtdec.c as lib/fdtdec.c is only compiled if CONFIG_OF_CONTROL is defined, but defining this for the ids8313 board leads in conjunction with CONFIG_SYS_GENERIC_BOARD in booting error: No valid FDT found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d <file.dtb> So move the common used function fdtdec_get_int() out of lib/fdtdec.c into lib/fdtdec_common.c Cc: Simon Glass <sjg(a)chromium.org> Cc: Kim Phillips <kim.phillips(a)freescale.com> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Michael Conrad <Michael.Conrad(a)ids.de> Tested this patchset on the ids8313 board, MAKEALL for powerpc and arm adds no compiler errors/warnings. While testing this patchset on the ids8313 board, I found, that current U-Boot compiles fine with eldk 5.5, but if erasing the sectors where U-Boot resists in the NOR flash, u-boot commands are not longer working :-( $ powerpc-linux-gcc -v Using built-in specs. COLLECT_GCC=powerpc-linux-gcc COLLECT_LTO_WRAPPER=/opt/eldk-5.5/powerpc/sysroots/i686-eldk-linux/usr/libexec/powerpc-linux/gcc/powerpc-linux/4.8.1/lto-wrapper Target: powerpc-linux [...] Thread model: posix gcc version 4.8.1 (GCC) $ This problem does not pop up with eldk 5.4 or 5.3 ! Digged a little bit in it, and found that some (not all!) fmt strings are loaded from flash addresses not from ram addresses ... gdb shows: Program received signal SIGTRAP, Trace/breakpoint trap. printf (fmt=0xfff5ad34 '\377' <repeats 200 times>..., fmt@entry=0x7fdad34 "parse_stream, end_trigger=%d\n") at /home/hs/ids/u-boot/common/console.c:479 ^^^^^^^^^^ addr in nor flash not in ram 479 { (gdb) bt #0 printf (fmt=0xfff5ad34 '\377' <repeats 200 times>..., fmt@entry=0x7fdad34 "parse_stream, end_trigger=%d\n") at /home/hs/ids/u-boot/common/console.c:479 #1 0x07f88c4c in parse_stream (end_trigger=10, input=0x775fe00, ctx=0x775fd60, dest=0x775fd7c) at /home/hs/ids/u-boot/common/hush.c:2942 this leads, if flash is erased, in a crash ... try to find out more ... This problem seems a toolchain problem, as I tried older U-Boot versions with eldk 5.5 on this board, and all versions break ... I have no other mpc83xx board handy ... can somebody try this scenario on a mpc83xx based board? Kim? Current U-Boot does work fine on a mpc52xx based board compiled with eldk 5.5, so it seems a mpc83xx specific problem? Heiko Schocher (4): bootm: make use of legacy image format configurable mpc8313, signed fit: enable legacy image format on ids8313 board lib, fdt: move fdtdec_get_int() out of lib/fdtdec.c mpc8313: add CONFIG_SYS_GENERIC_BOARD to ids8313 board README | 18 ++++++++++++++++++ common/cmd_bootm.c | 14 ++++++++++++++ common/cmd_disk.c | 4 ++++ common/cmd_fdc.c | 4 ++++ common/cmd_fpga.c | 2 ++ common/cmd_nand.c | 4 ++++ common/cmd_source.c | 4 ++++ common/cmd_ximg.c | 7 ++++++- common/image-fdt.c | 10 ++++++++-- common/image.c | 23 ++++++++++++++++------- doc/uImage.FIT/signature.txt | 3 +++ include/config_defaults.h | 8 ++++++++ include/configs/ids8313.h | 4 +++- include/image.h | 2 ++ lib/Makefile | 1 + lib/fdtdec.c | 36 ------------------------------------ lib/fdtdec_common.c | 33 +++++++++++++++++++++++++++++++++ tools/fdtdec.c | 1 + 18 files changed, 131 insertions(+), 47 deletions(-) create mode 100644 lib/fdtdec_common.c -- 1.8.3.1

3 9

[U-Boot] [RFC PATCH] fpga: Added support to load bit stream from SD/MMC
by Michal Simek 15 May '14

15 May '14

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Added support to load a bitstream image in chunks by reading it in chunks from SD/MMC. Command format: loadfs [dev] [address] [image size] [blocksize] <interface> [<dev[:part]>] <filename> Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- We have tested just FAT case but I am sending this as RFC to give some inputs from you. The reason for this command is that when u-boot running from OCM on zynq there is just 192kB for u-boot itself and there must be an option to load bitstream to PL because there full DDR controller. Bitstreams are bigger and bigger and reading it with chunks is only one way how to do it. This is also necessary to do it for u-boot SPL when we add fpga support there. The question is if this is the way how to extend fpga command because loadfs should be fpga subcommand. This patch is based on this branch. http://git.denx.de/?p=u-boot/u-boot-microblaze.git;a=shortlog;h=refs/heads/… Thanks for your comments, Michal --- common/cmd_fpga.c | 41 +++++++++++++++++++++ drivers/fpga/fpga.c | 28 ++++++++++++++ drivers/fpga/xilinx.c | 16 ++++++++ drivers/fpga/zynqpl.c | 85 +++++++++++++++++++++++++++++++++++++++++++ include/configs/zynq-common.h | 1 + include/fpga.h | 9 +++++ include/xilinx.h | 3 ++ 7 files changed, 183 insertions(+) diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 802f3ec..3add0c3 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> #include <fpga.h> +#include <fs.h> #include <malloc.h> /* Local functions */ @@ -25,6 +26,7 @@ static int fpga_get_op(char *opstr); #define FPGA_LOADMK 4 #define FPGA_LOADP 5 #define FPGA_LOADBP 6 +#define FPGA_LOADFS 7 /* ------------------------------------------------------------------------- */ /* command form: @@ -47,6 +49,11 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) const char *fit_uname = NULL; ulong fit_addr; #endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + fpga_fs_info fpga_fsinfo; + + fpga_fsinfo.fstype = FS_TYPE_FAT; +#endif if (devstr) dev = (int) simple_strtoul(devstr, NULL, 16); @@ -54,6 +61,14 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fpga_data = (void *)simple_strtoul(datastr, NULL, 16); switch (argc) { +#if defined(CONFIG_CMD_FPGA_LOADFS) + case 9: + fpga_fsinfo.blocksize = (unsigned int) + simple_strtoul(argv[5], NULL, 16); + fpga_fsinfo.interface = argv[6]; + fpga_fsinfo.dev_part = argv[7]; + fpga_fsinfo.filename = argv[8]; +#endif case 5: /* fpga <op> <dev> <data> <datasize> */ data_size = simple_strtoul(argv[4], NULL, 16); @@ -122,6 +137,13 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) case FPGA_NONE: case FPGA_INFO: break; +#if defined(CONFIG_CMD_FPGA_LOADFS) + case FPGA_LOADFS: + /* Blocksize can be zero */ + if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part || + !fpga_fsinfo.filename || fpga_fsinfo.fstype == FS_TYPE_ANY) + wrong_parms = 1; +#endif case FPGA_LOAD: case FPGA_LOADP: case FPGA_LOADB: @@ -171,6 +193,12 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) break; #endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + case FPGA_LOADFS: + rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo); + break; +#endif + #if defined(CONFIG_CMD_FPGA_LOADMK) case FPGA_LOADMK: switch (genimg_get_format(fpga_data)) { @@ -287,6 +315,10 @@ static int fpga_get_op(char *opstr) else if (!strcmp("loadbp", opstr)) op = FPGA_LOADBP; #endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + else if (!strcmp("loadfs", opstr)) + op = FPGA_LOADFS; +#endif #if defined(CONFIG_CMD_FPGA_LOADMK) else if (!strcmp("loadmk", opstr)) op = FPGA_LOADMK; @@ -300,7 +332,11 @@ static int fpga_get_op(char *opstr) return op; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +U_BOOT_CMD(fpga, 9, 1, do_fpga, +#else U_BOOT_CMD(fpga, 6, 1, do_fpga, +#endif "loadable FPGA image support", "[operation type] [device number] [image address] [image size]\n" "fpga operations:\n" @@ -318,6 +354,11 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga, "Load device from bitstream buffer with partial bitstream" "(Xilinx only)\n" #endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + "Load device from filesystem (FAT by default) (Xilinx only)\n" + " loadfs [dev] [address] [image size] [blocksize] <interface>\n" + " [<dev[:part]>] <filename>\n" +#endif #if defined(CONFIG_CMD_FPGA_LOADMK) " loadmk [dev] [address]\tLoad device generated with mkimage" #if defined(CONFIG_FIT) diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index e770950..37946d5 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -180,6 +180,34 @@ int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, return FPGA_FAIL; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + const fpga_desc *desc = fpga_validate(devnum, buf, size, + (char *)__func__); + + if (desc) { + switch (desc->devtype) { + case fpga_xilinx: +#if defined(CONFIG_FPGA_XILINX) + ret_val = xilinx_loadfs(desc->devdesc, buf, size, + fpga_fsinfo); +#else + fpga_no_sup((char *)__func__, "Xilinx devices"); +#endif + break; + default: + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); + } + } + + return ret_val; +} +#endif + /* * Generic multiplexing code */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index ab9f517..3795c1a 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -142,6 +142,22 @@ int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, return desc->operations->load(desc, buf, bsize, bstype); } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo) +{ + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); + return FPGA_FAIL; + } + + if (!desc->operations->loadfs) + return FPGA_FAIL; + + return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); +} +#endif + int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { if (!xilinx_validate (desc, (char *)__FUNCTION__)) { diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 915f077..7834e2f 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> +#include <fs.h> #include <zynqpl.h> #include <linux/sizes.h> #include <asm/arch/hardware.h> @@ -398,6 +399,87 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_SUCCESS; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fsinfo) +{ + unsigned long ts; /* Timestamp */ + u32 isr_status, swap; + u32 partialbit = 0; + u32 blocksize; + u32 pos = 0; + int fstype; + char *interface, *dev_part, *filename; + + blocksize = fsinfo->blocksize; + interface = fsinfo->interface; + dev_part = fsinfo->dev_part; + filename = fsinfo->filename; + fstype = fsinfo->fstype; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + + if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, + &partialbit)) + return FPGA_FAIL; + + dcache_disable(); + + do { + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2, + 0xffffffff, 0)) + return FPGA_FAIL; + + bsize -= blocksize; + pos += blocksize; + + if (fs_set_blk_dev(interface, dev_part, FS_TYPE_FAT)) + return FPGA_FAIL; + + if (bsize > blocksize) { + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + } else { + if (fs_read(filename, (u32) buf, pos, bsize) < 0) + return FPGA_FAIL; + } + } while (bsize > blocksize); + + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; + + dcache_enable(); + + isr_status = readl(&devcfg_base->int_sts); + + /* Check FPGA configuration completion */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for FPGA to config\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } + + debug("%s: FPGA config done\n", __func__); + + if (!partialbit) + zynq_slcr_devcfg_enable(); + + return FPGA_SUCCESS; +} +#endif + static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; @@ -405,6 +487,9 @@ static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) struct xilinx_fpga_op zynq_op = { .load = zynq_load, +#if defined(CONFIG_CMD_FPGA_LOADFS) + .loadfs = zynq_loadfs, +#endif .dump = zynq_dump, .info = zynq_info, }; diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index af420d1..8e0f935 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -217,6 +217,7 @@ #define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_FPGA_LOADP #define CONFIG_CMD_FPGA_LOADBP +#define CONFIG_CMD_FPGA_LOADFS /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT diff --git a/include/fpga.h b/include/fpga.h index 49efd37..914024c 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -35,6 +35,13 @@ typedef struct { /* typedef fpga_desc */ void *devdesc; /* real device descriptor */ } fpga_desc; /* end, typedef fpga_desc */ +typedef struct { /* typedef fpga_desc */ + unsigned int blocksize; + char *interface; + char *dev_part; + char *filename; + int fstype; +} fpga_fs_info; typedef enum { BIT_FULL = 0, @@ -47,6 +54,8 @@ extern int fpga_add(fpga_type devtype, void *desc); extern int fpga_count(void); extern int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype); +extern int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo); extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype); extern int fpga_dump(int devnum, const void *buf, size_t bsize); diff --git a/include/xilinx.h b/include/xilinx.h index 9600432..774487e 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -46,6 +46,7 @@ typedef struct { /* typedef xilinx_desc */ struct xilinx_fpga_op { int (*load)(xilinx_desc *, const void *, size_t, bitstream_type); + int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *); int (*dump)(xilinx_desc *, const void *, size_t); int (*info)(xilinx_desc *); }; @@ -56,6 +57,8 @@ int xilinx_load(xilinx_desc *desc, const void *image, size_t size, bitstream_type bstype); int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); int xilinx_info(xilinx_desc *desc); +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo); /* Board specific implementation specific function types *********************************************************************/ -- 1.8.2.3

3 3

[U-Boot] i.MX tree way behind master
by Otavio Salvador 15 May '14

15 May '14

Hello Stefano, Is it possible for you to ask for a pull request in i.MX tree and get it in sync with ARM one? Regards, -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750

2 1

[U-Boot] [PATCH][v2] powerpc/t4qds: Add alternate serdes protocols to align with A-007186
by shh.xie＠gmail.com 15 May '14

15 May '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes for V2: refine the commit message. arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 172 ++++++++++++++++++++++++++++++++ board/freescale/t4qds/eth.c | 20 ++++ board/freescale/t4qds/t4240qds.c | 27 +++++ 3 files changed, 219 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 1f99a0a..74c4c81 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = { HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {37, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, {38, {NONE, NONE, QSGMII_FM1_B, NONE, NONE, NONE, QSGMII_FM1_A, NONE}}, + {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, + {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, + {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, @@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = { XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {37, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, NONE, QSGMII_FM2_A, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, NONE, NONE, QSGMII_FM2_A, NONE} }, + {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {55, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, XFI_FM2_MAC10, XFI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = { }; static const struct serdes_config serdes3_cfg_tbl[] = { /* SerDes 3 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, + {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, + {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2}}, + {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2}}, + {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, + {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, @@ -161,13 +244,21 @@ static const struct serdes_config serdes3_cfg_tbl[] = { }; static const struct serdes_config serdes4_cfg_tbl[] = { /* SerDes 4 */ + {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} }, {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, + {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, + {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} }, {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} }, {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, + {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, + {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} }, {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} }, {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} @@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = { HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, + {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {37, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, {38, {NONE, NONE, QSGMII_FM1_B, NONE, NONE, NONE, QSGMII_FM1_A, NONE} }, {} }; static const struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ + {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, NONE, NONE} }, + {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {37, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, QSGMII_FM1_A, NONE, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, NONE, QSGMII_FM1_A, NONE, NONE} }, + {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {55, {NONE, XFI_FM1_MAC10, + XFI_FM2_MAC10, NONE, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {56, {NONE, XFI_FM1_MAC10, XFI_FM2_MAC10, NONE, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -265,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = { }; static const struct serdes_config serdes3_cfg_tbl[] = { /* SerDes 3 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, + {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, + {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, + {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, + {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, @@ -289,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = { }; static const struct serdes_config serdes4_cfg_tbl[] = { /* SerDes 4 */ + {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, + {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, + {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, + {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, + {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} }, {} diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 24cf907..6210e46 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -449,7 +449,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot1 and Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); @@ -465,6 +467,7 @@ int board_eth_init(bd_t *bis) slot_qsgmii_phyaddr[1][2]); } break; + case 37: case 38: fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); @@ -479,8 +482,11 @@ int board_eth_init(bd_t *bis) slot_qsgmii_phyaddr[1][3]); } break; + case 39: case 40: + case 45: case 46: + case 47: case 48: fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); @@ -585,12 +591,17 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); break; + case 6: case 7: + case 12: case 13: case 14: + case 15: case 16: + case 21: case 22: case 23: + case 24: case 25: case 26: /* XAUI/HiGig in Slot3, SGMII in Slot4 */ @@ -600,7 +611,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -612,6 +625,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); break; + case 37: case 38: /* QSGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -623,8 +637,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); break; + case 39: case 40: + case 45: case 46: + case 47: case 48: /* SGMII in Slot3 */ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); @@ -637,8 +654,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 49: case 50: + case 51: case 52: + case 53: case 54: fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 79b770b..fe1bc7f 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -354,14 +354,18 @@ int config_frontside_crossbar_vsc3316(void) FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; switch (srds_prtcl_s1) { + case 37: case 38: /* swap first lane and third lane on slot1 */ vsc3316_fsm1_tx[0][1] = 14; vsc3316_fsm1_tx[6][1] = 0; vsc3316_fsm1_rx[1][1] = 2; vsc3316_fsm1_rx[6][1] = 13; + case 39: case 40: + case 45: case 46: + case 47: case 48: /* swap first lane and third lane on slot2 */ vsc3316_fsm1_tx[2][1] = 8; @@ -382,17 +386,24 @@ int config_frontside_crossbar_vsc3316(void) FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; switch (srds_prtcl_s2) { + case 37: case 38: /* swap first lane and third lane on slot3 */ vsc3316_fsm2_tx[2][1] = 11; vsc3316_fsm2_tx[5][1] = 4; vsc3316_fsm2_rx[2][1] = 9; vsc3316_fsm2_rx[4][1] = 7; + case 39: case 40: + case 45: case 46: + case 47: case 48: + case 49: case 50: + case 51: case 52: + case 53: case 54: /* swap first lane and third lane on slot4 */ vsc3316_fsm2_tx[6][1] = 3; @@ -425,6 +436,7 @@ int config_backside_crossbar_mux(void) case 0: /* SerDes3 is not enabled */ break; + case 1: case 2: case 9: case 10: @@ -434,13 +446,20 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD3MX_SLOT5; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 3: case 4: + case 5: case 6: + case 7: case 8: + case 11: case 12: + case 13: case 14: + case 15: case 16: case 17: + case 18: case 19: case 20: /* SD3(4:7) => SLOT6(0:3) */ @@ -462,6 +481,7 @@ int config_backside_crossbar_mux(void) case 0: /* SerDes4 is not enabled */ break; + case 1: case 2: /* 10b, SD4(0:7) => SLOT7(0:7) */ brdcfg = QIXIS_READ(brdcfg[12]); @@ -469,8 +489,11 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD4MX_SLOT7; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 3: case 4: + case 5: case 6: + case 7: case 8: /* x1b, SD4(4:7) => SLOT8(0:3) */ brdcfg = QIXIS_READ(brdcfg[12]); @@ -478,9 +501,13 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD4MX_SLOT8; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 9: case 10: + case 11: case 12: + case 13: case 14: + case 15: case 16: case 18: /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ -- 1.8.0

1 0

[U-Boot] [PATCH] powerpc/t4qds: Add alternate serdes protocols to align with A-007186
by shh.xie＠gmail.com 15 May '14

15 May '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> A-007186: SerDes Ring VCO does not maintain lock throughout specified temperature range. Option 1 of the workaround states: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. So add the alternate serdes protocols by duplicating setting of the originals. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 172 ++++++++++++++++++++++++++++++++ board/freescale/t4qds/eth.c | 20 ++++ board/freescale/t4qds/t4240qds.c | 27 +++++ 3 files changed, 219 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 1f99a0a..74c4c81 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = { HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {37, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, {38, {NONE, NONE, QSGMII_FM1_B, NONE, NONE, NONE, QSGMII_FM1_A, NONE}}, + {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, + {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, + {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE} }, {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, NONE, NONE, QSGMII_FM1_A, NONE}}, @@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = { XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {37, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, NONE, QSGMII_FM2_A, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, NONE, NONE, QSGMII_FM2_A, NONE} }, + {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, QSGMII_FM2_A, NONE} }, + {55, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, XFI_FM2_MAC10, XFI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = { }; static const struct serdes_config serdes3_cfg_tbl[] = { /* SerDes 3 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, + {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, + {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2}}, + {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2}}, + {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, + {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1}}, {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, @@ -161,13 +244,21 @@ static const struct serdes_config serdes3_cfg_tbl[] = { }; static const struct serdes_config serdes4_cfg_tbl[] = { /* SerDes 4 */ + {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} }, {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, + {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, + {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} }, {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} }, {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, + {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, + {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} }, {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} }, {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} @@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = { HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, + {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {37, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, {38, {NONE, NONE, QSGMII_FM1_B, NONE, NONE, NONE, QSGMII_FM1_A, NONE} }, {} }; static const struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ + {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = { HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, NONE, NONE} }, + {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {37, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, QSGMII_FM1_A, NONE, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, NONE, QSGMII_FM1_A, NONE, NONE} }, + {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, NONE, QSGMII_FM1_A, NONE, NONE} }, + {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, NONE, NONE} }, + {55, {NONE, XFI_FM1_MAC10, + XFI_FM2_MAC10, NONE, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {56, {NONE, XFI_FM1_MAC10, XFI_FM2_MAC10, NONE, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, @@ -265,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = { }; static const struct serdes_config serdes3_cfg_tbl[] = { /* SerDes 3 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, + {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, + {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, + {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, PCIE2, PCIE2, PCIE2, PCIE2} }, + {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, + {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, SRIO1, SRIO1, SRIO1, SRIO1} }, {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, @@ -289,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = { }; static const struct serdes_config serdes4_cfg_tbl[] = { /* SerDes 4 */ + {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, + {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, + {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, + {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, + {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} }, {} diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 24cf907..6210e46 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -449,7 +449,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot1 and Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); @@ -465,6 +467,7 @@ int board_eth_init(bd_t *bis) slot_qsgmii_phyaddr[1][2]); } break; + case 37: case 38: fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); @@ -479,8 +482,11 @@ int board_eth_init(bd_t *bis) slot_qsgmii_phyaddr[1][3]); } break; + case 39: case 40: + case 45: case 46: + case 47: case 48: fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); @@ -585,12 +591,17 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); break; + case 6: case 7: + case 12: case 13: case 14: + case 15: case 16: + case 21: case 22: case 23: + case 24: case 25: case 26: /* XAUI/HiGig in Slot3, SGMII in Slot4 */ @@ -600,7 +611,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -612,6 +625,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); break; + case 37: case 38: /* QSGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -623,8 +637,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); break; + case 39: case 40: + case 45: case 46: + case 47: case 48: /* SGMII in Slot3 */ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); @@ -637,8 +654,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 49: case 50: + case 51: case 52: + case 53: case 54: fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 79b770b..fe1bc7f 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -354,14 +354,18 @@ int config_frontside_crossbar_vsc3316(void) FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; switch (srds_prtcl_s1) { + case 37: case 38: /* swap first lane and third lane on slot1 */ vsc3316_fsm1_tx[0][1] = 14; vsc3316_fsm1_tx[6][1] = 0; vsc3316_fsm1_rx[1][1] = 2; vsc3316_fsm1_rx[6][1] = 13; + case 39: case 40: + case 45: case 46: + case 47: case 48: /* swap first lane and third lane on slot2 */ vsc3316_fsm1_tx[2][1] = 8; @@ -382,17 +386,24 @@ int config_frontside_crossbar_vsc3316(void) FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; switch (srds_prtcl_s2) { + case 37: case 38: /* swap first lane and third lane on slot3 */ vsc3316_fsm2_tx[2][1] = 11; vsc3316_fsm2_tx[5][1] = 4; vsc3316_fsm2_rx[2][1] = 9; vsc3316_fsm2_rx[4][1] = 7; + case 39: case 40: + case 45: case 46: + case 47: case 48: + case 49: case 50: + case 51: case 52: + case 53: case 54: /* swap first lane and third lane on slot4 */ vsc3316_fsm2_tx[6][1] = 3; @@ -425,6 +436,7 @@ int config_backside_crossbar_mux(void) case 0: /* SerDes3 is not enabled */ break; + case 1: case 2: case 9: case 10: @@ -434,13 +446,20 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD3MX_SLOT5; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 3: case 4: + case 5: case 6: + case 7: case 8: + case 11: case 12: + case 13: case 14: + case 15: case 16: case 17: + case 18: case 19: case 20: /* SD3(4:7) => SLOT6(0:3) */ @@ -462,6 +481,7 @@ int config_backside_crossbar_mux(void) case 0: /* SerDes4 is not enabled */ break; + case 1: case 2: /* 10b, SD4(0:7) => SLOT7(0:7) */ brdcfg = QIXIS_READ(brdcfg[12]); @@ -469,8 +489,11 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD4MX_SLOT7; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 3: case 4: + case 5: case 6: + case 7: case 8: /* x1b, SD4(4:7) => SLOT8(0:3) */ brdcfg = QIXIS_READ(brdcfg[12]); @@ -478,9 +501,13 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD4MX_SLOT8; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 9: case 10: + case 11: case 12: + case 13: case 14: + case 15: case 16: case 18: /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ -- 1.8.0

1 0

[U-Boot] [PATCH v2] sandbox: set sandbox's vendor to null
by Masahiro Yamada 15 May '14

15 May '14

Because sandbox is not a real hardware, setting vendor=sandbox is almost meaningless. This commit sets sandbox's vendor field to '-'. It is a good thing that it decreases one level directory hierarchy. The files board/sandbox/sandbox/* have been moved to board/sandbox/*. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Rebase board/sandbox/{sandbox => }/Makefile | 0 board/sandbox/{sandbox => }/README.sandbox | 0 board/sandbox/{sandbox => }/sandbox.c | 0 boards.cfg | 2 +- 4 files changed, 1 insertion(+), 1 deletion(-) rename board/sandbox/{sandbox => }/Makefile (100%) rename board/sandbox/{sandbox => }/README.sandbox (100%) rename board/sandbox/{sandbox => }/sandbox.c (100%) diff --git a/board/sandbox/sandbox/Makefile b/board/sandbox/Makefile similarity index 100% rename from board/sandbox/sandbox/Makefile rename to board/sandbox/Makefile diff --git a/board/sandbox/sandbox/README.sandbox b/board/sandbox/README.sandbox similarity index 100% rename from board/sandbox/sandbox/README.sandbox rename to board/sandbox/README.sandbox diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox.c similarity index 100% rename from board/sandbox/sandbox/sandbox.c rename to board/sandbox/sandbox.c diff --git a/boards.cfg b/boards.cfg index 6aea684..59b5c4c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1182,7 +1182,7 @@ Active powerpc ppc4xx - xilinx ppc405-generic Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda(a)uam.es> -Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg(a)chromium.org> +Active sandbox sandbox - - sandbox sandbox - Simon Glass <sjg(a)chromium.org> Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com>:Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy(a)renesas.com> Active sh sh2 - renesas rsk7269 rsk7269 - - -- 1.8.3.2

2 1

[U-Boot] [PATCH] Revert "sandbox: move source files from board/ to arch/sandbox/"
by Masahiro Yamada 15 May '14

15 May '14

This reverts commit 258060905e04fe2eb509756ef3b37e23e220a2d6. Conflicts: boards.cfg Wrong patch 25806090 was applied by accident. Revert it. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Simon Glass <sjg(a)chromium.org> --- arch/sandbox/lib/Makefile | 2 +- board/sandbox/sandbox/Makefile | 7 +++++++ {doc => board/sandbox/sandbox}/README.sandbox | 0 {arch/sandbox/lib => board/sandbox/sandbox}/sandbox.c | 0 boards.cfg | 2 +- 5 files changed, 9 insertions(+), 2 deletions(-) create mode 100644 board/sandbox/sandbox/Makefile rename {doc => board/sandbox/sandbox}/README.sandbox (100%) rename {arch/sandbox/lib => board/sandbox/sandbox}/sandbox.c (100%) diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index 6480ebf..4c1a38d 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -8,4 +8,4 @@ # -obj-y += interrupts.o sandbox.o +obj-y += interrupts.o diff --git a/board/sandbox/sandbox/Makefile b/board/sandbox/sandbox/Makefile new file mode 100644 index 0000000..a0b9880 --- /dev/null +++ b/board/sandbox/sandbox/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := sandbox.o diff --git a/doc/README.sandbox b/board/sandbox/sandbox/README.sandbox similarity index 100% rename from doc/README.sandbox rename to board/sandbox/sandbox/README.sandbox diff --git a/arch/sandbox/lib/sandbox.c b/board/sandbox/sandbox/sandbox.c similarity index 100% rename from arch/sandbox/lib/sandbox.c rename to board/sandbox/sandbox/sandbox.c diff --git a/boards.cfg b/boards.cfg index 9d90550..6aea684 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1182,7 +1182,7 @@ Active powerpc ppc4xx - xilinx ppc405-generic Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda(a)uam.es> -Active sandbox sandbox - - <none> sandbox - Simon Glass <sjg(a)chromium.org> +Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg(a)chromium.org> Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com>:Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy(a)renesas.com> Active sh sh2 - renesas rsk7269 rsk7269 - - -- 1.8.3.2

2 1

[U-Boot] [PATCHv3 00/13] mmc: exynos: code cleanup and support DDR mode
by Jaehoon Chung 15 May '14

15 May '14

If card and host are supported DDR mode, then it can be used the DDR mode. This patch-set has dependency about beomho's patch-set. (Based-on u-boot-samsung repository) It's result for loading image. sdhci controller ->5260488 bytes read in 259 ms (19.4 MiB/s) dwmmc controller without DDR mode -> 5260488 bytes read in 202 ms (24.8 MiB/s) dwmmc controller with DDR mode -> 5260488 bytes read in 118 ms (42.5 MiB/s) Download the 400M image with lthor. sdhci controller -> 59.4sec (Avg 6.95 MB/s) dwmmc controller without DDR mode -> 61.6sec (Avg 6.72MB/s) dwmmc controller with DDR mode -> 60.4sec (Avg 6.85MB/s) Beomho Seo (3): arm: exynos: pinmux: add sdmmc4 gpio configratuion arm: exynos: clock: Remove exynos4x12_set_mmc_clk function board: trats2: Enable device tree on Trats2 Jaehoon Chung (10): ARM: exynos: board: change the mmc/sd init sequence ARM: exynos: clock: modify the set_mmc_clk for exynos4 mmc: exynos_dw_mmc: restore the property into host mmc: remove the unnecessary define and fix the wrong bit control mmc: support the DDR mode for eMMC mmc: dw_mmc: support the DDR mode ARM: dts: exnyos: enable dw-mmc controller mmc: exynos_dw_mmc: enable the DDR mode ARM: exynos4: enable the dwmmc configuration mmc: s5p_sdhci: add the s5p_sdhci_core_init function arch/arm/cpu/armv7/exynos/clock.c | 45 ++----- arch/arm/cpu/armv7/exynos/pinmux.c | 18 ++- arch/arm/dts/exynos4.dtsi | 8 ++ arch/arm/dts/exynos4412-trats2.dts | 12 ++ arch/arm/include/asm/arch-exynos/clk.h | 5 + board/samsung/common/board.c | 13 +- drivers/mmc/dw_mmc.c | 12 +- drivers/mmc/exynos_dw_mmc.c | 209 ++++++++++++++++++++------------ drivers/mmc/mmc.c | 16 ++- drivers/mmc/s5p_sdhci.c | 42 +++---- include/configs/exynos4-dt.h | 3 + include/dwmmc.h | 5 + include/mmc.h | 25 ++-- 13 files changed, 250 insertions(+), 163 deletions(-) -- 1.7.9.5

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[U-Boot] RFC: i.MX UART failures with baud-rate mis-match
by Eric Nelson 15 May '14

15 May '14

We've identified an issue with i.MX UARTs which causes an infinite stream of input characters when certain input characters with an incorrect baud rate are received. The details and a couple of ways to reproduce are in this thread on i.MX Community: https://community.freescale.com/message/403254 We'd like to get some feedback from other users of i.MX to see whether the problem exists on especially i.MX51 and i.MX3x. The easiest way to reproduce the problem is to apply patch 1 in the series, change a serial console to 19200, and send a lower-case 'b' to the serial port at 115200 baud: U-Boot > setenv baudrate 19200 ## Switch baudrate to 19200 bps and press ENTER ... ... hit a 'b' at 115200 and you should see a spew of garbage. ... hit an 'a' and the spew should stop. This has been repeated on i.MX6Q, i.MX6S and i.MX53-based boards. Patch 2 of 2 should resolve the issue.

2 5

[U-Boot] [PATCH 1/2] drivers:dfu: dfu_flush(): add raw data flush to complete dfu write
by Przemyslaw Marczak 15 May '14

15 May '14

Before dfu write and flush operations separation, dfu write data was flushed by host download request with len of zero size. Since above change manually calling dfu write with zero size has non sense (e.g. in THOR). This should be done by flush operation. So now dfu_write_buffer_drain() is called in dfu_flush(). If there is any raw data to flush (like it can be in thor) then it will be physically written to medium. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> --- drivers/dfu/dfu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 51b1026..a938109 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -131,6 +131,10 @@ int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { int ret = 0; + ret = dfu_write_buffer_drain(dfu); + if (ret) + return ret; + if (dfu->flush_medium) ret = dfu->flush_medium(dfu); -- 1.9.1

2 2