November 2014 - U-Boot

[U-Boot] [PATCH v4 0/4] add support for new arch stv0991
by Vikas Manocha 25 Nov '14

25 Nov '14

This patchset add support for new arch stv0991. Changes in v4: - rebased to current master - added maintainers info Changes in v3: - removed period from commit messages Changes in v2: - corrected files license to GPL-2.0+ - replaced printf() usage with puts() for string print - sorted sourcing of board Kconfig Vikas Manocha (4): stv0991: Add basic stv0991 architecture support stv0991: enable ethernet support stv0991: default + misc command configs enabled stv0991: add maintainer information MAINTAINERS | 6 + arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/stv0991/Makefile | 9 ++ arch/arm/cpu/armv7/stv0991/clock.c | 41 +++++++ arch/arm/cpu/armv7/stv0991/lowlevel.S | 12 ++ arch/arm/cpu/armv7/stv0991/pinmux.c | 62 +++++++++++ arch/arm/cpu/armv7/stv0991/reset.c | 26 +++++ arch/arm/cpu/armv7/stv0991/timer.c | 114 +++++++++++++++++++ arch/arm/include/asm/arch-stv0991/gpio.h | 22 ++++ arch/arm/include/asm/arch-stv0991/hardware.h | 73 ++++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 116 ++++++++++++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_creg.h | 95 ++++++++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_defs.h | 16 +++ arch/arm/include/asm/arch-stv0991/stv0991_gpt.h | 43 ++++++++ arch/arm/include/asm/arch-stv0991/stv0991_periph.h | 44 ++++++++ arch/arm/include/asm/arch-stv0991/stv0991_wdru.h | 28 +++++ board/st/stv0991/Kconfig | 23 ++++ board/st/stv0991/MAINTAINERS | 5 + board/st/stv0991/Makefile | 8 ++ board/st/stv0991/stv0991.c | 91 +++++++++++++++ configs/stv0991_defconfig | 3 + include/configs/stv0991.h | 88 +++++++++++++++ 22 files changed, 930 insertions(+) create mode 100644 arch/arm/cpu/armv7/stv0991/Makefile create mode 100644 arch/arm/cpu/armv7/stv0991/clock.c create mode 100644 arch/arm/cpu/armv7/stv0991/lowlevel.S create mode 100644 arch/arm/cpu/armv7/stv0991/pinmux.c create mode 100644 arch/arm/cpu/armv7/stv0991/reset.c create mode 100644 arch/arm/cpu/armv7/stv0991/timer.c create mode 100644 arch/arm/include/asm/arch-stv0991/gpio.h create mode 100644 arch/arm/include/asm/arch-stv0991/hardware.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_cgu.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_creg.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_defs.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_gpt.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_periph.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_wdru.h create mode 100644 board/st/stv0991/Kconfig create mode 100644 board/st/stv0991/MAINTAINERS create mode 100644 board/st/stv0991/Makefile create mode 100644 board/st/stv0991/stv0991.c create mode 100644 configs/stv0991_defconfig create mode 100644 include/configs/stv0991.h -- 1.7.9.5

4 13

[U-Boot] [PATCH 0/5] PL01x: baudrate & line control fixes
by Vikas Manocha 25 Nov '14

25 Nov '14

This patchset fixes the pl01x driver esp for pl011 baudrate & line control. Vikas Manocha (5): serial: pl01x: pass pl01x_type to set baudrate serial: pl01x: fix pl011 baud rate configuration serial: pl01x: move all line control at same place serial: pl01x: disable as per type of pl01x serial: pl01x: avoid pl01x type check two times drivers/serial/serial_pl01x.c | 46 +++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 22 deletions(-) -- 1.7.9.5

3 16

[U-Boot] [PATCH v2 1/5] arm: ls102xa: Add snoop disable for slave port 0, 1 and 2
by Alison Wang 25 Nov '14

25 Nov '14

From: Jason Jin <Jason.Jin(a)freescale.com> Disable the snoop for slave interface 0, 1 and 2 to avoid the interleaving on the CCI400 BUS. Signed-off-by: Jason Jin <Jason.Jin(a)freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- Change log: v2: Add tag "arm: ls102xa:" in the subject. arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + board/freescale/ls1021aqds/ls1021aqds.c | 7 +++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 7995fe2..a1f4fdb 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -448,6 +448,7 @@ struct ccsr_ddr { #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..e32dbeb 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -220,6 +220,13 @@ int board_init(void) /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b522ff2..811c911 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -272,6 +272,16 @@ int board_early_init_f(void) int board_init(void) { + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); config_serdes_mux(); -- 2.1.0.27.g96db324

2 9

[U-Boot] [PATCH 2/2] ls1: config: Enable USB EHCI Host on LS1021AQDS
by Nikhil Badola 25 Nov '14

25 Nov '14

Enable USB EHCI Host on LS1021AQDS Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- include/configs/ls1021aqds.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bb47813..fd43a3e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -273,6 +273,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_GENERIC_MMC /* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +/* * eTSEC */ #define CONFIG_TSEC_ENET -- 1.7.11.7

2 1

[U-Boot] [PATCH 1/2] drivers: usb: fsl: Define USB configs for LS102XA
by Nikhil Badola 25 Nov '14

25 Nov '14

Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR, CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ++++ include/usb/ehci-fsl.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..cbf41da 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -25,7 +25,10 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) +#define CONFIG_SYS_LS102XA_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 @@ -76,6 +79,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #else #error SoC not defined #endif diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index dd77ad6..897018b 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -163,6 +163,9 @@ #elif defined(CONFIG_MPC512X) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 +#elif defined(CONFIG_LS102XA) +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB2_ADDR 0 #endif /* -- 1.7.11.7

2 1

[U-Boot] [PATCH] drivers : usb: fsl: Implement usb Erratum A007798 workaround
by Nikhil Badola 25 Nov '14

25 Nov '14

Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- Depends on patch https://patchwork.ozlabs.org/patch/394797/ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/usb/host/ehci-fsl.c | 3 +-- include/fsl_usb.h | 11 +++++++++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 349ce52..fe3eb06 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -294,6 +294,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a007075()) puts("Work-around for Erratum A007075 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007798 + if (has_erratum_a007798()) + puts("Work-around for Erratum A007798 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 712f2ef..486bc53 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -677,6 +677,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007798 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index c125e2c..7101202 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -131,8 +131,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, in_le32(&ehci->usbmode); - if (SVR_SOC_VER(get_svr()) == SVR_T4240 && - IS_SVR_REV(get_svr(), 2, 0)) + if (has_erratum_a007798()) set_txfifothresh(ehci, TXFIFOTHRESH); return 0; diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 66f8934..e4902aa 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -139,6 +139,12 @@ static inline bool has_erratum_a007075(void) } return false; } + +static inline bool has_erratum_a007798(void) +{ + return SVR_SOC_VER(get_svr()) == SVR_T4240 && + IS_SVR_REV(get_svr(), 2, 0); +} #else static inline bool has_erratum_a006261(void) { @@ -150,5 +156,10 @@ static inline bool has_erratum_a007075(void) return false; } +static inline bool has_erratum_a007798(void) +{ + return false; +} + #endif #endif /*_ASM_FSL_USB_H_ */ -- 1.7.11.7

2 1

[U-Boot] [PATCH 1/3] drivers: usb: fsl: Move USB Errata checking code
by Nikhil Badola 25 Nov '14

25 Nov '14

Move USB Errata checking code from "arch/powerpc" to architecture independent file "fsl_usb.h" so that errata(s) become independent of the architecture. For each erratum checking function for PPC arch, define a nop function for non PPC arch for successful compilation in either case Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 1 + arch/powerpc/include/asm/fsl_errata.h | 55 ----------------------------- drivers/usb/host/ehci-fsl.c | 2 +- include/fsl_usb.h | 66 +++++++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+), 56 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3a04a89..349ce52 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -9,6 +9,7 @@ #include <linux/compiler.h> #include <asm/fsl_errata.h> #include <asm/processor.h> +#include <fsl_usb.h> #include "fsl_corenet_serdes.h" #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 64da4bb..b9e2fb0 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -26,59 +26,4 @@ static inline bool has_erratum_a006379(void) return false; } #endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 -static inline bool has_erratum_a006261(void) -{ - u32 svr = get_svr(); - u32 soc = SVR_SOC_VER(svr); - - switch (soc) { - case SVR_P1010: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_P2041: - case SVR_P2040: - return IS_SVR_REV(svr, 1, 0) || - IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); - case SVR_P3041: - return IS_SVR_REV(svr, 1, 0) || - IS_SVR_REV(svr, 1, 1) || - IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); - case SVR_P5010: - case SVR_P5020: - case SVR_P5021: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_T4240: - case SVR_T4160: - case SVR_T4080: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_T1040: - return IS_SVR_REV(svr, 1, 0); - case SVR_T2080: - case SVR_T2081: - return IS_SVR_REV(svr, 1, 0); - case SVR_P5040: - return IS_SVR_REV(svr, 1, 0); - } - - return false; -} -#endif - -static inline bool has_erratum_a007075(void) -{ - u32 svr = get_svr(); - u32 soc = SVR_SOC_VER(svr); - - switch (soc) { - case SVR_B4860: - case SVR_B4420: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_P1010: - return IS_SVR_REV(svr, 1, 0); - case SVR_P4080: - return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); - } - return false; -} #endif diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 45062e6..d5361d7 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -14,7 +14,7 @@ #include <asm/io.h> #include <usb/ehci-fsl.h> #include <hwconfig.h> -#include <asm/fsl_errata.h> +#include <fsl_usb.h> #include "ehci.h" diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 1a6c9c1..66f8934 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -85,4 +85,70 @@ struct ccsr_usb_phy { #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 #endif +/* USB Erratum Checking code */ +#ifdef CONFIG_PPC +static inline bool has_erratum_a006261(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P2041: + case SVR_P2040: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); + case SVR_P3041: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || + IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); + case SVR_P5010: + case SVR_P5020: + case SVR_P5021: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T4240: + case SVR_T4160: + case SVR_T4080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); + case SVR_P5040: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} + +static inline bool has_erratum_a007075(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + return false; +} +#else +static inline bool has_erratum_a006261(void) +{ + return false; +} + +static inline bool has_erratum_a007075(void) +{ + return false; +} + +#endif #endif /*_ASM_FSL_USB_H_ */ -- 1.7.11.7

2 1

[U-Boot] [PATCH v2] u_qe: add u_qe_upload_firmware for u_qe
by Zhao Qiang 25 Nov '14

25 Nov '14

Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- Changes for v2: - put u_qe functions under "#ifdef CONFIG_U_QE" drivers/qe/qe.c | 129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/qe/qe.h | 6 ++- 2 files changed, 133 insertions(+), 2 deletions(-) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 4de1881..bc94673 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -182,14 +182,16 @@ void qe_init(uint qe_base) qe_snums_init(); } +#ifdef CONFIG_U_QE void u_qe_init(void) { uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */ qe_immr = (qe_map_t *)qe_base; - qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); + u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); out_be32(&qe_immr->iram.iready, QE_IRAM_READY); } +#endif void qe_reset(void) { @@ -442,6 +444,131 @@ int qe_upload_firmware(const struct qe_firmware *firmware) return 0; } +#ifdef CONFIG_U_QE +/* + * Upload a microcode to the I-RAM at a specific address. + * + * See docs/README.qe_firmware for information on QE microcode uploading. + * + * Currently, only version 1 is supported, so the 'version' field must be + * set to 1. + * + * The SOC model and revision are not validated, they are only displayed for + * informational purposes. + * + * 'calc_size' is the calculated size, in bytes, of the firmware structure and + * all of the microcode structures, minus the CRC. + * + * 'length' is the size that the structure says it is, including the CRC. + */ +int u_qe_upload_firmware(const struct qe_firmware *firmware) +{ + unsigned int i; + unsigned int j; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; +#ifdef CONFIG_DEEP_SLEEP + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + if (!firmware) { + printf("Invalid address\n"); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Unsupported version\n"); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) { + printf("Invalid data\n"); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Invalid length\n"); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) { + printf("Firmware CRC is invalid\n"); + return -EIO; + } + + /* + * If the microcode calls for it, split the I-RAM. + */ + if (!firmware->split) { + out_be16(&qe_immr->cp.cercr, + in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR); + } + + if (firmware->soc.model) + printf("Firmware '%s' for %u V%u.%u\n", + firmware->id, be16_to_cpu(firmware->soc.model), + firmware->soc.major, firmware->soc.minor); + else + printf("Firmware '%s'\n", firmware->id); + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (ucode->code_offset) + qe_upload_microcode(firmware, ucode); + + /* Program the traps for this processor */ + for (j = 0; j < 16; j++) { + u32 trap = be32_to_cpu(ucode->traps[j]); + + if (trap) + out_be32(&qe_immr->rsp[i].tibcr[j], trap); + } + + /* Enable traps */ + out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr)); + } + + return 0; +} +#endif + struct qe_firmware_info *qe_get_firmware_info(void) { return qe_firmware_uploaded ? &qe_firmware_info : NULL; diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index 30484b8..33878f8 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -275,7 +275,6 @@ void *qe_muram_addr(uint offset); int qe_get_snum(void); void qe_put_snum(u8 snum); void qe_init(uint qe_base); -void u_qe_init(void); void qe_reset(void); void qe_assign_page(uint snum, uint para_ram_base); int qe_set_brg(uint brg, uint rate); @@ -286,4 +285,9 @@ void ft_qe_setup(void *blob); void qe_init(uint qe_base); void qe_reset(void); +#ifdef CONFIG_U_QE +void u_qe_init(void); +int u_qe_upload_firmware(const struct qe_firmware *firmware); +#endif + #endif /* __QE_H__ */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms
by Yuantian.Tang＠freescale.com 25 Nov '14

25 Nov '14

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> These patches depend on the following patches: https://patchwork.ozlabs.org/patch/389949/ https://patchwork.ozlabs.org/patch/389950/ https://patchwork.ozlabs.org/patch/389951/ https://patchwork.ozlabs.org/patch/389952/ Tang Yuantian (4): Add deep sleep framework support for Freescale QorIQ platforms ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation arm: ls102xa: Fixed a register definition error arm: ls1021qds: Add deep sleep support arch/arm/cpu/armv7/virt-v7.c | 14 +++--- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ddr.c | 7 +++ board/freescale/ls1021aqds/ls1021aqds.c | 60 +++++++++++++++++++++++ common/board_f.c | 10 ++++ drivers/ddr/fsl/arm_ddr_gen3.c | 48 ++++++++++++++++-- include/configs/ls1021aqds.h | 4 ++ include/fsl_ddr_sdram.h | 2 + include/fsl_sleep.h | 32 ++++++++++++ 9 files changed, 167 insertions(+), 12 deletions(-) create mode 100644 include/fsl_sleep.h -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 3/4] qe: add qe support to ls1021aqds
by Zhao Qiang 25 Nov '14

25 Nov '14

add qe support to ls1021aqds Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- board/freescale/ls1021aqds/ls1021aqds.c | 8 ++++++++ include/configs/ls1021aqds.h | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..3bc4a68 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -16,6 +16,9 @@ #include "../common/qixis.h" #include "ls1021aqds_qixis.h" +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -227,6 +230,11 @@ int board_init(void) fsl_serdes_init(); config_serdes_mux(); #endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + return 0; } diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 657e3b6..e19b81e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -67,6 +67,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_HAS_SERDES +#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI) +#define CONFIG_U_QE +#endif /* * IFC Definitions */ @@ -329,6 +332,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "fdt_high=0xcfffffff\0" \ -- 2.1.0.27.g96db324

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