November 2014 - U-Boot

[U-Boot] [PATCH 0/1] sun7i: Set ARMV7_BOOT_SEC_DEFAULT when OLD_SUNXI_KERNEL_COMPAT is set
by Hans de Goede 25 Nov '14

25 Nov '14

Hi Ian, Thanks for the quick review on the 2 display fixes. With Albert's pull-req of today the dependencies for this fix are going upstream as soon as Tom merges the pull-req. Can you review this one too please ? Thanks & Regards, Hans

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[U-Boot] [PATCH] ORIGEN: Enhance origen config to be more flexible on boot.
by Guillaume GARDET 25 Nov '14

25 Nov '14

This patch enhances the boot of origen board by adding support to ext2, bootz, initrd, bootenv loading and boot script. It still keeps the previous mmc load command if boot script fails. Signed-off-by: Guillaume GARDET <guillaume.gardet(a)free.fr> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- include/configs/origen.h | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/include/configs/origen.h b/include/configs/origen.h index 5d24916..2117fe1 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -61,6 +61,10 @@ #undef CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS @@ -68,7 +72,36 @@ #define COPY_BL2_FNPTR_ADDR 0x02020030 #define CONFIG_SPL_TEXT_BASE 0x02021410 -#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x40007000\0" \ + "rdaddr=0x48000000\0" \ + "kerneladdr=0x40007000\0" \ + "ramdiskaddr=0x48000000\0" \ + "console=ttySAC2,115200n8\0" \ + "mmcdev=0\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev}; " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv}; " \ + "run importbootenv; " \ + "fi; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi; " \ + "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " #define CONFIG_IDENT_STRING " for ORIGEN" -- 1.8.4.5

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[U-Boot] [PATCH] ARNDALE: Enhance arndale config to be more flexible on boot.
by Guillaume GARDET 25 Nov '14

25 Nov '14

This patch enhances the boot of arndale board by adding support to bootz, initrd, bootenv loading and boot script. It still keeps the previous mmc load command if boot script fails. Signed-off-by: Guillaume GARDET <guillaume.gardet(a)free.fr> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- include/configs/arndale.h | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 75f9933..edf9ee6 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -72,9 +72,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - /* SD/MMC configuration */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC @@ -103,8 +100,11 @@ #define CONFIG_CMD_MMC #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_NET #define CONFIG_CMD_HASH +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_CMD_BOOTZ #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK @@ -130,7 +130,37 @@ #define CONFIG_SPL_TEXT_BASE 0x02023400 #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + "loadaddr=0x40007000\0" \ + "rdaddr=0x4f000000\0" \ + "kerneladdr=0x40007000\0" \ + "ramdiskaddr=0x4f000000\0" \ + "console=ttySAC2,115200n8\0" \ + "mmcdev=1\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev}; " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv}; " \ + "run importbootenv; " \ + "fi; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi; " \ + "mmc read ${loadaddr} 451 2000; bootm ${loadaddr} " /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -- 1.8.4.5

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[U-Boot] [PATCH 0/2] No need for parade bridge on peach-pi
by Sjoerd Simons 25 Nov '14

25 Nov '14

With current u-boot-samsung HEAD on a peach-pi the following error is printed: exynos_lcd_power_on: ps8625_init() failed Which is not surprising given that chip does not exist on these boards. Sjoerd Simons (2): exynos5420: fix compilation without parade video Exynos5800: The Peach-Pi board does not have a Parade video bridge arch/arm/dts/exynos5800-peach-pi.dts | 5 ----- board/samsung/smdk5420/smdk5420.c | 4 ++++ include/configs/peach-pi.h | 2 -- 3 files changed, 4 insertions(+), 7 deletions(-) -- 2.1.3

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[U-Boot] [PATCH v2 0/2] dm: rpi: Move Raspberry Pi to use driver model
by Simon Glass 25 Nov '14

25 Nov '14

This series adds driver model support to the GPIO and serial drivers used by Raspberry Pi, and moves Raspberry Pi over to driver model. This requires adding driver model support to the pl01x serial driver, and replacing the bcm2835 GPIO driver with a driver model version (since there are no longer clients that don't use driver model). See u-boot-dm.git branch rpi-working for the tree this is based on. Changes in v2: - Adjust header file include to dm/platform_data/... - Add new patch to move script load address to 0x8000 Simon Glass (2): dm: rpi: Move serial to driver model dm: rpi: Move script load address to 0x8000 board/raspberrypi/rpi/rpi.c | 12 ++++++++++++ include/configs/rpi.h | 8 ++++---- 2 files changed, 16 insertions(+), 4 deletions(-) -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v2 0/30] x86: Add additional system setup for ivybridge
by Simon Glass 25 Nov '14

25 Nov '14

This series adds full support for the LPC (Low Pin Count) bridge, the PCH (Platform Controller Hub), PCI devices like USB and SATA and more CPU init support (turbo mode, etc.) With this series, chromebook_link can use SATA and USB at the command line. Changes in v2: - Adjust rtc_init() call to remove the parameter - Change 'not' to 'no' since it reads better - Drop WIP commit for u-boot.srec as it is not needed now - Drop the part of the commit message that talks about using build date - Fix 'AT' value in link script - Move CLEAR_CMOS up to the top, indicated to be manually changed - Move common SATA init to a function to reduce duplication - Remove ISA DMA init which isn't needed in U-Boot - Remove i8259 patch and just update the existing interrupt code - Remove the parameter from rtc_init() and simplify the code - Remove use of __PRE_RAM__ define - Rename functions to pci_read_bar32() and pci_write_bar32() - Use .rel* instead of .rel.* to catch more cases - Use existing lapic_setup() code instead of duplicating it - Use i8259 init in pcat_interrupts.c - Use interrupt.h header instead of i8259.h - Use pci_write_bar32() to write to BARs Simon Glass (30): Align embedded device tree correctly Add ALIGN_DOWN() to find next smallest alignment pci: Update pci_ids.h to include some missing IDs x86: Remove board_early_init_r() x86: Panic if there is no relocation data x86: Ensure that all relocation data is included in the image x86: Factor out common values in the link script rtc: mc146818: Set up RTC at start of day x86: Add ioapic.h header x86: pci: Add handlers before and after a PCI hose scan x86: config: Enable plug-and-play for link PCI pci: Add functions to read and write a BAR address x86: Set up edge triggering on interrupt 9 x86: ivybridge: Add support for BD82x6x PCH x86: Add a simple header file for ACPI x86: ivybridge: Add PCH init x86: ivybridge: Add additional LPC init x86: dts: Move PCI peripherals into a pci node x86: dts: Add LPC settings for link x86: ivybridge: Add SATA init x86: dts: Add SATA settings for link x86: ivybridge: Set up EHCI USB x86: config: Enable USB on link x86: ivybridge: Set up XHCI USB x86: Add Intel speedstep and turbo mode code x86: Add LAPIC setup code x86: Add init for model 206AX CPU x86: Drop some msr functions that we don't support x86: ivybridge: Add northbridge init functions x86: config: Enable SPI for chromebook_link arch/x86/cpu/Makefile | 2 + arch/x86/cpu/config.mk | 5 +- arch/x86/cpu/coreboot/coreboot.c | 11 - arch/x86/cpu/ivybridge/Makefile | 7 + arch/x86/cpu/ivybridge/bd82x6x.c | 135 ++++++ arch/x86/cpu/ivybridge/lpc.c | 523 +++++++++++++++++++++- arch/x86/cpu/ivybridge/model_206ax.c | 514 +++++++++++++++++++++ arch/x86/cpu/ivybridge/northbridge.c | 188 ++++++++ arch/x86/cpu/ivybridge/pch.c | 123 +++++ arch/x86/cpu/ivybridge/pci.c | 40 ++ arch/x86/cpu/ivybridge/sata.c | 225 ++++++++++ arch/x86/cpu/ivybridge/usb_ehci.c | 29 ++ arch/x86/cpu/ivybridge/usb_xhci.c | 32 ++ arch/x86/cpu/lapic.c | 62 +++ arch/x86/cpu/pci.c | 12 + arch/x86/cpu/turbo.c | 98 ++++ arch/x86/cpu/u-boot.lds | 18 +- arch/x86/dts/link.dts | 41 +- arch/x86/include/asm/acpi.h | 24 + arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 21 + arch/x86/include/asm/arch-ivybridge/model_206ax.h | 4 + arch/x86/include/asm/arch-ivybridge/pch.h | 120 +++++ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 +- arch/x86/include/asm/interrupt.h | 11 + arch/x86/include/asm/ioapic.h | 38 ++ arch/x86/include/asm/lapic.h | 125 +++++- arch/x86/include/asm/msr-index.h | 2 + arch/x86/include/asm/msr.h | 11 - arch/x86/include/asm/pci.h | 3 + arch/x86/include/asm/post.h | 1 + arch/x86/include/asm/speedstep.h | 89 ++++ arch/x86/include/asm/turbo.h | 31 ++ arch/x86/lib/pcat_interrupts.c | 38 ++ arch/x86/lib/relocate.c | 3 + board/google/chromebook_link/link.c | 5 - common/board_r.c | 3 - doc/device-tree-bindings/ata/intel-sata.txt | 26 ++ doc/device-tree-bindings/misc/intel-lpc.txt | 47 +- drivers/pci/pci.c | 24 +- drivers/rtc/mc146818.c | 43 +- include/common.h | 15 + include/configs/chromebook_link.h | 11 +- include/fdtdec.h | 2 + include/pci.h | 23 + include/pci_ids.h | 187 +++++++- include/rtc.h | 5 + lib/fdtdec.c | 2 + scripts/Makefile.lib | 2 + 48 files changed, 2915 insertions(+), 79 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/bd82x6x.c create mode 100644 arch/x86/cpu/ivybridge/model_206ax.c create mode 100644 arch/x86/cpu/ivybridge/northbridge.c create mode 100644 arch/x86/cpu/ivybridge/pch.c create mode 100644 arch/x86/cpu/ivybridge/sata.c create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c create mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c create mode 100644 arch/x86/cpu/lapic.c create mode 100644 arch/x86/cpu/turbo.c create mode 100644 arch/x86/include/asm/acpi.h create mode 100644 arch/x86/include/asm/arch-ivybridge/bd82x6x.h create mode 100644 arch/x86/include/asm/ioapic.h create mode 100644 arch/x86/include/asm/speedstep.h create mode 100644 arch/x86/include/asm/turbo.h create mode 100644 doc/device-tree-bindings/ata/intel-sata.txt -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v2 0/2] mtd: denali: Use SELF_INIT to fix up registers after nand_scan_ident()
by Masahiro Yamada 25 Nov '14

25 Nov '14

This patch series is here because Scott Wood recommended me to use CONFIG_SYS_NAND_SELF_INIT to solve my problem: http://patchwork.ozlabs.org/patch/402462/ Changes in v2: - Use &nand_info[0] instead of nand_info - Print a warning message if initialization fails Masahiro Yamada (2): mtd: denali: use CONFIG_SYS_NAND_SELF_INIT mtd: denali: set some registers after nand_scan_ident() drivers/mtd/nand/Kconfig | 7 +++ drivers/mtd/nand/denali.c | 132 +++++++++++++++++++++++++++++++++------------- drivers/mtd/nand/denali.h | 5 +- 3 files changed, 104 insertions(+), 40 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 4/4] x86: Remove unnecessary call to initr_enable_interrupts()
by Bin Meng 25 Nov '14

25 Nov '14

Actually initr_enable_interrupts() was never called in an x86 build due to it was wrapped by CONFIG_x86 (typo of X86). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- common/board_r.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/board_r.c b/common/board_r.c index b5ea030..128fcce 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -841,7 +841,7 @@ init_fnc_t init_sequence_r[] = { board_early_init_r, #endif interrupt_init, -#if defined(CONFIG_ARM) || defined(CONFIG_x86) +#if defined(CONFIG_ARM) initr_enable_interrupts, #endif #ifdef CONFIG_X86 -- 1.8.2.1

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[U-Boot] [PATCH 3/4] x86: Refactor interrupt_init()
by Bin Meng 25 Nov '14

25 Nov '14

Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/interrupts.c | 26 ++++++++++++++++++++------ arch/x86/include/asm/i8259.h | 2 ++ arch/x86/lib/pcat_interrupts.c | 9 +-------- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 51e2c59..ea03724 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -20,6 +20,7 @@ #include <linux/compiler.h> #include <asm/msr.h> #include <asm/u-boot-x86.h> +#include <asm/i8259.h> DECLARE_GLOBAL_DATA_PTR; @@ -128,9 +129,6 @@ int cpu_init_interrupts(void) int irq_entry_size = irq_1 - irq_0; void *irq_entry = (void *)irq_0; - /* Just in case... */ - disable_interrupts(); - /* Setup the IDT */ for (i = 0; i < 256; i++) { idt[i].access = 0x8e; @@ -146,9 +144,6 @@ int cpu_init_interrupts(void) load_idt(&idt_ptr); - /* It is now safe to enable interrupts */ - enable_interrupts(); - return 0; } @@ -172,6 +167,25 @@ int disable_interrupts(void) return flags & X86_EFLAGS_IF; } +int interrupt_init(void) +{ + /* Just in case... */ + disable_interrupts(); + +#ifdef CONFIG_SYS_PCAT_INTERRUPTS + /* Initialize the master/slave i8259 pic */ + i8259_init(); +#endif + + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts(); + + /* It is now safe to enable interrupts */ + enable_interrupts(); + + return 0; +} + /* IRQ Low-Level Service Routine */ void irq_llsr(struct irq_regs *regs) { diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 73113f9..bc4033b 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -69,4 +69,6 @@ #define ICW4_AEOI 0x02 /* Automatic EOI Mode */ #define ICW4_PM 0x01 /* Microprocessor Mode */ +int i8259_init(void); + #endif diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 2ce371e..27c7f08 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -24,12 +24,10 @@ #error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined" #endif -int interrupt_init(void) +int i8259_init(void) { u8 i; - disable_interrupts(); - /* Mask all interrupts */ outb(0xff, MASTER_PIC + IMR); outb(0xff, SLAVE_PIC + IMR); @@ -62,11 +60,6 @@ int interrupt_init(void) */ unmask_irq(2); - /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts(); - - enable_interrupts(); - return 0; } -- 1.8.2.1

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[U-Boot] [PATCH 2/4] x86: Remove cpu_init_r() for x86
by Bin Meng 25 Nov '14

25 Nov '14

Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/cpu.c | 6 ------ arch/x86/include/asm/u-boot-x86.h | 2 -- common/board_r.c | 2 +- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index cf0606e..1a6f679 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -319,12 +319,6 @@ int x86_cpu_init_f(void) return 0; } -int x86_cpu_init_r(void) -{ - return 0; -} -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); - void x86_enable_caches(void) { unsigned long cr0; diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 0399417..f454b83 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -10,8 +10,6 @@ /* cpu/.../cpu.c */ int arch_cpu_init(void); -int x86_cpu_init_r(void); -int cpu_init_r(void); int x86_cpu_init_f(void); int cpu_init_f(void); void init_gd(gd_t *id, u64 *gdt_addr); diff --git a/common/board_r.c b/common/board_r.c index 7c33900..b5ea030 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -774,7 +774,7 @@ init_fnc_t init_sequence_r[] = { initr_flash, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PPC) || defined(CONFIG_X86) +#if defined(CONFIG_PPC) /* initialize higher level parts of CPU like time base and timers */ cpu_init_r, #endif -- 1.8.2.1

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