November 2014 - U-Boot

[U-Boot] ARM: flush_dcache_all for PSCI
by Jan Kiszka 26 Nov '14

26 Nov '14

Hi all, I'm trying to get Marc's CPU hotplug-anabling patch [1] for sunxi working on a B-Pi. After the first discussion it became clear that we need something like flush_dcache_all in the PSCI monitor (I don't think we need an icache flush, do we?). Does anyone have a clever suggestion how to reuse the existing code for that? Or do we really need to re-implement everything, in the worst case in assembly? Thanks! Jan [1] https://git.kernel.org/cgit/linux/kernel/git/maz/u-boot.git/commit/?h=wip/p… -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux

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[U-Boot] [PATCH 1/2] sun6i: axp221: Add axp221_get_sid function
by Hans de Goede 26 Nov '14

26 Nov '14

For sun6i the SID is stored in the pmic, rather then in the SoC itself, add a function to retreive the sid. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- drivers/power/axp221.c | 27 +++++++++++++++++++++++++++ include/axp221.h | 6 ++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c index 941193a..826567a 100644 --- a/drivers/power/axp221.c +++ b/drivers/power/axp221.c @@ -184,3 +184,30 @@ int axp221_init(void) return 0; } + +int axp221_get_sid(unsigned int *sid) +{ + u8 *dest = (u8 *)sid; + int i, ret; + + ret = axp221_init(); + if (ret) + return ret; + + ret = p2wi_write(AXP221_PAGE, 1); + if (ret) + return ret; + + for (i = 0; i < 16; i++) { + ret = p2wi_read(AXP221_SID + i, &dest[i]); + if (ret) + return ret; + } + + p2wi_write(AXP221_PAGE, 0); + + for (i = 0; i < 4; i++) + sid[i] = be32_to_cpu(sid[i]); + + return 0; +} diff --git a/include/axp221.h b/include/axp221.h index e3b4409..db219c6 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -10,6 +10,7 @@ #define AXP221_CTRL_ADDR 0x3e #define AXP221_INIT_DATA 0x3e +/* Page 0 addresses */ #define AXP221_CHIP_ID 0x03 #define AXP221_OUTPUT_CTRL1 0x10 #define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6) @@ -34,6 +35,10 @@ #define AXP221_ALDO1_CTRL 0x28 #define AXP221_ALDO2_CTRL 0x28 #define AXP221_ALDO3_CTRL 0x2a +#define AXP221_PAGE 0xff + +/* Page 1 addresses */ +#define AXP221_SID 0x20 int axp221_set_dcdc1(unsigned int mvolt); int axp221_set_dcdc2(unsigned int mvolt); @@ -48,3 +53,4 @@ int axp221_set_aldo1(unsigned int mvolt); int axp221_set_aldo2(unsigned int mvolt); int axp221_set_aldo3(unsigned int mvolt); int axp221_init(void); +int axp221_get_sid(unsigned int *sid); -- 2.1.0

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[U-Boot] mx53loco: compilation broken with 2015.01-rc2
by Guillaume Gardet 26 Nov '14

26 Nov '14

Hi, mx53loco_defconfig is broken in 2015.01-rc2 (was ok with -rc1). I have the following warning: drivers/block/dwc_ahsata.c: In function 'reset_sata': drivers/block/dwc_ahsata.c:611:2: warning: implicit declaration of function 'disable_sata_clock' [-Wimplicit-function-declaration] And finally this error: drivers/built-in.o: In function `reset_sata': /home/abuild/rpmbuild/BUILD/u-boot-2015.01-rc2/drivers/block/dwc_ahsata.c:611: undefined reference to `disable_sata_clock' ld.bfd: BFD (GNU Binutils; openSUSE 13.2) 2.24.0.20140403-6.1 assertion fail ../../bfd/elf32-arm.c:7696 ld.bfd: error: required section '.rel.plt' not found in the linker script ld.bfd: final link failed: Invalid operation Makefile:1066: recipe for target 'u-boot' failed Commit 10ee8ecafbb4405ac77f6df081325630617aa7cd : "sata: implement reset_sata for dwc_ahsata" is probably the problem. mx6 is fixed by commit 8d29cef5887887157f54f98493440ce5c824d5cb : "arm: mx6: introduce disable_sata_clock", but nothing for mx5. Guillaume

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[U-Boot] qemu-system-arm segfaults on zynq_zed
by Douglas Rupp 26 Nov '14

26 Nov '14

I'm brand new to Uboot, so hopefully this is just some missing switch. I did search the archive, and I was able to build and u-boot a versaatilepb version, but xilinx-zynq-a9 is the one I really need. u-boot-2014.10$ make zynq_zed_defconfig u-boot-2014.10$ make all CROSS_COMPILE=arm-none-eabi- ARCH=arm u-boot-2014.10$ qemu-system-arm -M xilinx-zynq-a9 -m 1024M -nographic -kernel u-boot-dtb.bin Segmentation fault (core dumped) What am I doing wrong?

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[U-Boot] [PATCH] mvebu_mmc: Speed up access time
by Mario Schuknecht 26 Nov '14

26 Nov '14

Remove udelay, because card status is polled in a loop. Signed-off-by: Mario Schuknecht <mario.schuknecht(a)dresearch-fe.de> --- drivers/mmc/mvebu_mmc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 9f98c3f..2bf9444 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -72,8 +72,6 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", cmd->cmdidx, cmd->resp_type, cmd->cmdarg); - udelay(10*1000); - debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE)); -- 1.8.4.5

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[U-Boot] ls1021aqds: add hwconfig setting to do pin mux
by Yuan Yao 26 Nov '14

26 Nov '14

Changed in v2: - Rebase to latest u-boot. Added in v1: - Add hwconfig setting to do pin mux.

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[U-Boot] [Patch v2] powerpc/mpc85xx: Fix DDR TLB mapping leftover
by York Sun 26 Nov '14

26 Nov '14

Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB mapping function, but made the DDR mapping leftover size to zero, causing the message not printed. Signed-off-by: York Sun <yorksun(a)freescale.com> CC: Alexander Graf <agraf(a)suse.de> CC: Scott Wood <scottwood(a)freescale.com> --- Change log v2: Fix unnecessary parentheses arch/powerpc/cpu/mpc85xx/tlb.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 129ec66..cd5fb76 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -299,12 +299,15 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, { unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; + u64 size; - memsize = min(memsize, CONFIG_MAX_MEM_MAPPED); - memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM); + size = min(memsize, CONFIG_MAX_MEM_MAPPED); + size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); - if (memsize) - print_size(memsize, " left unmapped\n"); + if (size || memsize > CONFIG_MAX_MEM_MAPPED) { + print_size(memsize - CONFIG_MAX_MEM_MAPPED + size, + " left unmapped\n"); + } return memsize_in_meg; } -- 1.7.9.5

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[U-Boot] [PATCH] powerpc/mpc85xx: Fix DDR TLB mapping leftover
by York Sun 26 Nov '14

26 Nov '14

Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB mapping function, but made the DDR mapping leftover size to zero, causing the message not printed. Signed-off-by: York Sun <yorksun(a)freescale.com> CC: Alexander Graf <agraf(a)suse.de> CC: Scott Wood <scottwood(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/tlb.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 129ec66..4f0f7d5 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -299,12 +299,15 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, { unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; + u64 size; - memsize = min(memsize, CONFIG_MAX_MEM_MAPPED); - memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM); + size = min(memsize, CONFIG_MAX_MEM_MAPPED); + size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); - if (memsize) - print_size(memsize, " left unmapped\n"); + if ((size) || (memsize > CONFIG_MAX_MEM_MAPPED)) { + print_size(memsize - CONFIG_MAX_MEM_MAPPED + size, + " left unmapped\n"); + } return memsize_in_meg; } -- 1.7.9.5

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[U-Boot] [PATCH 0/19] x86: ivybridge: Add graphics support
by Simon Glass 25 Nov '14

25 Nov '14

This series adds a graphics driver and support for execution of the VGA option ROM. This option ROM is required on ivybridge for the graphics to work, at least until someone creates the equivalent source code. Option ROMs can be run using U-Boot's BIOS emulator, but on x86 it is also possible to run then natively. This is something of a pain to arrange due to all the environment that is required (16-bit to 32-bit calls, etc.) but it can be done, so this series adds that feature too. Video mode selection is useful as it allows different resolutions to be selected. This series adds support for VESA modes and a way of selecting the mode to use in U-Boot. These options are enabled for chromebook_link, which now boots to a prompt complete with a functioning LCD. A resolution 0f 1280x1024 is selected by default. While the Chrome OS EC works correctly, the keyboard does not as yet. Also U-Boot is currently very slow, taking about 2 seconds to boot to a prompt when video is enabled. These problems will be the subject of future work. Simon Glass (19): x86: Add a definition of asmlinkage Introduce a header file for the BIOS emulator x86: Add GDT descriptors for option ROMs x86: Add vesa mode configuration options Add support for Vesa BIOS extensions x86: Add support for running option ROMs natively pci: Add general support for execution of video ROMs x86: video: Add video driver for bare x86 boards x86: Allow an option ROM to be built into U-Boot x86: Add initial video device init for Intel GMA x86: dts: Add video information to the device tree x86: config: Enable video support for chromebook_link bios_emulator: Allow x86 to use the emulator bios_emulator: Add vesa support and allow ROMs to be passed in as data bios_emulator: Allow a custom interrupt handler to be installed bios_emulator: Add an option to enable debugging bios_emulator: Always print errors when opcode decode fails x86: chromebook_link: Enable the x86 emulator x86: chromebook_link: Enable the Chrome OS EC Makefile | 3 + arch/x86/Kconfig | 149 +++++ arch/x86/cpu/cpu.c | 9 +- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 13 +- arch/x86/cpu/ivybridge/gma.c | 756 ++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/gma.h | 157 ++++++ arch/x86/dts/link.dts | 13 + arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 + arch/x86/include/asm/processor.h | 31 +- arch/x86/lib/Makefile | 3 + arch/x86/lib/bios.c | 348 ++++++++++++ arch/x86/lib/bios.h | 98 ++++ arch/x86/lib/bios_asm.S | 281 ++++++++++ arch/x86/lib/bios_interrupts.c | 219 ++++++++ board/google/chromebook_link/link.c | 4 + doc/device-tree-bindings/video/intel-gma.txt | 40 ++ drivers/bios_emulator/Makefile | 2 +- drivers/bios_emulator/atibios.c | 198 +++++-- drivers/bios_emulator/besys.c | 100 ++-- drivers/bios_emulator/bios.c | 4 +- drivers/bios_emulator/biosemui.h | 2 +- drivers/bios_emulator/include/biosemu.h | 53 +- drivers/bios_emulator/include/x86emu.h | 7 +- drivers/bios_emulator/include/x86emu/debug.h | 20 +- drivers/bios_emulator/include/x86emu/regs.h | 2 +- drivers/bios_emulator/x86emu/debug.c | 10 +- drivers/bios_emulator/x86emu/decode.c | 24 +- drivers/bios_emulator/x86emu/ops.c | 58 +- drivers/bios_emulator/x86emu/ops2.c | 4 +- drivers/bios_emulator/x86emu/sys.c | 5 + drivers/pci/Makefile | 2 +- drivers/pci/pci_rom.c | 276 ++++++++++ drivers/video/Makefile | 1 + drivers/video/ati_radeon_fb.c | 2 +- drivers/video/x86_fb.c | 37 ++ include/bios_emul.h | 65 +++ include/common.h | 3 + include/configs/chromebook_link.h | 19 +- include/fdtdec.h | 1 + include/pci_rom.h | 58 ++ include/vbe.h | 103 ++++ include/video_fb.h | 2 +- lib/fdtdec.c | 1 + 44 files changed, 2950 insertions(+), 236 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/gma.c create mode 100644 arch/x86/cpu/ivybridge/gma.h create mode 100644 arch/x86/lib/bios.c create mode 100644 arch/x86/lib/bios.h create mode 100644 arch/x86/lib/bios_asm.S create mode 100644 arch/x86/lib/bios_interrupts.c create mode 100644 doc/device-tree-bindings/video/intel-gma.txt create mode 100644 drivers/pci/pci_rom.c create mode 100644 drivers/video/x86_fb.c create mode 100644 include/bios_emul.h create mode 100644 include/pci_rom.h create mode 100644 include/vbe.h -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH 0/1] ls1021aqds: add hwconfig setting to do pin mux
by Yuan Yao 25 Nov '14

25 Nov '14

Added in v1: - Add pin mux support for ls1021aqds. Test log: U-Boot 2014.07-01993-g052b512-dirty (Oct 20 2014 - 19:58:20) CPU: Freescale LayerScape LS1020E, Version: 1.0, (0x87081010) Clock Configuration: CPU0(ARMV7):1000 MHz, Bus:300 MHz, DDR:800 MHz (1600 MT/s data rate), Reset Configuration Word (RCW): 00000000: 0608000a 00000000 00000000 00000000 00000010: 60000000 00407900 e0025a00 21046000 00000020: 00000000 00000000 00000000 00038000 00000030: 00000000 001b7200 00000000 00000000 Board: LS1021AQDS vBank: 4 Sys ID:0x2b, Sys Ver: 0x11 FPGA: v13 (QIXIS_LS1021QDS_2014_08_27_1658), build 65386 I2C: ready DRAM: Initializing DDR....using SPD Detected UDIMM 18KSF51272AZ-1G6K1 2 GiB (DDR3, 32-bit, CL=11, ECC off) Using SERDES1 Protocol: 96 (0x60) Flash: 128 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: eTSEC1 is in sgmii mode eTSEC2 is in sgmii mode Phy not found PHY reset timed out Phy not found PHY reset timed out eTSEC1, eTSEC2, eTSEC3 [PRIME] => pri baudrate=115200 boot=dhcp 82000000 r66431/ls1/uImage.ls1021a; tftp 8f000000 r66431/ls1/ls1021a-qds.dtb; tftp 88000000 r66431/ls1/fsl-image-x11-ls1021aqds-20140424073555.rootfs.ext2.gz.u-boot ; bootm 82000000 88000000 8f000000 boot_bank0=i2c mw 0x66 0x50 0x40;i2c mw 0x66 0x10 0x20;i2c mw 0x66 0x10 0x21 boot_bank4=i2c mw 0x66 0x50 0x44;i2c mw 0x66 0x10 0x20;i2c mw 0x66 0x10 0x21 bootargs=root=/dev/ram0 rw console=ttyS0,115200 bootdelay=3 eth1addr=00:04:9f:03:2e:c5 eth2addr=00:04:9f:03:2e:c6 eth3addr=00:04:9f:03:2e:c7 eth4addr=00:04:9f:03:2e:c8 eth5addr=00:04:9f:03:2e:c9 eth6addr=00:04:9f:03:2e:ca ethact=eTSEC3 ethaddr=00:04:9f:03:2e:c4 ethprime=eTSEC3 fdt_high=0xffffffff hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null,ecc=off initrd_high=0xffffffff ipaddr=192.168.1.121 loadaddr=0x82000000 scsidevs=0 serverip=192.168.1.1 stderr=serial stdin=serial stdout=serial zhuoboot=tftp 82000000 b46552/ls1021aqds/uImage.ls1021a; tftp 8f000000 b46552/ls1021aqds/ls1021a-qds.dtb;tftp 88000000 b46552/ls1021aqds/ramdisk.small;bootm 82000000 88000000 8f000000 Environment size: 1117/8188 bytes => i2c md 0x66 0x5e 005e: 00 00 12 81 f7 ff ff ff ff ef e7 00 3f ff ff ff ............?... => set hwconfig "fsl_ddr:ctlr_intlv=null,bank_intlv=null,ecc=off;sai" => save Saving Environment to Flash... Un-Protected 1 sectors Erasing Flash... . done Erased 1 sectors Writing to Flash... 9....8....7....6....5....4....3....2....1....9....8....7....6....5....4....3....2....1....done Protected 1 sectors => run boot_bank4 U-Boot 2014.07-01993-g052b512-dirty (Oct 20 2014 - 19:58:20) CPU: Freescale LayerScape LS1020E, Version: 1.0, (0x87081010) Clock Configuration: CPU0(ARMV7):1000 MHz, Bus:300 MHz, DDR:800 MHz (1600 MT/s data rate), Reset Configuration Word (RCW): 00000000: 0608000a 00000000 00000000 00000000 00000010: 60000000 00407900 e0025a00 21046000 00000020: 00000000 00000000 00000000 00038000 00000030: 00000000 001b7200 00000000 00000000 Board: LS1021AQDS vBank: 4 Sys ID:0x2b, Sys Ver: 0x11 FPGA: v13 (QIXIS_LS1021QDS_2014_08_27_1658), build 65386 I2C: ready DRAM: Initializing DDR....using SPD Detected UDIMM 18KSF51272AZ-1G6K1 2 GiB (DDR3, 32-bit, CL=11, ECC off) Using SERDES1 Protocol: 96 (0x60) Flash: 128 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: eTSEC1 is in sgmii mode eTSEC2 is in sgmii mode Phy not found PHY reset timed out Phy not found PHY reset timed out eTSEC1, eTSEC2, eTSEC3 [PRIME] => i2c md 0x66 0x5e 005e: 0c 00 12 81 f7 ff ff ff ff ef e7 00 3f ff ff ff ............?... => [b46683@rhuath ~]$

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