January 2014 - U-Boot

[U-Boot] Quickstart-Manual for u-boot?
by Fred Fisch 13 Jan '14

13 Jan '14

Hi, I already found - the sources in GIT - the config-name of my board - the (really huge) manual Since all I want to do is just compile MLO/u-boot.img for BeagleBone Black the latter seems to be totally oversized for me. So my question: is there some kind of quick-start/cookbook available that just describes the steps to compile U-Boot for a single platform? Cheers Fred

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[U-Boot] [PATCH v2] net/designware: make driver compatible with data cache
by Alexey Brodkin 13 Jan '14

13 Jan '14

Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Flush Tx/Rx buffer descriptors their modification * Invalidate Tx/Rx buffer descriptors before reading its values * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Mischa Jonker <mjonker(a)synopsys.com> Compared to v1: 1. Dropped all extra "readl"/"writel" since it makes no sense in terms of data access via D$. 2. Added flush/invalidation of buffer descriptors after/before its data access. --- drivers/net/designware.c | 53 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 22155b4..53a95bf 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -51,6 +51,11 @@ static void tx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->tx_mac_descrtable, + (unsigned int)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); } @@ -63,6 +68,15 @@ static void rx_descs_init(struct eth_device *dev) struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; @@ -78,6 +92,11 @@ static void rx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->rx_mac_descrtable, + (unsigned int)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); } @@ -197,6 +216,11 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + /* Invalidate only "status" field for the following check */ + invalidate_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); + /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { printf("CPU not owner of tx frame\n"); @@ -205,6 +229,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) memcpy((void *)desc_p->dmamac_addr, packet, length); + /* Flush data to be sent */ + flush_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + length); + #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ @@ -220,6 +248,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; #endif + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + sizeof(struct dmamacdescr)); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) desc_num = 0; @@ -235,18 +267,28 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) static int dw_eth_recv(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - u32 desc_num = priv->rx_currdescnum; + u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; - - u32 status = desc_p->txrx_status; int length = 0; + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + + sizeof(struct dmamacdescr)); + + status = desc_p->txrx_status; + /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { length = (status & DESC_RXSTS_FRMLENMSK) >> \ DESC_RXSTS_FRMLENSHFT; + /* Invalidate received data */ + invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + + length); + NetReceive(desc_p->dmamac_addr, length); /* @@ -254,6 +296,11 @@ static int dw_eth_recv(struct eth_device *dev) * the next one */ desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + + /* Flush only status field - others weren't changed */ + flush_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) -- 1.8.4.2

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[U-Boot] 2014.01: two ARM boards left with CONFIG_SYS_HZ warning
by Albert ARIBAUD 13 Jan '14

13 Jan '14

Hello, As we are about to release 2014.01, there are still two boards left which have the following warning: time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000 and should not be defined by platforms" [-Wcpp] ISTR work was underway to fix these. Is there, actually, and if not, what do we do with these boards? I don't like having builds where there are warnings left. Amicalement, -- Albert.

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[U-Boot] [PATCH 2/2] ARM: versatile: pass console setting to the kernel
by Linus Walleij 13 Jan '14

13 Jan '14

The Versatiles come up with the primary UART set to ttyAMA0 at 38400 baud, and unless we pass this to the kernel it will assume it is set to 9600 baud which will be quite awkward for the terminal, let's try to be helpful and inform the kernel what setting is used. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- include/configs/versatile.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 10738ac24be0..29c32fee5178 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -101,7 +101,8 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ - "netdev=25,0,0xf1010000,0xf1010010,eth0" + "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ + "console=ttyAMA0,38400n1" /* * Static configuration when assigning fixed address -- 1.8.3.1

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[U-Boot] [PATCH 1/2] ARM: versatile: pass correct machine type for Versatile AB
by Linus Walleij 13 Jan '14

13 Jan '14

When U-Boot is configured for Versatile AB, it will still pass the machine ID of Versatile PB to the kernel. After this simple fix the system boots correctly. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/armltd/versatile/versatile.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 30a3b904db4c..4e2d3421d8b1 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -52,7 +52,11 @@ int board_early_init_f (void) int board_init (void) { /* arch number of Versatile Board */ +#ifdef CONFIG_ARCH_VERSATILE_AB + gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB; +#else gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; -- 1.8.3.1

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[U-Boot] [PATCH v2 0/2] video: ipu reg: Correct some reserved array sizes
by Liu Ying 12 Jan '14

12 Jan '14

The structures ipu_cm and ipu_idmac contain some reserved arrays as placeholders to make sure the trailing entries may point to the relevant IPU registers. This patch corrects the size of the reserved arrays. Changes in v2: Added Robin Gong's ack. Liu Ying (2): video: ipu reg: Correct reserved1 array size in struct ipu_cm video: ipu reg: Correct reserved array size in struct ipu_idmac drivers/video/ipu_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH v7 17/17] doc: SPI: Update status.txt
by Jagannadha Sutradharudu Teki 12 Jan '14

12 Jan '14

Updated current SPI subsyetem status. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- doc/SPI/status.txt | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/doc/SPI/status.txt b/doc/SPI/status.txt index 62c3c85..13889f5 100644 --- a/doc/SPI/status.txt +++ b/doc/SPI/status.txt @@ -11,6 +11,11 @@ SPI FLASH (drivers/mtd/spi): - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing) - Added memory_mapped support for read operations. - Common probe support for all supported flash vendors except, ramtron. +- Extended read commands support(dual read, dual IO read) +- Quad Page Program support. +- Quad Read support(quad fast read, quad IO read) +- Dual flash connection topology support(accessing two spi flash memories with single cs) +- Banking support on dual flash connection topology. SPI DRIVERS (drivers/spi): - @@ -18,14 +23,10 @@ SPI DRIVERS (drivers/spi): TODO: - Runtime detection of spi_flash params, SFDP(if possible) - Add support for multibus build/accessing. -- Extended read commands support(dual read, dual IO read) -- Quad Page Program support. -- Quad Read support(quad fast read, quad IO read) -- Dual flash connection topology support(accessing two spi flash memories with single cs) -- Banking support on dual flash connection topology. - Need proper cleanups on spi_flash and drivers. -- Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> 18-09-2013. 07-10-2013. +08-01-2014. -- 1.8.3

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[U-Boot] [PATCH v7 16/17] sf: Add CONFIG_SF_DUAL_FLASH
by Jagannadha Sutradharudu Teki 12 Jan '14

12 Jan '14

This config will use for defining greater than single flash support. currently - DUAL_STACKED and DUAL_PARALLEL. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- README | 6 ++++++ drivers/mtd/spi/sf.c | 3 ++- drivers/mtd/spi/sf_ops.c | 14 ++++++++++---- drivers/mtd/spi/sf_probe.c | 2 ++ 4 files changed, 20 insertions(+), 5 deletions(-) diff --git a/README b/README index a0646c3..aea82be 100644 --- a/README +++ b/README @@ -2756,6 +2756,12 @@ CBFS (Coreboot Filesystem) support Define this option to use the Bank addr/Extended addr support on SPI flashes which has size > 16Mbytes. + CONFIG_SF_DUAL_FLASH Dual flash memories + + Define this option to use dual flash support where two flash + memories can be connected with a given cs line. + currently Xilinx Zynq qspi support these type of connections. + - SystemACE Support: CONFIG_SYSTEMACE diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index c780a81..664e860 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -18,9 +18,10 @@ static int spi_flash_read_write(struct spi_slave *spi, unsigned long flags = SPI_XFER_BEGIN; int ret; +#ifdef CONFIG_SF_DUAL_FLASH if (spi->flags & SPI_XFER_U_PAGE) flags |= SPI_XFER_U_PAGE; - +#endif if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 843f379..1f1bb36 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -131,6 +131,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) } #endif +#ifdef CONFIG_SF_DUAL_FLASH static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) { switch (flash->dual_flash) { @@ -150,6 +151,7 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) break; } } +#endif int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { @@ -167,9 +169,10 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) check_status = poll_bit; } +#ifdef CONFIG_SF_DUAL_FLASH if (spi->flags & SPI_XFER_U_PAGE) flags |= SPI_XFER_U_PAGE; - +#endif ret = spi_xfer(spi, 8, &cmd, NULL, flags); if (ret) { debug("SF: fail to read %s status register\n", @@ -257,9 +260,10 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) while (len) { erase_addr = offset; +#ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) spi_flash_dual_flash(flash, &erase_addr); - +#endif #ifdef CONFIG_SPI_FLASH_BAR ret = spi_flash_bank(flash, erase_addr); if (ret < 0) @@ -298,9 +302,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, for (actual = 0; actual < len; actual += chunk_len) { write_addr = offset; +#ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) spi_flash_dual_flash(flash, &write_addr); - +#endif #ifdef CONFIG_SPI_FLASH_BAR ret = spi_flash_bank(flash, write_addr); if (ret < 0) @@ -383,9 +388,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, while (len) { read_addr = offset; +#ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) spi_flash_dual_flash(flash, &read_addr); - +#endif #ifdef CONFIG_SPI_FLASH_BAR bank_sel = spi_flash_bank(flash, read_addr); if (bank_sel < 0) diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 48de7c1..bc3cf6c 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -150,8 +150,10 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift; flash->sector_size = params->sector_size << flash->shift; flash->size = flash->sector_size * params->nr_sectors << flash->shift; +#ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash & SF_DUAL_STACKED_FLASH) flash->size <<= 1; +#endif /* Compute erase sector and command */ if (params->flags & SECT_4K) { -- 1.8.3

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[U-Boot] [PATCH v7 15/17] sf: Add dual memories support - DUAL_PARALLEL
by Jagannadha Sutradharudu Teki 12 Jan '14

12 Jan '14

This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- doc/SPI/README.dual-flash | 27 +++++++++++++++++++++++++++ drivers/mtd/spi/sf_ops.c | 8 ++++++-- drivers/mtd/spi/sf_probe.c | 11 ++++++----- include/spi.h | 3 ++- include/spi_flash.h | 5 ++++- 5 files changed, 45 insertions(+), 9 deletions(-) diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash index ba0aa26..6c88d65 100644 --- a/doc/SPI/README.dual-flash +++ b/doc/SPI/README.dual-flash @@ -54,6 +54,33 @@ SF_DUAL_STACKED_FLASH: by default, if U_PAGE is unset lower memory should accessible, once user wants to access upper memory need to set U_PAGE. +SPI_FLASH_CONN_DUALPARALLEL: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating parallel with separate buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +-------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + | Controller | CS +---------------+ + | SPI/QSPI |---------------------->| | + | | I0[3:0] | Lower Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + +-------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register. + - Operation: + Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory + and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory. + Note: Technically there is only one CS line from the controller, but zynq qspi controller has an internal hw logic to enable additional CS when controller is configured for dual memories. diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index e877858..843f379 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -119,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) u8 bank_sel; int ret; - bank_sel = offset / SPI_FLASH_16MB_BOUN; + bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); if (ret) { @@ -142,6 +142,9 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) flash->spi->flags &= ~SPI_XFER_U_PAGE; } break; + case SF_DUAL_PARALLEL_FLASH: + *addr >>= flash->shift; + break; default: debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); break; @@ -388,7 +391,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, if (bank_sel < 0) return ret; #endif - remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; + remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * + (bank_sel + 1)) - offset; if (len < remain_len) read_len = len; else diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index b9e14c5..48de7c1 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -146,19 +146,20 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->read = spi_flash_cmd_read_ops; /* Compute the flash size */ - flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256; - flash->sector_size = params->sector_size; - flash->size = flash->sector_size * params->nr_sectors; + flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; + flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift; + flash->sector_size = params->sector_size << flash->shift; + flash->size = flash->sector_size * params->nr_sectors << flash->shift; if (flash->dual_flash & SF_DUAL_STACKED_FLASH) flash->size <<= 1; /* Compute erase sector and command */ if (params->flags & SECT_4K) { flash->erase_cmd = CMD_ERASE_4K; - flash->erase_size = 4096; + flash->erase_size = 4096 << flash->shift; } else if (params->flags & SECT_32K) { flash->erase_cmd = CMD_ERASE_32K; - flash->erase_size = 32768; + flash->erase_size = 32768 << flash->shift; } else { flash->erase_cmd = CMD_ERASE_64K; flash->erase_size = flash->sector_size; diff --git a/include/spi.h b/include/spi.h index d214d82..ffd6647 100644 --- a/include/spi.h +++ b/include/spi.h @@ -47,6 +47,7 @@ /* SPI bus connection options */ #define SPI_CONN_DUAL_SHARED 1 << 0 +#define SPI_CONN_DUAL_SEPARATED 1 << 1 /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec @@ -66,7 +67,7 @@ * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. - * @option: Varies SPI bus options - separate bus. + * @option: Varies SPI bus options - separate, shared bus. * @flags: Indication of SPI flags. */ struct spi_slave { diff --git a/include/spi_flash.h b/include/spi_flash.h index 36f1f03..f79f0ea 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -40,6 +40,7 @@ enum spi_read_cmds { enum spi_dual_flash { SF_SINGLE_FLASH = 0, SF_DUAL_STACKED_FLASH = 1 << 0, + SF_DUAL_PARALLEL_FLASH = 1 << 1, }; /** @@ -70,7 +71,8 @@ extern const struct spi_flash_params spi_flash_params_table[]; * * @spi: SPI slave * @name: Name of SPI flash - * @dual_flash: Indicates dual flash memories - dual stacked + * @dual_flash: Indicates dual flash memories - dual stacked, parallel + * @shift: Flash shift useful in dual parallel * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -96,6 +98,7 @@ struct spi_flash { struct spi_slave *spi; const char *name; u8 dual_flash; + u8 shift; u32 size; u32 page_size; -- 1.8.3

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[U-Boot] [PATCH v7 14/17] sf: Add dual memories support - DUAL_STACKED
by Jagannadha Sutradharudu Teki 12 Jan '14

12 Jan '14

This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- doc/SPI/README.dual-flash | 65 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/sf.c | 3 +++ drivers/mtd/spi/sf_ops.c | 57 +++++++++++++++++++++++++++++++++------- drivers/mtd/spi/sf_probe.c | 8 +++++- include/spi.h | 8 ++++++ include/spi_flash.h | 8 ++++++ 6 files changed, 138 insertions(+), 11 deletions(-) create mode 100644 doc/SPI/README.dual-flash diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash new file mode 100644 index 0000000..ba0aa26 --- /dev/null +++ b/doc/SPI/README.dual-flash @@ -0,0 +1,65 @@ +SPI/QSPI Dual flash connection modes: +===================================== + +This describes how SPI/QSPI flash memories are connected to a given +controller in a single chip select line. + +Current spi_flash framework supports, single flash memory connected +to a given controller with single chip select line, but there are some +hw logics(ex: xilinx zynq qspi) that describes two/dual memories are +connected with a single chip select line from a controller. + +"dual_flash" from include/spi.h describes these types of connection mode + +Possible connections: +-------------------- +SF_SINGLE_FLASH: + - single spi flash memory connected with single chip select line. + + +------------+ CS +---------------+ + | |----------------------->| | + | Controller | I0[3:0] | Flash memory | + | SPI/QSPI |<======================>| (SPI/QSPI) | + | | CLK | | + | |----------------------->| | + +------------+ +---------------+ + +SF_DUAL_STACKED_FLASH: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating stacked fasion with shared buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | | +=========>| memory | + | | | CLK | (SPI/QSPI) | + | | | +---->| | + | Controller | CS | | +---------------+ + | SPI/QSPI |------------|----|---->| | + | | I0[3:0] | | | Lower Flash | + | |<===========+====|====>| memory | + | | CLK | | (SPI/QSPI) | + | |-----------------+---->| | + +------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG + Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory + Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory + - Operation: + accessing memories serially like one after another. + by default, if U_PAGE is unset lower memory should accessible, + once user wants to access upper memory need to set U_PAGE. + +Note: Technically there is only one CS line from the controller, but +zynq qspi controller has an internal hw logic to enable additional CS +when controller is configured for dual memories. + +[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM… + +-- +Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +05-01-2014. diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index d5e175c..c780a81 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -18,6 +18,9 @@ static int spi_flash_read_write(struct spi_slave *spi, unsigned long flags = SPI_XFER_BEGIN; int ret; + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; + if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 7ae9582..e877858 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -131,10 +131,28 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) } #endif +static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) +{ + switch (flash->dual_flash) { + case SF_DUAL_STACKED_FLASH: + if (*addr >= (flash->size >> 1)) { + *addr -= flash->size >> 1; + flash->spi->flags |= SPI_XFER_U_PAGE; + } else { + flash->spi->flags &= ~SPI_XFER_U_PAGE; + } + break; + default: + debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); + break; + } +} + int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { struct spi_slave *spi = flash->spi; unsigned long timebase; + unsigned long flags = SPI_XFER_BEGIN; int ret; u8 status; u8 check_status = 0x0; @@ -146,7 +164,10 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) check_status = poll_bit; } - ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; + + ret = spi_xfer(spi, 8, &cmd, NULL, flags); if (ret) { debug("SF: fail to read %s status register\n", cmd == CMD_READ_STATUS ? "read" : "flag"); @@ -219,7 +240,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { - u32 erase_size; + u32 erase_size, erase_addr; u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; @@ -231,15 +252,20 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) cmd[0] = flash->erase_cmd; while (len) { + erase_addr = offset; + + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &erase_addr); + #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, erase_addr); if (ret < 0) return ret; #endif - spi_flash_addr(offset, cmd); + spi_flash_addr(erase_addr, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], - cmd[2], cmd[3], offset); + cmd[2], cmd[3], erase_addr); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); if (ret < 0) { @@ -258,6 +284,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { unsigned long byte_addr, page_size; + u32 write_addr; size_t chunk_len, actual; u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; @@ -266,8 +293,13 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, cmd[0] = flash->write_cmd; for (actual = 0; actual < len; actual += chunk_len) { + write_addr = offset; + + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &write_addr); + #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, write_addr); if (ret < 0) return ret; #endif @@ -277,7 +309,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (flash->spi->max_write_size) chunk_len = min(chunk_len, flash->spi->max_write_size); - spi_flash_addr(offset, cmd); + spi_flash_addr(write_addr, cmd); debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -322,7 +354,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { u8 *cmd, cmdsz; - u32 remain_len, read_len; + u32 remain_len, read_len, read_addr; int bank_sel = 0; int ret = -1; @@ -346,8 +378,13 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, cmd[0] = flash->read_cmd; while (len) { + read_addr = offset; + + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &read_addr); + #ifdef CONFIG_SPI_FLASH_BAR - bank_sel = spi_flash_bank(flash, offset); + bank_sel = spi_flash_bank(flash, read_addr); if (bank_sel < 0) return ret; #endif @@ -357,7 +394,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, else read_len = remain_len; - spi_flash_addr(offset, cmd); + spi_flash_addr(read_addr, cmd); ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index ac42b60..b9e14c5 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -134,6 +134,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->spi = spi; flash->name = params->name; flash->memory_map = spi->memory_map; + flash->dual_flash = flash->spi->option; /* Assign spi_flash ops */ flash->write = spi_flash_cmd_write_ops; @@ -148,6 +149,8 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256; flash->sector_size = params->sector_size; flash->size = flash->sector_size * params->nr_sectors; + if (flash->dual_flash & SF_DUAL_STACKED_FLASH) + flash->size <<= 1; /* Compute erase sector and command */ if (params->flags & SECT_4K) { @@ -324,7 +327,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi) puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR - if (flash->size > SPI_FLASH_16MB_BOUN) { + if (((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || + ((flash->dual_flash > SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/include/spi.h b/include/spi.h index c8a9d87..d214d82 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,6 +30,7 @@ #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_U_PAGE (1 << 5) /* SPI TX operation modes */ #define SPI_OPM_TX_QPP 1 << 0 @@ -44,6 +45,9 @@ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ SPI_OPM_RX_QIOF +/* SPI bus connection options */ +#define SPI_CONN_DUAL_SHARED 1 << 0 + /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec @@ -62,6 +66,8 @@ * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. + * @option: Varies SPI bus options - separate bus. + * @flags: Indication of SPI flags. */ struct spi_slave { unsigned int bus; @@ -71,6 +77,8 @@ struct spi_slave { unsigned int wordlen; unsigned int max_write_size; void *memory_map; + u8 option; + u8 flags; }; /** diff --git a/include/spi_flash.h b/include/spi_flash.h index 213d659..36f1f03 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -36,6 +36,12 @@ enum spi_read_cmds { #define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST #define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST +/* Dual SPI flash memories */ +enum spi_dual_flash { + SF_SINGLE_FLASH = 0, + SF_DUAL_STACKED_FLASH = 1 << 0, +}; + /** * struct spi_flash_params - SPI/QSPI flash device params structure * @@ -64,6 +70,7 @@ extern const struct spi_flash_params spi_flash_params_table[]; * * @spi: SPI slave * @name: Name of SPI flash + * @dual_flash: Indicates dual flash memories - dual stacked * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -88,6 +95,7 @@ extern const struct spi_flash_params spi_flash_params_table[]; struct spi_flash { struct spi_slave *spi; const char *name; + u8 dual_flash; u32 size; u32 page_size; -- 1.8.3

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