January 2014 - U-Boot

[U-Boot] [PATCH] arm: use canonical sub mnemonic
by Andreas Bießmann 14 Jan '14

14 Jan '14

Building some arm boards with older binutils may produce errors like this: ---8<--- crt0.S: Assembler messages: crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)' --->8--- Use canonical version of the subtract mnemonic to avoid those issues. Reported-by: Alexey Smishlayev <alexey(a)xtech2.lv> Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> --- arch/arm/cpu/armv7/lowlevel_init.S | 2 +- arch/arm/lib/crt0.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 69e3053..f1aea05 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -24,7 +24,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_SPL_BUILD ldr r9, =gdata #else - sub sp, #GD_SIZE + sub sp, sp, #GD_SIZE bic sp, sp, #7 mov r9, sp #endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index ac54b93..dfc2de9 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,7 +67,7 @@ ENTRY(_main) ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - sub sp, #GD_SIZE /* allocate one GD above SP */ + sub sp, sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r9, sp /* GD is above SP */ mov r0, #0 -- 1.7.10.4

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[U-Boot] [PATCH] arm: put .hash, .got.plt and .machine_param back in binaries
by Albert ARIBAUD 14 Jan '14

14 Jan '14

Some targets will build fine but not boot if sections .hash and .got.plt are not present in the binary. Add them back. Also, Exynos machines require .machine_param section in SPL. Add it. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- This patch was prepared with the help of Rajeshwari Birge. Please test, especially if you own an Exynos-based board. arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/exynos/config.mk | 7 +++++++ arch/arm/cpu/u-boot.lds | 3 +-- spl/Makefile | 3 ++- 4 files changed, 11 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/config.mk diff --git a/arch/arm/config.mk b/arch/arm/config.mk index fd3e5fb..5d39d39 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -105,4 +105,4 @@ PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) endif # limit ourselves to the sections we want in the .bin. -OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn +OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn diff --git a/arch/arm/cpu/armv7/exynos/config.mk b/arch/arm/cpu/armv7/exynos/config.mk new file mode 100644 index 0000000..ee0d2da --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) Albert ARIBAUD <albert.u.boot(a)aribaud.net> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +SPL_OBJCFLAGS += -j .machine_param diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 9463a33..4da5d24 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -92,8 +92,6 @@ SECTIONS } .dynsym _end : { *(.dynsym) } - .hash : { *(.hash) } - .got.plt : { *(.got.plt) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } @@ -101,4 +99,5 @@ SECTIONS .interp : { *(.interp*) } .gnu : { *(.gnu*) } .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } } diff --git a/spl/Makefile b/spl/Makefile index 2a787af..b95582b 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -171,7 +171,8 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin endif $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) - $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ + $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O srec $< $(obj)$(SPL_BIN).srec + $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@ GEN_UBOOT = \ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ -- 1.8.3.2

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[U-Boot] [PATCH 0/9] Further support for the kmp204x architecture
by Valentin Longchamp 14 Jan '14

14 Jan '14

This patch series refines the support for the kmp204x designs. The main additions are: - further support of the QRIO CPLD (bootcounter and GPIO) - support of the new kmcoge4 board based on kmp204x - support of I2C deblocking - support for FPGA configuration (PCIe FPGA) - various fixes and smaller enhancements Rainer Boschung (2): kmp204x: support for QRIO1 bootcounter kmp204x: I2C deblocking for I2C-bus1 added Valentin Longchamp (7): kmp204x: introduce QRIO GPIO functions kmp204x: implement workaround for A-006559 kmp204x: add support for the kmcoge4 board kmp204x: update I2C field of RCW KM: add the KM_UBI_PART_BOOT_OPTS #define kmp204x: enable support for SPANSION SPI NOR kmp204x: initial support for PCIe FPGA configuration board/keymile/kmp204x/Makefile | 2 +- board/keymile/kmp204x/kmp204x.c | 124 ++++++++++++++-------------- board/keymile/kmp204x/kmp204x.h | 10 +++ board/keymile/kmp204x/pbi.cfg | 10 +++ board/keymile/kmp204x/pci.c | 85 ++++++++++++++++++++ board/keymile/kmp204x/qrio.c | 147 ++++++++++++++++++++++++++++++++++ board/keymile/kmp204x/rcw_kmp204x.cfg | 2 +- boards.cfg | 1 + include/configs/km/keymile-common.h | 10 ++- include/configs/km/kmp204x-common.h | 15 ++++ include/configs/kmp204x.h | 7 +- 11 files changed, 345 insertions(+), 68 deletions(-) create mode 100644 board/keymile/kmp204x/qrio.c -- 1.8.0.1

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[U-Boot] [PATCH 1/2] socfpga: Adding Scan Manager driver
by Chin Liang See 13 Jan '14

13 Jan '14

Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 ++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 ++++++++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + include/configs/socfpga_cyclone5.h | 1 + 6 files changed, 335 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3e84a0c..4edc5d4 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,4 +9,4 @@ obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c new file mode 100644 index 0000000..30cbb8b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/scan_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_scan_manager *scan_manager_base = + (void *)(SOCFPGA_SCANMGR_ADDRESS); +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Function to check IO scan chain engine status and wait if the engine is + * is active. Poll the IO scan chain engine till maximum iteration reached. + */ +static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter) +{ + uint32_t scanmgr_status; + + scanmgr_status = readl(&scan_manager_base->stat); + + /* Poll the engine until the scan engine is inactive */ + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) + || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) { + + max_iter--; + + if (max_iter > 0) + scanmgr_status = readl(&scan_manager_base->stat); + else + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE; + } + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE; +} + + + +/* Program HPS IO Scan Chain */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain) +{ + + uint16_t tdi_tdo_header; + uint32_t io_program_iter; + uint32_t io_scan_chain_data_residual; + uint32_t residual; + uint32_t i; + uint32_t index = 0; + + /* De-assert reinit if the IO scan chain is intended for HIO */ + if (3 == io_scan_chain_id) + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Check if the scan chain engine is inactive and the + * WFIFO is empty before enabling the IO scan chain + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + return 1; + } + + /* + * Enable IO Scan chain based on scan chain id + * Note: only one chain can be enabled at a time + */ + setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + + /* + * Calculate number of iteration needed for full 128-bit (4 x32-bits) + * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits + */ + io_program_iter = io_scan_chain_len_in_bits >> + IO_SCAN_CHAIN_128BIT_SHIFT; + io_scan_chain_data_residual = io_scan_chain_len_in_bits & + IO_SCAN_CHAIN_128BIT_MASK; + + /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD << + TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* Program IO scan chain in 128-bit iteration */ + for (i = 0; i < io_program_iter; i++) { + + /* write TDI_TDO packet header to scan manager */ + writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte); + + /* calculate array index */ + index = i * 4; + + /* write 4 successive 32-bit IO scan chain data into WFIFO */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 1], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 2], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 3], + &scan_manager_base->fifoquadbyte); + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + return 1; + } + } + + /* Calculate array index for final TDI_TDO packet */ + index = io_program_iter * 4; + + /* Final TDI_TDO packet if any */ + if (0 != io_scan_chain_data_residual) { + + /* + * Calculate number of quad bytes FIFO write + * needed for the final TDI_TDO packet + */ + io_program_iter = io_scan_chain_data_residual >> + IO_SCAN_CHAIN_32BIT_SHIFT; + + /* + * Construct TDI_TDO packet for remaining IO + * scan chain (2 bytes) + */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + ((io_scan_chain_data_residual - 1) + << TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* + * Program the last part of IO scan chain write TDI_TDO packet + * header (2 bytes) to scan manager + */ + writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte); + + for (i = 0; i < io_program_iter; i++) { + /* + * write remaining scan chain data into scan + * manager WFIFO with 4 bytes write + */ + writel(iocsr_scan_chain[index + i], + &scan_manager_base->fifoquadbyte); + } + + index += io_program_iter; + residual = io_scan_chain_data_residual & + IO_SCAN_CHAIN_32BIT_MASK; + + if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) { + /* + * write the last 4B scan chain data + * into scan manager WFIFO + */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifoquadbyte); + + } else { + /* + * write the remaining 1 - 3 bytes scan chain + * data into scan manager WFIFO byte by byte + * to prevent JTAG engine shifting unused data + * from the FIFO and mistaken the data as a + * valid command (even though unused bits are + * set to 0, but just to prevent hardware + * glitch) + */ + for (i = 0; i < residual; i += 8) { + writel(((iocsr_scan_chain[index] >> i) + & IO_SCAN_CHAIN_BYTE_MASK), + &scan_manager_base->fifosinglebyte); + + } + } + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + return 1; + } + } /* if (io_scan_chain_data_residual) */ + + /* Disable IO Scan chain when configuration done*/ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + + return 0; +} + +int scan_mgr_configure_iocsr(void) +{ + int status = 0; + + /* configure the IOCSR through scan chain */ + status |= scan_mgr_io_scan_chain_prg(0, + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table); + status |= scan_mgr_io_scan_chain_prg(1, + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table); + status |= scan_mgr_io_scan_chain_prg(2, + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table); + status |= scan_mgr_io_scan_chain_prg(3, + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table); + return status; +} + + + diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 36a00c3..8a49a1a 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -32,6 +32,10 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + /* configure the IOCSR / IO buffer settings */ + if (scan_mgr_configure_iocsr()) + hang(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h new file mode 100644 index 0000000..dfbfade --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifosinglebyte; + u32 fifodoublebyte; + u32 fifoquadbyte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT (7) + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK (0x7F) + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT (5) + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK (0x1F) + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK (0xFF) + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT (24) + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD (127) + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE (0x80) + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT (8) + +/* IO scan chain engine is idle */ +#define SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE (0) + +/* IO scan chain engine is active */ +#define SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE (1) + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define MAX_WAITING_DELAY_IO_SCAN_ENGINE (100) + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 50c4ebd..8d329cf 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -13,5 +13,6 @@ #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 980636c..981a26b 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" /* * High level configuration -- 1.7.9.5

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[U-Boot] Pull request: u-boot-arm/master
by Albert ARIBAUD 13 Jan '14

13 Jan '14

Hello Tom, The following changes since commit 7f673c99c2d8d1aa21996c5b914f06d784b080ca: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-01-10 10:56:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 4efd69250f6118ebd783867b3809001a1886ce9e: ARM: pxa: Fix OneNAND window access on VPAC270 (2014-01-13 12:39:10 +0100) ---------------------------------------------------------------- Marek Vasut (2): ARM: pxa: Fix OneNAND SPL builds ARM: pxa: Fix OneNAND window access on VPAC270 arch/arm/cpu/pxa/config.mk | 13 +++++++++++++ board/vpac270/u-boot-spl.lds | 1 + include/configs/vpac270.h | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-) Amicalement, -- Albert.

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[U-Boot] Pull request: u-boot-video/master
by Anatolij Gustschin 13 Jan '14

13 Jan '14

Hey Tom, please pull two minor fixes for release. Thanks! Anatolij The following changes since commit 7f673c99c2d8d1aa21996c5b914f06d784b080ca: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-01-10 10:56:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-video.git master for you to fetch changes up to d47c961695dd60ed7e54dc61c16ef3f3173fe3ea: video: ipu reg: Correct reserved array size in struct ipu_idmac (2014-01-12 23:00:06 +0100) ---------------------------------------------------------------- Liu Ying (2): video: ipu reg: Correct reserved1 array size in struct ipu_cm video: ipu reg: Correct reserved array size in struct ipu_idmac drivers/video/ipu_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 13 Jan '14

13 Jan '14

Minor fixes, please apply for 2014.01 The following changes since commit 7f673c99c2d8d1aa21996c5b914f06d784b080ca: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-01-10 10:56:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 3603e31db54ddba820b7a7b9c7659e272f8c65de: usb: ums: wait for usb cable connection before enter ums mode (2014-01-13 12:29:12 +0100) ---------------------------------------------------------------- Inderpal Singh (2): usb: ehci: exynos: set/reset hsic phys usb: exynos5: arndale: Add network support Kuo-Jung Su (2): usb: gadget: fotg210: add w1c interrupt status support usb: gadget: fotg210: EP0 fifo empty indication is non-reliable Przemyslaw Marczak (1): usb: ums: wait for usb cable connection before enter ums mode arch/arm/include/asm/arch-exynos/ehci.h | 14 ++++++++++++++ board/samsung/arndale/arndale.c | 21 +++++++++++++++++++++ common/cmd_usb_mass_storage.c | 24 ++++++++++++++++++++++++ drivers/usb/gadget/fotg210.c | 15 +++++++++++++++ drivers/usb/host/ehci-exynos.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/configs/arndale.h | 4 ++++ include/usb_mass_storage.h | 3 +++ 7 files changed, 122 insertions(+)

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[U-Boot] [PATCH] sf: params: Removed flag SECT_4K for Micron N25Q128
by Siva Durga Prasad Paladugu 13 Jan '14

13 Jan '14

Remove the flag SECT_4K for device N25Q128 as the 4K-byte sub sector erase granularity is available only for top/bottom 8 sectors in some of the N25Q128 chips. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/mtd/spi/sf_params.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 4cdb4c2..daf8fe7 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -73,8 +73,8 @@ const struct spi_flash_params spi_flash_params_table[] = { {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, -- 1.7.4

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[U-Boot] [PATCH] powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI
by Prabhakar Kushwaha 13 Jan '14

13 Jan '14

Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG. Also add their details in README. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Makefile | 4 ++-- README | 7 +++++++ include/configs/B4860QDS.h | 4 ++-- include/configs/P2041RDB.h | 5 +++-- include/configs/T1040QDS.h | 4 ++-- include/configs/T2080QDS.h | 4 ++-- include/configs/T4240QDS.h | 4 ++-- include/configs/corenet_ds.h | 14 +++++++++----- include/configs/km/kmp204x-common.h | 4 ++-- 9 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Makefile b/Makefile index e6f6edb..beee7ec 100644 --- a/Makefile +++ b/Makefile @@ -419,8 +419,8 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ $(obj)u-boot.pbl: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ - -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ + $(obj)tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \ + -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage \ -d $< $@ $(obj)u-boot.sha1: $(obj)u-boot.bin diff --git a/README b/README index a0646c3..bc481b9 100644 --- a/README +++ b/README @@ -472,6 +472,13 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_PBL_PBI + CONFIG_SYS_FSL_PBL_RCW + Provides a tool to build boot Image for PBL(Pre boot loader) + Here PBL can be used to load some instructions and/or data for + pre-initialization. + Define both configs to enable above feature. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c182158..c667229 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -16,8 +16,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index ee71252..2b81cbe 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -18,8 +18,9 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW \ + $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7d0bc04..74d8049 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -32,8 +32,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg #endif /* High Level Configuration Options */ diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index bff001f..b35e107 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -45,8 +45,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg #endif #define CONFIG_SRIO_PCIE_BOOT_MASTER diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index c96df54..1f1177b 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -21,8 +21,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 969b990..3a1826d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -15,15 +15,19 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg #if defined(CONFIG_P3041DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW \ + $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg #elif defined(CONFIG_P4080DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW \ + $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg #elif defined(CONFIG_P5020DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW \ + $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg #elif defined(CONFIG_P5040DS) -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg +#define CONFIG_SYS_FSL_PBL_RCW \ + $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 50330cc..0463fcb 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -24,8 +24,8 @@ #define CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg -#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg /* High Level Configuration Options */ #define CONFIG_BOOKE -- 1.7.9.5

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[U-Boot] [PULL] u-boot-pxa/master
by Marek Vasut 13 Jan '14

13 Jan '14

Minor fixes, please apply for 2014.01 The following changes since commit 7f673c99c2d8d1aa21996c5b914f06d784b080ca: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-01-10 10:56:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-pxa.git master for you to fetch changes up to 4efd69250f6118ebd783867b3809001a1886ce9e: ARM: pxa: Fix OneNAND window access on VPAC270 (2014-01-13 12:39:10 +0100) ---------------------------------------------------------------- Marek Vasut (2): ARM: pxa: Fix OneNAND SPL builds ARM: pxa: Fix OneNAND window access on VPAC270 arch/arm/cpu/pxa/config.mk | 13 +++++++++++++ board/vpac270/u-boot-spl.lds | 1 + include/configs/vpac270.h | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-)

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