January 2014 - U-Boot

[U-Boot] [PATCH] arm: make 'MAKEALL -a' distinguish between arm and aarch64
by Albert ARIBAUD 10 Jan '14

10 Jan '14

The vexpress_aemv8a is the first aarch64 board in U-Boot. As it was introduced, it gets built when "MAKEALL -a arm" is invoked, and fails as this command is run with a 32-bit, not 64-bit, toolchain as the cross-compiler. Introduce 'arch64' as a valid 'MAKEALL -a' argument, treated as 'arm' for all other intents, and change the architecture of the vexpress_aemv8a entry in boards.cfg from 'arm' to 'aarch64'. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- This patch must be applied above the arm64 series and Tom's (amended) patch re config.h. It has been tested and verified to: - correctly exclude vexpress_aemv8a from MAKEALL -a arm - correctly include only vexpress_aemv8a from MAKEALL -a aarch64 - correctly build vexpress_aemv8a from MAKEALL -a aarch64 boards.cfg | 3 +-- mkconfig | 7 +++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/boards.cfg b/boards.cfg index e168590..029553d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -397,7 +397,7 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich(a)gmail.com> Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut(a)gmail.com> Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson(a)gmail.com> -Active arm armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua(a)phytium.com.cn> +Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua(a)phytium.com.cn> Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel(a)googlemail.com> Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> @@ -1242,4 +1242,3 @@ Orphan powerpc mpc8xx - - genietv Orphan powerpc mpc8xx - - mbx8xx MBX - - Orphan powerpc mpc8xx - - mbx8xx MBX860T - - Orphan powerpc mpc8xx - - nx823 NX823 - - - diff --git a/mkconfig b/mkconfig index 40db991..b96c81f 100755 --- a/mkconfig +++ b/mkconfig @@ -85,6 +85,13 @@ if [ "${ARCH}" -a "${ARCH}" != "${arch}" ]; then exit 1 fi +# +# Test above needed aarch64, now we need arm +# +if [ "${arch}" = "aarch64" ]; then + arch="arm" +fi + if [ "$options" ] ; then echo "Configuring for ${BOARD_NAME} - Board: ${CONFIG_NAME}, Options: ${options}" else -- 1.8.3.2

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[U-Boot] [PATCH] armv8: Use __aarch64__ rather than CONFIG_ARM64 in some cases
by Tom Rini 10 Jan '14

10 Jan '14

The toolchain sets __aarch64__ for both LE and BE. In the case of posix_types.h we cannot reliably use config.h as that will lead to problems. In the case of byteorder.h it's clearer to check the EB flag being set in either case instead. Cc: David Feng <fenghua(a)phytium.com.cn> Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/include/asm/byteorder.h | 14 +------------- arch/arm/include/asm/posix_types.h | 6 +++--- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h index 71a9966..20cce76 100644 --- a/arch/arm/include/asm/byteorder.h +++ b/arch/arm/include/asm/byteorder.h @@ -23,22 +23,10 @@ # define __SWAB_64_THRU_32__ #endif -#ifdef CONFIG_ARM64 - -#ifdef __AARCH64EB__ -#include <linux/byteorder/big_endian.h> -#else -#include <linux/byteorder/little_endian.h> -#endif - -#else /* CONFIG_ARM64 */ - -#ifdef __ARMEB__ +#if defined(__ARMEB__) || defined(__AARCH64EB__) #include <linux/byteorder/big_endian.h> #else #include <linux/byteorder/little_endian.h> #endif -#endif /* CONFIG_ARM64 */ - #endif diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h index 9ba9add..fe4483f 100644 --- a/arch/arm/include/asm/posix_types.h +++ b/arch/arm/include/asm/posix_types.h @@ -31,15 +31,15 @@ typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ typedef unsigned long __kernel_size_t; typedef long __kernel_ssize_t; typedef long __kernel_ptrdiff_t; -#else /* CONFIG_ARM64 */ +#else typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; -#endif /* CONFIG_ARM64 */ +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; -- 1.7.9.5

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[U-Boot] [PATCH v16 00/10] arm64 patch
by fenghua＠phytium.com.cn 10 Jan '14

10 Jan '14

From: David Feng <fenghua(a)phytium.com.cn> Changes for v16: - make the patches work with latest recently u-boot. add rela relocation type to OBJCFLAGS definition at arm/config.mk. Changes for v15: - modify boot process, u-boot will run at the highest exception level until it prepare jump to OS. - Fix a few bugs in cache.S.These bug is reported by York Sun <yorksun(a)freescale.com> and Scott Wood <scottwood(a)freescale.com>. - when booting, slaves will wait on WFI, master wakeup slaves by SGI interrupt. - add generic_timer.c to utilize the newest timer architecture. - add gic.S to support gic initialization and interrupt operations, currently only support GICv2. Changes for v14: - Merge rela relocation patches from Scott Wood <scottwood(a)freescale.com>. - Remove all CONFIG_NEED_MANUAL_RELOC and other fixups due to manual relocation. With rela relocation patches them are not needed. - Fix the bug of MEMORY_ATTRIBUTES definition due to assembler. That need put brackets around (MT_NORMAL*8). Otherwise the result is wrong.This bug is reported by York Sun <yorksun(a)freescale.com>. - -msoft-float is not supported by aarch64-gcc, make a test though $(call cc-option,-msoft-float). - Adjust the virtual address space to 42 bits. - Filter armv8 boards from LIST_arm in MAKEALL. - remove gpio.h in asm/arch-armv8/ and move mmu.h to asm/armv8/ directory. - remove vexpress64.dts from this patch, it could be accessed from linux kernel. Changes for v13: - fix the bug of board_r.c and arm/lib/board.c due to CONFIG_NEED_MANUAL_RELOC. adjust initr_serial() in board_r.c to the first entry of init_sequence_r[] and relocate serial_initialize() in arm/lib/board.c, routines of serial_device should be relocated firstly by serial_initialize(), so that printf access the correct puts function, otherwise uninitialized serial_current will be selected as the output device. - fix the bug of dcache_enable(). after mmu_setup the sctrl register value should be fetched again because it has been modifed by mmu_seup() function. This bug is reported by York Sun <yorksun(a)freescale.com>. - add macro branch_if_slave to macro.h, it choose processor with all zero affinity value as the master and is used in start.S. Changes for v12: - custom the patches to new format boards.cfg. Changes for v11: - Replace CONFIG_ARMV8 with CONFIG_ARM64. Currently, it's hard to distinguish what is armv8 specific and what is aarch64 specific, so we use CONFIG_ARM64 only, no CONFIG_ARMV8 used. - rename README.armv8 with README.arm64 and make some modification. Changes for v10: - add weak definition to include/linux/linkage.h and make setup_el2/setup_el3/lowlevel_init weak routines, so them can be easily overridden by processor specific code. - modify s-o-f of 0002-board-support-of-vexpress_aemv8a which use wrong mail address of Bhupesh Sharma. Changes for v9: - add Signed-off-by information to patch "board support of vexpress_aemv8a" which SMC91111 support is integrated from Sharma Bhupesh's patch. - adjust pt_regs struct and add exception state preservation in exception.S. Changes for v8: - Integrate SMC91111 patch of sharma bhupesh. - remove v8_outer_cache* which is not need currently. - Change license tag. - Mov crt0.S/relocate.S/interrupts.c to arm/lib and rename them with _64 suffix. - Make el3/el2 initializing process of start.S as two separate routines. It could be easier to be replaced with processor specific codes. - Remove exception stack save and restore routine, it is unnecessary now. - simplify __weak function declaration. Changes for v7: - Check the patches with checkpatch.pl and get rid of almost all warnings. There are a few warnings still, but I think it should be that. - change printf format in cmd_pxe.c, use %zd indtead of %ld to format size_t type variable. - add macro PGTABLE_SIZE to identify tlb table size. Changes for v6: - Make modification to inappropriate licensed file and bugs according to ScottWood's advice. Thanks Scott for his checking to these patches. - Enable u-boot's running at EL1. - Get rid of compiling warnings originated from cmd_pxe.c. Changes for v5: - fix the generic board_f.c, remove zero_global_data from init_sequence_f array and move it to board_init_f() function with CONFIG_X86 switch. The previous fixup is inaccurate. - Replace __ARMEB__ with __AARCH64EB__ in byteorder.h and unaligned.h, gcc for aarch64 use __AARCH64EB__ and __AARCH64EL__ to identify endian. - Some modification to README.armv8 Changes for v4: - merge arm64 to arm architecture. David Feng (10): fdt_support: 64bit initrd start address support cmd_pxe: remove compiling warnings add weak entry definition arm64: Add tool to statically apply RELA relocations arm64: Turn u-boot.bin back into an ELF file after relocate-rela arm64: Make checkarmreloc accept arm64 relocations arm64: core support arm64: generic board support arm64: board support of vexpress_aemv8a arm64: MAKEALL, filter armv8 boards from LIST_arm MAKEALL | 12 +- Makefile | 39 +++++- arch/arm/config.mk | 7 +- arch/arm/cpu/armv8/Makefile | 17 +++ arch/arm/cpu/armv8/cache.S | 136 +++++++++++++++++++ arch/arm/cpu/armv8/cache_v8.c | 219 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/config.mk | 15 +++ arch/arm/cpu/armv8/cpu.c | 43 ++++++ arch/arm/cpu/armv8/exceptions.S | 113 ++++++++++++++++ arch/arm/cpu/armv8/generic_timer.c | 31 +++++ arch/arm/cpu/armv8/gic.S | 106 +++++++++++++++ arch/arm/cpu/armv8/start.S | 164 +++++++++++++++++++++++ arch/arm/cpu/armv8/tlb.S | 34 +++++ arch/arm/cpu/armv8/transition.S | 83 ++++++++++++ arch/arm/cpu/armv8/u-boot.lds | 89 +++++++++++++ arch/arm/include/asm/armv8/mmu.h | 111 ++++++++++++++++ arch/arm/include/asm/byteorder.h | 12 ++ arch/arm/include/asm/cache.h | 5 + arch/arm/include/asm/config.h | 6 + arch/arm/include/asm/gic.h | 49 ++++++- arch/arm/include/asm/global_data.h | 6 +- arch/arm/include/asm/io.h | 15 ++- arch/arm/include/asm/macro.h | 53 ++++++++ arch/arm/include/asm/posix_types.h | 10 ++ arch/arm/include/asm/proc-armv/ptrace.h | 21 +++ arch/arm/include/asm/proc-armv/system.h | 59 ++++++++- arch/arm/include/asm/system.h | 84 ++++++++++++ arch/arm/include/asm/types.h | 4 + arch/arm/include/asm/u-boot.h | 4 + arch/arm/include/asm/unaligned.h | 2 +- arch/arm/lib/Makefile | 20 ++- arch/arm/lib/board.c | 7 +- arch/arm/lib/bootm.c | 24 ++++ arch/arm/lib/crt0_64.S | 113 ++++++++++++++++ arch/arm/lib/interrupts_64.c | 120 +++++++++++++++++ arch/arm/lib/relocate_64.S | 58 ++++++++ board/armltd/vexpress64/Makefile | 8 ++ board/armltd/vexpress64/vexpress64.c | 56 ++++++++ boards.cfg | 1 + common/board_f.c | 20 ++- common/cmd_pxe.c | 4 +- common/fdt_support.c | 66 +++++----- common/image.c | 1 + doc/README.arm64 | 46 +++++++ examples/standalone/stubs.c | 15 +++ include/configs/vexpress_aemv8a.h | 189 ++++++++++++++++++++++++++ include/image.h | 1 + include/linux/linkage.h | 4 + tools/Makefile | 6 + tools/relocate-rela.c | 189 ++++++++++++++++++++++++++ 50 files changed, 2429 insertions(+), 68 deletions(-) create mode 100644 arch/arm/cpu/armv8/Makefile create mode 100644 arch/arm/cpu/armv8/cache.S create mode 100644 arch/arm/cpu/armv8/cache_v8.c create mode 100644 arch/arm/cpu/armv8/config.mk create mode 100644 arch/arm/cpu/armv8/cpu.c create mode 100644 arch/arm/cpu/armv8/exceptions.S create mode 100644 arch/arm/cpu/armv8/generic_timer.c create mode 100644 arch/arm/cpu/armv8/gic.S create mode 100644 arch/arm/cpu/armv8/start.S create mode 100644 arch/arm/cpu/armv8/tlb.S create mode 100644 arch/arm/cpu/armv8/transition.S create mode 100644 arch/arm/cpu/armv8/u-boot.lds create mode 100644 arch/arm/include/asm/armv8/mmu.h create mode 100644 arch/arm/lib/crt0_64.S create mode 100644 arch/arm/lib/interrupts_64.c create mode 100644 arch/arm/lib/relocate_64.S create mode 100644 board/armltd/vexpress64/Makefile create mode 100644 board/armltd/vexpress64/vexpress64.c create mode 100644 doc/README.arm64 create mode 100644 include/configs/vexpress_aemv8a.h create mode 100644 tools/relocate-rela.c -- 1.7.9.5

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[U-Boot] [PATCH 1/3 V2] esdhc: Workaround for card can't be detected on T4240QDS
by Haijun Zhang 10 Jan '14

10 Jan '14

Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang <Haijun.Zhang(a)freescale.com> --- changes for V2: - Add the judgement condition for this broken card drivers/mmc/fsl_esdhc.c | 9 +++++++++ include/configs/T4240QDS.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 134a02d..b3b5f37 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -548,6 +548,15 @@ static int esdhc_getcd(struct mmc *mmc) struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; + /* + * Card detecting pin is not functional on T4240QDS with rev 1.0 SoC. + * Presuming card is present. + */ +#if defined(CONFIG_T4240QDS) + if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || + IS_SVR_REV(get_svr(), 1, 0)) + return 1; +#endif while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index c96df54..955e6b9 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG5 0x55 +#define QIXIS_MUX_SDHC 2 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) #define CONFIG_SYS_CSPR3_EXT (0xf) -- 1.8.4.1

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[U-Boot] [PATCH] powerpc: mpc8xx: remove redandant CONFIG_8xx definition
by Masahiro Yamada 10 Jan '14

10 Jan '14

We do not define CONFIG_8xx in source files because it is defined in arch/powerpc/cpu/mpc8xx/config.mk Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/powerpc/cpu/mpc8xx/kgdb.S | 2 -- arch/powerpc/cpu/mpc8xx/start.S | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index ac1fe8f..e774d1e 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -9,8 +9,6 @@ #include <mpc8xx.h> #include <version.h> -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 99cafbd..f8aa93d 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -26,8 +26,6 @@ #include <mpc8xx.h> #include <version.h> -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> -- 1.8.3.2

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[U-Boot] [PATCH] powerpc: mpc83xx: remove redandant CONFIG_MPC83xx definition
by Masahiro Yamada 10 Jan '14

10 Jan '14

We do not have to define CONFIG_MPC83xx in board config headers because it is defined in arch/powerpc/cpu/mpc83xx/config.mk. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- include/configs/MERGERBOX.h | 1 - include/configs/MPC8308RDB.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC8360EMDS.h | 1 - include/configs/MPC8360ERDK.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/MVBLM7.h | 1 - include/configs/SIMPC8313.h | 1 - include/configs/TQM834x.h | 1 - include/configs/km/km8309-common.h | 1 - include/configs/mpc8308_p1m.h | 1 - include/configs/sbc8349.h | 1 - include/configs/ve8313.h | 1 - include/configs/vme8349.h | 1 - 20 files changed, 20 deletions(-) diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h index 8a40029..3dcea0b 100644 --- a/include/configs/MERGERBOX.h +++ b/include/configs/MERGERBOX.h @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC837x 1 #define CONFIG_MPC8377 1 diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 0131b9c..bf974fd 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 07719e9..69b2cb1 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -14,7 +14,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index aedb529..3dd52ce 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -35,7 +35,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC831x 1 /* MPC831x CPU family */ #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c4c771b..65a63e2 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -14,7 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f5b6202..1735b3c 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,7 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 7640d06..6b7d648 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index ffb9a15..398918a 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -47,7 +47,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC83xx 1 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index d4c82cd..aefde74 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -14,7 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 01e7ac7..1b8bad1 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -19,7 +19,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index f52e77a..695e47b 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 938f7ab..1d1f4c0 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index efdf1aa..30af691 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC834x 1 #define CONFIG_MPC8343 1 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 40fb63d..46157cc 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -16,7 +16,6 @@ #define CONFIG_NAND_U_BOOT #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 15cf2bd..6762e3a 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x specific */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 47355ab..29c6f60 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -15,7 +15,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index de7a53a..4ae9afd 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b7f83e0..2516a3e 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -19,7 +19,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 5cf4ae5..00787bb 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_VE8313 1 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 7ecbafe..175311c 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -29,7 +29,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ -- 1.8.3.2

1 0

[U-Boot] [PATCH] powerpc: mpc5xxx: remove redandant CONFIG_MPC5xxx definition
by Masahiro Yamada 10 Jan '14

10 Jan '14

We do not have to define CONFIG_MPC5xxx in board config headers (and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/powerpc/cpu/mpc5xxx/start.S | 2 -- include/configs/BC3450.h | 1 - include/configs/IceCube.h | 1 - include/configs/MVBC_P.h | 1 - include/configs/MVSMR.h | 1 - include/configs/PM520.h | 1 - include/configs/TB5200.h | 1 - include/configs/TOP5200.h | 1 - include/configs/TQM5200.h | 1 - include/configs/Total5200.h | 1 - include/configs/a3m071.h | 1 - include/configs/a4m072.h | 1 - include/configs/aev.h | 1 - include/configs/canmb.h | 1 - include/configs/cm5200.h | 1 - include/configs/cpci5200.h | 1 - include/configs/digsy_mtc.h | 1 - include/configs/galaxy5200.h | 1 - include/configs/hmi1001.h | 1 - include/configs/inka4x0.h | 1 - include/configs/ipek01.h | 1 - include/configs/jupiter.h | 1 - include/configs/manroland/mpc5200-common.h | 1 - include/configs/mcc200.h | 1 - include/configs/mecp5200.h | 1 - include/configs/motionpro.h | 1 - include/configs/munices.h | 1 - include/configs/o2dnt-common.h | 1 - include/configs/pcm030.h | 1 - include/configs/pf5200.h | 1 - include/configs/v38b.h | 1 - 31 files changed, 32 deletions(-) diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 84ab41e..02c706e 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -14,8 +14,6 @@ #include <mpc5xxx.h> #include <version.h> -#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 377db7b..ad69d33 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -22,7 +22,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_TQM5200 1 /* ... on a TQM5200 module */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 52368f8..ca49a99 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -13,7 +13,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 9d49de7..99e4e90 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -13,7 +13,6 @@ #include <version.h> -#define CONFIG_MPC5xxx 1 #define CONFIG_MPC5200 1 #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h index f69b9a8..bb565b6 100644 --- a/include/configs/MVSMR.h +++ b/include/configs/MVSMR.h @@ -13,7 +13,6 @@ #include <version.h> -#define CONFIG_MPC5xxx 1 #define CONFIG_MPC5200 1 #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 557a8ba..767ffdc 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -14,7 +14,6 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_PM520 1 /* ... on PM520 board */ #define CONFIG_SYS_TEXT_BASE 0xfff00000 diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 90f7fc4..af550aa 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -16,7 +16,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #define CONFIG_TB5200 1 /* ... on a TB5200 base board */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 7aba009..e19201f 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -25,7 +25,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ #define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 13500ee..2f91840 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -16,7 +16,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index acc4fdc..d76235e 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -24,7 +24,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index d151869..1c2ac3a 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -13,7 +13,6 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_A3M071 /* ... on A3M071 board */ #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 6473702..7ff18ec 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -16,7 +16,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/aev.h b/include/configs/aev.h index 0eafb3c..d853419 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -16,7 +16,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index d929bde..3511d10 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -13,7 +13,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ #define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index ac3d6bd..1200511 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -11,7 +11,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index db5cead..d1f2da3 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -24,7 +24,6 @@ */ #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index bc5853e..e2aa0af 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -20,7 +20,6 @@ * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 560363d..c200ea9 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -23,7 +23,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 1c74a2e..20ed1bb 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -13,7 +13,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_HMI1001 1 /* HMI1001 board */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 608d759..c1cfd56 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -16,7 +16,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_INKA4X0 1 /* INKA4x0 board */ diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index 408168b..c17292e 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -16,7 +16,6 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPX5200 1 /* ... on MPX5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ #define CONFIG_IPEK01 /* Motherboard is ipek01 */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 71e8ece..c3a6d7e 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -13,7 +13,6 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* especially an MPC5200 */ #define CONFIG_JUPITER 1 /* ... on Jupiter board */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index 21b17f6..3e4a464 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -12,7 +12,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 1b9e2d0..a236191 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -14,7 +14,6 @@ */ #define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MCC200 1 /* ... on MCC200 board */ /* diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 047e171..68f03ea 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -24,7 +24,6 @@ */ #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_MECP5200 1 /* ... on MECP5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 8071ac3..c9715d2 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -15,7 +15,6 @@ */ /* CPU and board */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ diff --git a/include/configs/munices.h b/include/configs/munices.h index 3bda8eb..f6ac303 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -11,7 +11,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ #define CONFIG_MUNICES 1 /* ... on MUNICes board */ diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index ce08454..18714ea 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -16,7 +16,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 5c61889..6bc195a 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -20,7 +20,6 @@ High Level Configuration Options (easy to change) -----------------------------------------------------------------------------*/ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ #define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 327be3f..61bcbbe 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -23,7 +23,6 @@ */ #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_PF5200 1 /* ... on PF5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 0c54435..7f6b0c7 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -12,7 +12,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_V38B 1 /* ...on V38B board */ -- 1.8.3.2

1 0

[U-Boot] [PATCH] powerpc: ppc4xx: remove redandant CONFIG_4xx definition
by Masahiro Yamada 10 Jan '14

10 Jan '14

We do not have to define CONFIG_4xx in board config headers because it is defined in arch/powerpc/cpu/ppc4xx/config.mk. include/configs/JSE.h defines "CONFIG_4x", not "CONFIG_4xx". I believe it is a typo because "CONFIG_4x" is not used at all in other files. So, I also deleted "CONFIG_4x" in include/configs/JSE.h. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- include/configs/APC405.h | 1 - include/configs/AR405.h | 1 - include/configs/ASH405.h | 1 - include/configs/CATcenter.h | 1 - include/configs/CMS700.h | 1 - include/configs/CPCI2DP.h | 1 - include/configs/CPCI405.h | 1 - include/configs/CPCI4052.h | 1 - include/configs/CPCI405AB.h | 1 - include/configs/CPCI405DT.h | 1 - include/configs/CPCIISER4.h | 1 - include/configs/CRAYL1.h | 1 - include/configs/DP405.h | 1 - include/configs/DU405.h | 1 - include/configs/DU440.h | 1 - include/configs/G2000.h | 1 - include/configs/HH405.h | 1 - include/configs/HUB405.h | 1 - include/configs/JSE.h | 2 -- include/configs/KAREF.h | 1 - include/configs/METROBOX.h | 1 - include/configs/MIP405.h | 1 - include/configs/OCRTC.h | 1 - include/configs/PCI405.h | 1 - include/configs/PIP405.h | 1 - include/configs/PLU405.h | 1 - include/configs/PMC405.h | 1 - include/configs/PMC405DE.h | 1 - include/configs/PMC440.h | 1 - include/configs/PPChameleonEVB.h | 1 - include/configs/VOH405.h | 1 - include/configs/VOM405.h | 1 - include/configs/W7OLMC.h | 1 - include/configs/W7OLMG.h | 1 - include/configs/WUH405.h | 1 - include/configs/acadia.h | 1 - include/configs/alpr.h | 1 - include/configs/bamboo.h | 1 - include/configs/bluestone.h | 1 - include/configs/bubinga.h | 1 - include/configs/canyonlands.h | 1 - include/configs/csb272.h | 1 - include/configs/csb472.h | 1 - include/configs/dlvision-10g.h | 1 - include/configs/dlvision.h | 1 - include/configs/ebony.h | 1 - include/configs/gdppc440etx.h | 1 - include/configs/icon.h | 1 - include/configs/intip.h | 1 - include/configs/io.h | 1 - include/configs/io64.h | 1 - include/configs/iocon.h | 1 - include/configs/katmai.h | 1 - include/configs/kilauea.h | 1 - include/configs/korat.h | 1 - include/configs/luan.h | 1 - include/configs/lwmon5.h | 1 - include/configs/makalu.h | 1 - include/configs/neo.h | 1 - include/configs/ocotea.h | 1 - include/configs/p3p440.h | 1 - include/configs/pcs440ep.h | 1 - include/configs/quad100hd.h | 1 - include/configs/redwood.h | 1 - include/configs/sbc405.h | 1 - include/configs/sc3.h | 1 - include/configs/sequoia.h | 1 - include/configs/t3corp.h | 1 - include/configs/taihu.h | 1 - include/configs/taishan.h | 1 - include/configs/walnut.h | 1 - include/configs/xilinx-ppc405.h | 1 - include/configs/xilinx-ppc440.h | 1 - include/configs/xpedite1000.h | 1 - include/configs/yosemite.h | 1 - include/configs/yucca.h | 1 - include/configs/zeus.h | 1 - 77 files changed, 78 deletions(-) diff --git a/include/configs/APC405.h b/include/configs/APC405.h index afc9ae8..2678f50 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -19,7 +19,6 @@ * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_APCG405 1 /* ...on a APC405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/AR405.h b/include/configs/AR405.h index a4bd4b1..45dd46a 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_AR405 1 /* ...on a AR405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 2f53407..2ff9b59 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_ASH405 1 /* ...on a ASH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index ba5dba5..27539d2 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -59,7 +59,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 0bb22be..5b872f6 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOM405 1 /* ...on a VOM405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 85720a5..05106cd 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 793ee75..34252d4 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 53cf498..bf85439 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index ce31032..7d58e9d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ #define CONFIG_CPCI405AB 1 /* ...and special AB version */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index f09fcb0..c2598a3 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index ae36411..25365f7 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index a4ce6c3..788fa0f 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -19,7 +19,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ /* * Note: I make an "image" from U-Boot itself, which prefixes 0x40 diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 74e79e2..68e4a7f 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_DP405 1 /* ...on a DP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 433077d..9be2310 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -17,7 +17,6 @@ * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_DU405 1 /* ...on a DU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 71be122..be5494b 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -21,7 +21,6 @@ */ #define CONFIG_DU440 1 /* Board is esd DU440 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 5c537ce..0c66092 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_G2000 1 /* ...on a PLU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 26b3bdf..033dcbf 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -24,7 +24,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_HH405 1 /* ...on a HH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 5e16653..1783b9f 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_HUB405 1 /* ...on a HUB405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 5738ea9..5cc2557 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -20,8 +20,6 @@ #define CONFIG_JSE 1 /* JSE has a PPC405GPr */ #define CONFIG_405GP 1 - /* ... which is a 4xxx series */ -#define CONFIG_4x 1 /* ... with a 33MHz OSC. connected to the SysCLK input */ #define CONFIG_SYS_CLK_FREQ 33333333 /* ... with on-chip memory here (4KBytes) */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 39eb2ef..546b725 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -23,7 +23,6 @@ #define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 6715435..69ab5bb 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -89,7 +89,6 @@ #define CONFIG_METROBOX 1 /* Board is Metrobox */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 6042a1e..68824fd 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -17,7 +17,6 @@ * (easy to change) ***********************************************************/ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_MIP405 1 /* ...on a MIP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 7baba93..4680afe 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_OCRTC 1 /* ...on a OCRTC board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 3b5c73e..0989407 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -20,7 +20,6 @@ * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PCI405 1 /* ...on a PCI405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 29888b4..a6f505a 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -17,7 +17,6 @@ * (easy to change) ***********************************************************/ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PIP405 1 /* ...on a PIP405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 947b3d8..8705161 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PLU405 1 /* ...on a PLU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 9fab4b2..c68d9a6 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -13,7 +13,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PMC405 1 /* ...on a PMC405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 0984095..94b9547 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index efe6960..fd39109 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -24,7 +24,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF90000 diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 1b17afa..e277d0d 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -59,7 +59,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3d46afe..d4a4b68 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOH405 1 /* ...on a VOH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 319a9a2..c06897b 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -16,7 +16,6 @@ * (easy to change) */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOM405 1 /* ...on a VOM405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 00a24ab..895ad46 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ #define CONFIG_W7OLMC 1 /* ...specifically an LMC */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 8ed2fa2..2a38116 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ #define CONFIG_W7OLMG 1 /* ...specifically an LMG */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index d2038e5..e4f0d19 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -19,7 +19,6 @@ #define CONFIG_IDENT_STRING " $Name: $" #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_WUH405 1 /* ...on a WUH405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/acadia.h b/include/configs/acadia.h index f23d549..5f3b5f9 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -16,7 +16,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_ACADIA 1 /* Board is Acadia */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 08bba36..7849b22 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -14,7 +14,6 @@ #define CONFIG_ALPR 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 326e3d6..97da1e9 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -17,7 +17,6 @@ #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h index 33e0496..8bd71c6 100644 --- a/include/configs/bluestone.h +++ b/include/configs/bluestone.h @@ -16,7 +16,6 @@ #define CONFIG_APM821XX 1 /* APM821XX series */ #define CONFIG_HOSTNAME bluestone -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 2b9c1c9..ea7b104 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -18,7 +18,6 @@ */ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index f6faeec..620a0f5 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -33,7 +33,6 @@ #endif #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 8a848be..a5c6f84 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 5c03417..6aa98ef 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index c527be4..31fc65d 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index c97963a..1e86c55 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_DLVISION 1 /* on a Neo board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 8dc654e..3f0ad69 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -17,7 +17,6 @@ #define CONFIG_EBONY 1 /* Board is ebony */ #define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index a6f1aff..6810b3b 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -21,7 +21,6 @@ #define CONFIG_440GR 1 /* Specific PPC440GR support */ #define CONFIG_HOSTNAME gdppc440etx #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/icon.h b/include/configs/icon.h index eafcf5a..bbe9b59 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -16,7 +16,6 @@ * High Level Configuration Options */ #define CONFIG_ICON 1 /* Board is icon */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ diff --git a/include/configs/intip.h b/include/configs/intip.h index d3d7a44..b56b3aa 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -30,7 +30,6 @@ #define CONFIG_IDENT_STRING " intip 0.06" #endif #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/io.h b/include/configs/io.h index 2d67cfc..7f86767 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_IO 1 /* on a Io board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/io64.h b/include/configs/io64.h index 39ed285..6915b20 100644 --- a/include/configs/io64.h +++ b/include/configs/io64.h @@ -20,7 +20,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_IO64 1 /* Board is Io64 */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 788c715..d34b91d 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -9,7 +9,6 @@ #define __CONFIG_H #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_IOCON 1 /* on a IoCon board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/katmai.h b/include/configs/katmai.h index ca0df2d..fa72eb0 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -18,7 +18,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_KATMAI 1 /* Board is Katmai */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index d2acc28..0695d2d 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -19,7 +19,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_KILAUEA 1 /* Board is Kilauea */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 811ff99..5494a60 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -22,7 +22,6 @@ * High Level Configuration Options */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 #ifdef CONFIG_KORAT_PERMANENT diff --git a/include/configs/luan.h b/include/configs/luan.h index 67f75c7..15e4a7e 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -17,7 +17,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_LUAN 1 /* Board is Luan */ #define CONFIG_440SP 1 /* Specific PPC440SP support */ -#define CONFIG_4xx 1 /* PPC4xx family */ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index e9c8d8f..07ddfc4 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -22,7 +22,6 @@ #define CONFIG_LWMON5 1 /* Board is lwmon5 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifdef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index d6207eb..fd4c26e 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -19,7 +19,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_MAKALU 1 /* Board is Makalu */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */ diff --git a/include/configs/neo.h b/include/configs/neo.h index 62ea8ec..d549985 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -10,7 +10,6 @@ #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_NEO 1 /* on a Neo board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index f3fb585..4ff2f05 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -26,7 +26,6 @@ #define CONFIG_OCOTEA 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 1fdd602..225567b 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -20,7 +20,6 @@ #define CONFIG_P3P440 1 /* Board is P3P440 */ #define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 5a5fe7f..e6e06f2 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -23,7 +23,6 @@ #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 20d6178..e91e805 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -15,7 +15,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_QUAD100HD 1 /* Board is Quad100hd */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EP 1 /* Specifc 405EP support*/ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/redwood.h b/include/configs/redwood.h index c8bd02e..84d1e58 100644 --- a/include/configs/redwood.h +++ b/include/configs/redwood.h @@ -12,7 +12,6 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC460 family */ #define CONFIG_460SX 1 /* ... PPC460 family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 2fd1dc4..69dc210 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -17,7 +17,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 9a11150..14e033d 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -43,7 +43,6 @@ */ #define CONFIG_SC3 1 -#define CONFIG_4xx 1 #define CONFIG_405GP 1 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index d2dedac..0e21ee3 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -27,7 +27,6 @@ #define CONFIG_HOSTNAME rainier #endif #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 9ab9924..502e795 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -16,7 +16,6 @@ */ #define CONFIG_460GT 1 /* Specific PPC460GT */ #define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 4ebaf2e..5c0ce7a 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -13,7 +13,6 @@ #define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_TAIHU 1 /* on a taihu board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 3dbfc6a..3d5c351 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -18,7 +18,6 @@ #define CONFIG_TAISHAN 1 /* Board is taishan */ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 diff --git a/include/configs/walnut.h b/include/configs/walnut.h index a569182..8b803a2 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -18,7 +18,6 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ /* ...or on a SYCAMORE board */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h index 431e331..a0151fe 100644 --- a/include/configs/xilinx-ppc405.h +++ b/include/configs/xilinx-ppc405.h @@ -15,7 +15,6 @@ /* cpu parameter */ #define CONFIG_405 1 -#define CONFIG_4xx 1 #define CONFIG_XILINX_405 1 #include <configs/xilinx-ppc.h> diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h index 2ec3dd1..f457008 100644 --- a/include/configs/xilinx-ppc440.h +++ b/include/configs/xilinx-ppc440.h @@ -9,7 +9,6 @@ #define __CONFIG_GEN_H /*CPU*/ -#define CONFIG_4xx 1 #define CONFIG_440 1 #define CONFIG_XILINX_440 1 diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index eb193f8..ca322b2 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -18,7 +18,6 @@ #define CONFIG_XPEDITE1000 1 #define CONFIG_SYS_BOARD_NAME "XPedite1000" #define CONFIG_SYS_FORM_PMC 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #define CONFIG_440GX 1 /* 440 GX */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 2dd742e..8508a80 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -23,7 +23,6 @@ #define CONFIG_HOSTNAME yellowstone #endif #define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 5d584fb..76717e4 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -18,7 +18,6 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index d8aeb37..4d7a7fc 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -15,7 +15,6 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_ZEUS 1 /* Board is Zeus */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EP 1 /* Specifc 405EP support*/ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 -- 1.8.3.2

1 0

[U-Boot] [PATCH v2] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
by Chin Liang See 09 Jan '14

09 Jan '14

To add the Cadence SPI driver support for Altera SOCFPGA. It required information such as clocks and timing from platform's configuration header file within include/configs folder Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Jagan Teki <jagannadh.teki(a)gmail.com> Cc: Gerhard Sittig <gsi(a)denx.de> --- Changes for v2 - Combine driver into single C file instead of 2 - Added documentation on the macro used - Using structure for registers instead of macro --- doc/README.socfpga | 47 ++ drivers/spi/Makefile | 1 + drivers/spi/cadence_qspi.c | 1018 ++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/cadence_qspi.h | 170 ++++++++ 4 files changed, 1236 insertions(+) create mode 100644 drivers/spi/cadence_qspi.c create mode 100644 drivers/spi/cadence_qspi.h diff --git a/doc/README.socfpga b/doc/README.socfpga index cfcbbfe..242af97 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -51,3 +51,50 @@ the card #define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 -> The clock rate to controller. Do note the controller have a wrapper which divide the clock from PLL by 4. + +-------------------------------------------- +cadence_qspi +-------------------------------------------- +Here are macro and detailed configuration required to enable Cadence QSPI +controller support within SOCFPGA + +#define CONFIG_SPI_FLASH +-> To enable the SPI flash framework support + +#define CONFIG_CMD_SF +-> To enable the console support for SPI flash + +#define CONFIG_SF_DEFAULT_SPEED (50000000) +-> To set the target SPI clock frequency in Hz + +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +-> To set the SPI mode (CPOL & CPHA). Normally use mode 3 for serial NOR flash + +#define CONFIG_SPI_FLASH_QUAD (1) +-> To enable the Quad IO mode for performance boost + +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION +-> To enable the SPI flash support for vendor Micron and Spansion + +#define CONFIG_CQSPI_BASE (SOCFPGA_QSPIREGS_ADDRESS) +#define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS) +-> To specify the base address for controller CSR base and AHB data base addr + +#define CONFIG_CQSPI_REF_CLK (400000000) +-> The clock frequency supplied from PLL to the QSPI controller + +#define CONFIG_CQSPI_PAGE_SIZE (256) +-> To define the page size of serial flash in bytes + +#define CONFIG_CQSPI_BLOCK_SIZE (16) +-> To define the block size of serial flash in pages + +#define CONFIG_CQSPI_DECODER (0) +-> To enable the 4-to-16 decoder which enable up to 16 serial flash devices + +#define CONFIG_CQSPI_TSHSL_NS (200) +#define CONFIG_CQSPI_TSD2D_NS (255) +#define CONFIG_CQSPI_TCHSH_NS (20) +#define CONFIG_CQSPI_TSLCH_NS (20) +-> Configure the controller based on serial flash device timing characteristic diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ed4ecd7..b8d56ea 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c new file mode 100644 index 0000000..4712b45 --- /dev/null +++ b/drivers/spi/cadence_qspi.c @@ -0,0 +1,1018 @@ +/* + * (C) Copyright 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <malloc.h> +#include <spi.h> +#include "cadence_qspi.h" + +static int qspi_is_init; +static unsigned int qspi_calibrated_hz; +static unsigned int qspi_calibrated_cs; + +static const struct cadence_qspi *cadence_qspi_base = (void *)QSPI_BASE; + +#define to_cadence_qspi_slave(s) \ + container_of(s, struct cadence_qspi_slave, slave) + +#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \ + ((((tdelay_ns) - (tsclk_ns)) / (tref_ns))) + +#define CQSPI_GET_WR_SRAM_LEVEL() \ + ((readl(&cadence_qspi_base->sramfill) >> \ + CQSPI_REG_SRAMLEVEL_WR_LSB) & CQSPI_REG_SRAMLEVEL_WR_MASK) + +static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf, + unsigned int addr_width) +{ + unsigned int addr; + + addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2]; + + if (addr_width == 4) + addr = (addr << 8) | addr_buf[3]; + + return addr; +} + +static void cadence_qspi_apb_read_fifo_data(void *dest, + const void *src_ahb_addr, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest; + unsigned int *src_ptr = (unsigned int *)src_ahb_addr; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + *dest_ptr = readl(src_ptr); + remaining -= CQSPI_FIFO_WIDTH; + } else { + /* dangling bytes */ + temp = readl(src_ptr); + memcpy(dest_ptr, &temp, remaining); + break; + } + dest_ptr++; + } + + return; +} + +static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr, + const void *src, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; + unsigned int *src_ptr = (unsigned int *)src; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + writel(*src_ptr, dest_ptr); + remaining -= sizeof(unsigned int); + } else { + /* dangling bytes */ + memcpy(&temp, src_ptr, remaining); + writel(temp, dest_ptr); + break; + } + src_ptr++; + } + + return; +} + +/* Read from SRAM FIFO with polling SRAM fill level. */ +static int qspi_read_sram_fifo_poll(void *dest_addr, + const void *src_addr, unsigned int num_bytes) +{ + unsigned int remaining = num_bytes; + unsigned int retry; + unsigned int sram_level = 0; + unsigned char *dest = (unsigned char *)dest_addr; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = (readl(&cadence_qspi_base->sramfill) >> + CQSPI_REG_SRAMLEVEL_RD_LSB) & + CQSPI_REG_SRAMLEVEL_RD_MASK; + if (sram_level) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: No receive data after polling for %d " + "times\n", CQSPI_REG_RETRY); + return -1; + } + + sram_level *= CQSPI_FIFO_WIDTH; + sram_level = sram_level > remaining ? remaining : sram_level; + + /* Read data from FIFO. */ + cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level); + dest += sram_level; + remaining -= sram_level; + udelay(1); + } + return 0; +} + + +/* Write to SRAM FIFO with polling SRAM fill level. */ +static int qpsi_write_sram_fifo_push(void *dest_addr, + const void *src_addr, unsigned int num_bytes) +{ + unsigned int retry = CQSPI_REG_RETRY; + unsigned int sram_level; + unsigned int wr_bytes; + unsigned char *src = (unsigned char *)src_addr; + int remaining = num_bytes; + unsigned int page_size = CONFIG_CQSPI_PAGE_SIZE; + unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = CQSPI_GET_WR_SRAM_LEVEL(); + if (sram_level <= sram_threshold_words) + break; + } + if (!retry) { + printf("QSPI: SRAM fill level (0x%08x) " + "not hit lower expected level (0x%08x)", + sram_level, sram_threshold_words); + return -1; + } + /* Write a page or remaining bytes. */ + wr_bytes = (remaining > page_size) ? + page_size : remaining; + + cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes); + src += wr_bytes; + remaining -= wr_bytes; + } + + return 0; +} + +static void cadence_qspi_apb_controller_enable(void) +{ + setbits_le32(&cadence_qspi_base->cfg, CQSPI_REG_CONFIG_ENABLE_MASK); +} + +static void cadence_qspi_apb_controller_disable(void) +{ + clrbits_le32(&cadence_qspi_base->cfg, CQSPI_REG_CONFIG_ENABLE_MASK); +} + +/* Return 1 if idle, otherwise return 0 (busy). */ +static unsigned int cadence_qspi_wait_idle(void) +{ + unsigned int start, count = 0; + /* timeout in unit of ms */ + unsigned int timeout = 5000; + + start = get_timer(0); + for ( ; get_timer(start) < timeout ; ) { + if ((readl(&cadence_qspi_base->cfg) >> + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) + count++; + else + count = 0; + /* + * Ensure the QSPI controller is in true idle state after + * reading back the same idle status consecutively + */ + if (count >= CQSPI_POLL_IDLE_RETRY) + return 1; + } + + /* Timeout, still in busy mode. */ + printf("QSPI: QSPI is still busy after poll for %d times.\n", + CQSPI_REG_RETRY); + return 0; +} + +static void cadence_qspi_apb_readdata_capture(unsigned int bypass, + unsigned int delay) +{ + unsigned int reg; + cadence_qspi_apb_controller_disable(); + + reg = readl(&cadence_qspi_base->rddatacap); + + if (bypass) + reg |= (1 << CQSPI_REG_RD_DATA_CAPTURE_BYPASS_LSB); + else + reg &= ~(1 << CQSPI_REG_RD_DATA_CAPTURE_BYPASS_LSB); + + reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK + << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + + reg |= ((delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK) + << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + + writel(reg, &cadence_qspi_base->rddatacap); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_config_baudrate_div(unsigned int ref_clk_hz, + unsigned int sclk_hz) +{ + unsigned int reg; + unsigned int div; + + cadence_qspi_apb_controller_disable(); + reg = readl(&cadence_qspi_base->cfg); + reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); + + div = ref_clk_hz / sclk_hz; + + if (div > 32) + div = 32; + + /* Check if even number. */ + if ((div & 1)) + div = (div / 2); + else + div = (div / 2) - 1; + + debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, + ref_clk_hz, sclk_hz, div); + + div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; + reg |= div; + writel(reg, &cadence_qspi_base->cfg); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_set_clk_mode(unsigned int clk_pol, + unsigned int clk_pha) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(); + reg = readl(&cadence_qspi_base->cfg); + reg &= ~(1 << + (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); + + reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); + reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); + + writel(reg, &cadence_qspi_base->cfg); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_chipselect(unsigned int chip_select, + unsigned int decoder_enable) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(); + + debug("%s : chipselect %d decode %d\n", __func__, chip_select, + decoder_enable); + + reg = readl(&cadence_qspi_base->cfg); + /* docoder */ + if (decoder_enable) + reg |= CQSPI_REG_CONFIG_DECODE_MASK; + else { + reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; + /* Convert CS if without decoder. + * CS0 to 4b'1110 + * CS1 to 4b'1101 + * CS2 to 4b'1011 + * CS3 to 4b'0111 + */ + chip_select = 0xF & ~(1 << chip_select); + } + + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK + << CQSPI_REG_CONFIG_CHIPSELECT_LSB); + reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) + << CQSPI_REG_CONFIG_CHIPSELECT_LSB; + writel(reg, &cadence_qspi_base->cfg); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_delay(unsigned int ref_clk, unsigned int sclk_hz, + unsigned int tshsl_ns, unsigned int tsd2d_ns, + unsigned int tchsh_ns, unsigned int tslch_ns) +{ + unsigned int ref_clk_ns; + unsigned int sclk_ns; + unsigned int tshsl, tchsh, tslch, tsd2d; + unsigned int reg; + + cadence_qspi_apb_controller_disable(); + + /* Convert to ns. */ + ref_clk_ns = (1000000000) / ref_clk; + + /* Convert to ns. */ + sclk_ns = (1000000000) / sclk_hz; + + /* Plus 1 to round up 1 clock cycle. */ + tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; + tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; + tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; + tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; + + reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) + << CQSPI_REG_DELAY_TSHSL_LSB); + reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) + << CQSPI_REG_DELAY_TCHSH_LSB); + reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) + << CQSPI_REG_DELAY_TSLCH_LSB); + reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) + << CQSPI_REG_DELAY_TSD2D_LSB); + writel(reg, &cadence_qspi_base->delay); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_controller_init(void) +{ + unsigned reg; + + cadence_qspi_apb_controller_disable(); + + /* Configure the device size and address bytes */ + reg = readl(&cadence_qspi_base->devsz); + /* Clear the previous value */ + reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); + reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); + reg |= (CONFIG_CQSPI_PAGE_SIZE << CQSPI_REG_SIZE_PAGE_LSB); + reg |= (CONFIG_CQSPI_BLOCK_SIZE << CQSPI_REG_SIZE_BLOCK_LSB); + writel(reg, &cadence_qspi_base->devsz); + + /* Configure the remap address register, no remap */ + writel(0, &cadence_qspi_base->remapaddr); + + /* Disable all interrupts */ + writel(0, &cadence_qspi_base->irqmask); + + cadence_qspi_apb_controller_enable(); + return; +} + +static int cadence_qspi_apb_exec_flash_cmd(unsigned int reg) +{ + unsigned int retry = CQSPI_REG_RETRY; + + /* Write the CMDCTRL without start execution. */ + writel(reg, &cadence_qspi_base->flashcmd); + /* Start execute */ + reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; + writel(reg, &cadence_qspi_base->flashcmd); + + while (retry--) { + reg = readl(&cadence_qspi_base->flashcmd); + if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: flash command execution timeout\n"); + return -EIO; + } + + /* Polling QSPI idle status. */ + if (!cadence_qspi_wait_idle()) + return -EIO; + + return 0; +} + +/* For command RDID, RDSR. */ +static int cadence_qspi_apb_command_read(unsigned int cmdlen, const u8 *cmdbuf, + unsigned int rxlen, u8 *rxbuf) +{ + unsigned int reg; + unsigned int read_len; + int status; + + if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d " + "rxlen %d\n", cmdlen, rxlen); + return -EINVAL; + } + + reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + + /* 0 means 1 byte. */ + reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + status = cadence_qspi_apb_exec_flash_cmd(reg); + if (status != 0) + return status; + + reg = readl(&cadence_qspi_base->flashcmdrddatalo); + + /* Put the read value into rx_buf */ + read_len = (rxlen > 4) ? 4 : rxlen; + memcpy(rxbuf, &reg, read_len); + rxbuf += read_len; + + if (rxlen > 4) { + reg = readl(&cadence_qspi_base->flashcmdrddataup); + + read_len = rxlen - read_len; + memcpy(rxbuf, &reg, read_len); + } + return 0; +} + +/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ +static int cadence_qspi_apb_command_write(unsigned int cmdlen, + const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int addr_value; + unsigned int wr_data; + unsigned int wr_len; + + if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n", + cmdlen, txlen); + return -EINVAL; + } + + reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + if (cmdlen == 4 || cmdlen == 5) { + /* Command with address */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + /* Number of bytes to write. */ + reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], + cmdlen >= 5 ? 4 : 3); + + writel(addr_value, &cadence_qspi_base->flashcmdaddr); + } + + if (txlen) { + /* writing data = yes */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); + reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) + << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; + + wr_len = txlen > 4 ? 4 : txlen; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, &cadence_qspi_base->flashcmdwrdatalo); + + if (txlen > 4) { + txbuf += wr_len; + wr_len = txlen - wr_len; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, &cadence_qspi_base->flashcmdwrdataup); + } + } + + /* Execute the command */ + return cadence_qspi_apb_exec_flash_cmd(reg); +} + +/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ +static int cadence_qspi_apb_indirect_read_setup(unsigned int ahb_phy_addr, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int rd_reg; + unsigned int addr_value; + unsigned int dummy_clk; + unsigned int dummy_bytes; + unsigned int addr_bytes; + + /* + * Identify addr_byte. All NOR flash device drivers are using fast read + * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte. + * With that, the length is in value of 5 or 6. Only FRAM chip from + * ramtron using normal read (which won't need dummy byte). + * Unlikely NOR flash using normal read due to performance issue. + */ + if (cmdlen >= 5) + /* to cater fast read where cmd + addr + dummy */ + addr_bytes = cmdlen - 2; + else + /* for normal read (only ramtron as of now) */ + addr_bytes = cmdlen - 1; + + /* Setup the indirect trigger address */ + writel((ahb_phy_addr & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + &cadence_qspi_base->indaddrtrig); + + /* Configure SRAM partition for read. */ + writel(CQSPI_REG_SRAM_PARTITION_RD, &cadence_qspi_base->srampart); + + /* Configure the opcode */ + rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; + +#if (CONFIG_SPI_FLASH_QUAD == 1) + /* Instruction and address at DQ0, data at DQ0-3. */ + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; +#endif + + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(addr_value, &cadence_qspi_base->indrdstaddr); + + /* The remaining lenght is dummy bytes. */ + dummy_bytes = cmdlen - addr_bytes - 1; + if (dummy_bytes) { + + if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX) + dummy_bytes = CQSPI_DUMMY_BYTES_MAX; + + rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); +#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) + writel(0x0, &cadence_qspi_base->modebit); +#else + writel(0xFF, &cadence_qspi_base->modebit); +#endif + + /* Convert to clock cycles. */ + dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE; + /* Need to minus the mode byte (8 clocks). */ + dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE; + + if (dummy_clk) + rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) + << CQSPI_REG_RD_INSTR_DUMMY_LSB; + } + + writel(rd_reg, &cadence_qspi_base->devrd); + + /* set device size */ + reg = readl(&cadence_qspi_base->devsz); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, &cadence_qspi_base->devsz); + return 0; +} + +static int cadence_qspi_apb_indirect_read_execute(void *ahb_base_addr, + unsigned int rxlen, u8 *rxbuf) +{ + unsigned int reg; + + writel(rxlen, &cadence_qspi_base->indrdcnt); + + /* Start the indirect read transfer */ + writel(CQSPI_REG_INDIRECTRD_START_MASK, + &cadence_qspi_base->indrd); + + if (qspi_read_sram_fifo_poll((void *)rxbuf, + (const void *)ahb_base_addr, rxlen)) { + goto failrd; + } + + /* Check flash indirect controller */ + reg = readl(&cadence_qspi_base->indrd); + if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) { + reg = readl(&cadence_qspi_base->indrd); + printf("QSPI: indirect completion status " + "error with reg 0x%08x\n", reg); + goto failrd; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTRD_DONE_MASK, &cadence_qspi_base->indrd); + return 0; + +failrd: + /* Cancel the indirect read */ + writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, &cadence_qspi_base->indrd); + return -1; +} + +/* Opcode + Address (3/4 bytes) */ +static int cadence_qspi_apb_indirect_write_setup(unsigned int ahb_phy_addr, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int addr_bytes = cmdlen > 4 ? 4 : 3; + + if (cmdlen < 4 || cmdbuf == NULL) { + printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n", + cmdlen, (unsigned int)cmdbuf); + return -EINVAL; + } + /* Setup the indirect trigger address */ + writel((ahb_phy_addr & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + &cadence_qspi_base->indaddrtrig); + + writel(CQSPI_REG_SRAM_PARTITION_WR, + &cadence_qspi_base->srampart); + + /* Configure the opcode */ + reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; + writel(reg, &cadence_qspi_base->devwr); + + /* Setup write address. */ + reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(reg, &cadence_qspi_base->indwrstaddr); + + reg = readl(&cadence_qspi_base->devsz); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, &cadence_qspi_base->devsz); + return 0; +} + +static int cadence_qspi_apb_indirect_write_execute(void *ahb_base_addr, + unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int retry; + + /* Configure the indirect read transfer bytes */ + writel(txlen, &cadence_qspi_base->indwrcnt); + + /* Start the indirect write transfer */ + writel(CQSPI_REG_INDIRECTWR_START_MASK, &cadence_qspi_base->indwr); + + if (qpsi_write_sram_fifo_push(ahb_base_addr, + (const void *)txbuf, txlen)) { + goto failwr; + } + + /* Wait until last write is completed (FIFO empty) */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = CQSPI_GET_WR_SRAM_LEVEL(); + if (reg == 0) + break; + + udelay(1); + } + if (reg != 0) { + printf("QSPI: timeout for indirect write\n"); + goto failwr; + } + + /* Check flash indirect controller status */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = readl(&cadence_qspi_base->indwr); + if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK) + break; + udelay(1); + } + if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) { + printf("QSPI: indirect completion " + "status error with reg 0x%08x\n", reg); + goto failwr; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTWR_DONE_MASK, &cadence_qspi_base->indwr); + return 0; + +failwr: + /* Cancel the indirect write */ + writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, &cadence_qspi_base->indwr); + return -1; +} + +static void cadence_qspi_apb_enter_xip(char xip_dummy) +{ + unsigned int reg; + + /* enter XiP mode immediately and enable direct mode */ + reg = readl(&cadence_qspi_base->cfg); + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + reg |= CQSPI_REG_CONFIG_DIRECT_MASK; + reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK; + writel(reg, &cadence_qspi_base->cfg); + + /* keep the XiP mode */ + writel(xip_dummy, &cadence_qspi_base->modebit); + + /* Enable mode bit at devrd */ + reg = readl(&cadence_qspi_base->devrd); + reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); + writel(reg, &cadence_qspi_base->devrd); +} + +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + cadence_qspi_apb_config_baudrate_div(CONFIG_CQSPI_REF_CLK, hz); + + /* Reconfigure delay timing if speed is changed. */ + cadence_qspi_apb_delay(CONFIG_CQSPI_REF_CLK, hz, + CONFIG_CQSPI_TSHSL_NS, CONFIG_CQSPI_TSD2D_NS, + CONFIG_CQSPI_TCHSH_NS, CONFIG_CQSPI_TSLCH_NS); + return; +} + +/* calibration sequence to determine the read data capture delay register */ +int spi_calibration(struct spi_slave *slave) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + u8 opcode_rdid = 0x9F; + unsigned int idcode = 0, temp = 0; + int err = 0, i, range_lo = -1, range_hi = -1; + + /* start with slowest clock (1 MHz) */ + spi_set_speed(slave, 1000000); + + /* configure the read data capture delay register to 0 */ + cadence_qspi_apb_readdata_capture(1, 0); + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(); + + /* read the ID which will be our golden value */ + err = cadence_qspi_apb_command_read(1, &opcode_rdid, + 3, (u8 *)&idcode); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* use back the intended clock and find low range */ + spi_set_speed(slave, cadence_qspi->max_hz); + for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(); + + /* reconfigure the read data capture delay register */ + cadence_qspi_apb_readdata_capture(1, i); + + /* Enable back QSPI */ + cadence_qspi_apb_controller_enable(); + + /* issue a RDID to get the ID value */ + err = cadence_qspi_apb_command_read(1, &opcode_rdid, + 3, (u8 *)&temp); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* search for range lo */ + if (range_lo == -1 && temp == idcode) { + range_lo = i; + continue; + } + + /* search for range hi */ + if (range_lo != -1 && temp != idcode) { + range_hi = i - 1; + break; + } + range_hi = i; + } + + if (range_lo == -1) { + puts("SF: Calibration failed (low range)\n"); + return err; + } + + /* Disable QSPI for subsequent initialization */ + cadence_qspi_apb_controller_disable(); + + /* configure the final value for read data capture delay register */ + cadence_qspi_apb_readdata_capture(1, (range_hi + range_lo) / 2); + printf("SF: Read data capture delay calibrated to %i (%i - %i)\n", + (range_hi + range_lo) / 2, range_lo, range_hi); + + /* just to ensure we do once only when speed or chip select change */ + qspi_calibrated_hz = cadence_qspi->max_hz; + qspi_calibrated_cs = slave->cs; + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ +#if (CONFIG_CQSPI_DECODER == 1) + if (((cs >= 0) && (cs < CQSPI_DECODER_MAX_CS)) && ((bus >= 0) && + (bus < CQSPI_DECODER_MAX_CS))) { + return 1; + } +#else + if (((cs >= 0) && (cs < CQSPI_NO_DECODER_MAX_CS)) && + ((bus >= 0) && (bus < CQSPI_NO_DECODER_MAX_CS))) { + return 1; + } +#endif + printf("QSPI: Invalid bus or cs. Bus %d cs %d\n", bus, cs); + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + return; +} + +void spi_init(void) +{ + cadence_qspi_apb_controller_init(); + qspi_is_init = 1; + return; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct cadence_qspi_slave *cadence_qspi; + + debug("%s: bus %d cs %d max_hz %dMHz mode %d\n", __func__, + bus, cs, max_hz/1000000, mode); + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + cadence_qspi = malloc(sizeof(struct cadence_qspi_slave)); + if (!cadence_qspi) { + printf("QSPI: Can't allocate struct cadence_qspi_slave. " + "Bus %d cs %d\n", bus, cs); + return NULL; + } + + cadence_qspi->slave.bus = bus; + cadence_qspi->slave.cs = cs; + cadence_qspi->mode = mode; + cadence_qspi->max_hz = max_hz; + cadence_qspi->regbase = (void *)QSPI_BASE; + cadence_qspi->ahbbase = (void *)QSPI_AHB_BASE; + + if (!qspi_is_init) + spi_init(); + + return &cadence_qspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + free(cadence_qspi); + return; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + unsigned int clk_pol = (cadence_qspi->mode & SPI_CPOL) ? 1 : 0; + unsigned int clk_pha = (cadence_qspi->mode & SPI_CPHA) ? 1 : 0; + int err = 0; + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(); + + /* Set Chip select */ + cadence_qspi_apb_chipselect(slave->cs, CONFIG_CQSPI_DECODER); + + /* Set SPI mode */ + cadence_qspi_apb_set_clk_mode(clk_pol, clk_pha); + + /* Set clock speed */ + spi_set_speed(slave, cadence_qspi->max_hz); + + /* calibration required for different SCLK speed or chip select */ + if (qspi_calibrated_hz != cadence_qspi->max_hz || + qspi_calibrated_cs != slave->cs) { + err = spi_calibration(slave); + if (err) + return err; + } + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + return; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, + void *data_in, unsigned long flags) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + void *ahbbase = cadence_qspi->ahbbase; + u8 *cmd_buf = cadence_qspi->cmd_buf; + size_t data_bytes; + int err = 0; + u32 mode = CQSPI_STIG_WRITE; + + if (flags & SPI_XFER_BEGIN) { + /* copy command to local buffer */ + cadence_qspi->cmd_len = bitlen / 8; + memcpy(cmd_buf, data_out, cadence_qspi->cmd_len); + } + + if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { + /* if start and end bit are set, the data bytes is 0. */ + data_bytes = 0; + } else { + data_bytes = bitlen / 8; + } + + if ((flags & SPI_XFER_END) || (flags == 0)) { + if (cadence_qspi->cmd_len == 0) { + printf("QSPI: Error, command is empty.\n"); + return -1; + } + + if (data_in && data_bytes) { + /* read */ + /* Use STIG if no address. */ + if (!CQSPI_IS_ADDR(cadence_qspi->cmd_len)) + mode = CQSPI_STIG_READ; + else + mode = CQSPI_INDIRECT_READ; + } else if (data_out && !(flags & SPI_XFER_BEGIN)) { + /* write */ + if (!CQSPI_IS_ADDR(cadence_qspi->cmd_len)) + mode = CQSPI_STIG_WRITE; + else + mode = CQSPI_INDIRECT_WRITE; + } + + switch (mode) { + case CQSPI_STIG_READ: + err = cadence_qspi_apb_command_read( + cadence_qspi->cmd_len, cmd_buf, + data_bytes, data_in); + + break; + case CQSPI_STIG_WRITE: + err = cadence_qspi_apb_command_write( + cadence_qspi->cmd_len, cmd_buf, + data_bytes, data_out); + break; + case CQSPI_INDIRECT_READ: + err = cadence_qspi_apb_indirect_read_setup( + QSPI_AHB_BASE, + cadence_qspi->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_read_execute + (ahbbase, data_bytes, data_in); + } + break; + case CQSPI_INDIRECT_WRITE: + err = cadence_qspi_apb_indirect_write_setup + (QSPI_AHB_BASE, + cadence_qspi->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_write_execute + (ahbbase, data_bytes, data_out); + } + break; + default: + err = -1; + break; + } + + if (flags & SPI_XFER_END) { + /* clear command buffer */ + memset(cmd_buf, 0, sizeof(cadence_qspi->cmd_buf)); + cadence_qspi->cmd_len = 0; + } + } + return err; +} + +void spi_enter_xip(struct spi_slave *slave, char xip_dummy) +{ + /* Enter XiP */ + cadence_qspi_apb_enter_xip(xip_dummy); + return; +} + + diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h new file mode 100644 index 0000000..1466735 --- /dev/null +++ b/drivers/spi/cadence_qspi.h @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CADENCE_QSPI_H__ +#define __CADENCE_QSPI_H__ + +#define QSPI_BASE (CONFIG_CQSPI_BASE) +#define QSPI_AHB_BASE (CONFIG_CQSPI_AHB_BASE) +#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) + +struct cadence_qspi_slave { + struct spi_slave slave; + unsigned int mode; + unsigned int max_hz; + void *regbase; + void *ahbbase; + size_t cmd_len; + u8 cmd_buf[32]; + size_t data_len; +}; + +struct cadence_qspi { + u32 cfg; + u32 devrd; + u32 devwr; + u32 delay; + u32 rddatacap; + u32 devsz; + u32 srampart; + u32 indaddrtrig; + u32 dmaper; + u32 remapaddr; + u32 modebit; + u32 sramfill; + u32 txthresh; + u32 rxthresh; + u32 _pad_0x38_0x3f[2]; + u32 irqstat; + u32 irqmask; + u32 _pad_0x48_0x4f[2]; + u32 lowwrprot; + u32 uppwrprot; + u32 wrprot; + u32 _pad_0x5c_0x5f; + u32 indrd; + u32 indrdwater; + u32 indrdstaddr; + u32 indrdcnt; + u32 indwr; + u32 indwrwater; + u32 indwrstaddr; + u32 indwrcnt; + u32 _pad_0x80_0x8f[4]; + u32 flashcmd; + u32 flashcmdaddr; + u32 _pad_0x98_0x9f[2]; + u32 flashcmdrddatalo; + u32 flashcmdrddataup; + u32 flashcmdwrdatalo; + u32 flashcmdwrdataup; + u32 _pad_0xb0_0xfb[19]; + u32 moduleid; +}; + +/* Controller's configuration and status register */ +#define CQSPI_REG_CONFIG_CLK_POL_LSB 1 +#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 +#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0) +#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7) +#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9) +#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18) +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_IDLE_LSB 31 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_DELAY_TSLCH_LSB 0 +#define CQSPI_REG_DELAY_TCHSH_LSB 8 +#define CQSPI_REG_DELAY_TSD2D_LSB 16 +#define CQSPI_REG_DELAY_TSHSL_LSB 24 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF +#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS_LSB 0 +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF +#define CQSPI_REG_SIZE_ADDRESS_LSB 0 +#define CQSPI_REG_SIZE_PAGE_LSB 4 +#define CQSPI_REG_SIZE_BLOCK_LSB 16 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F +#define CQSPI_REG_SRAMLEVEL_RD_LSB 0 +#define CQSPI_REG_SRAMLEVEL_WR_LSB 16 +#define CQSPI_REG_SRAMLEVEL_RD_MASK 0xFFFF +#define CQSPI_REG_SRAMLEVEL_WR_MASK 0xFFFF +#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5) +#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0) +#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1) +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF +#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5) + +/* Transfer type */ +#define CQSPI_STIG_READ 0 +#define CQSPI_STIG_WRITE 1 +#define CQSPI_INDIRECT_READ 2 +#define CQSPI_INDIRECT_WRITE 3 + +/* Transfer mode */ +#define CQSPI_INST_TYPE_SINGLE (0) +#define CQSPI_INST_TYPE_DUAL (1) +#define CQSPI_INST_TYPE_QUAD (2) + +/* controller operation setting */ +#define CQSPI_NO_DECODER_MAX_CS (4) +#define CQSPI_DECODER_MAX_CS (16) +#define CQSPI_READ_CAPTURE_MAX_DELAY (16) +#define CQSPI_REG_POLL_US (1) +#define CQSPI_REG_RETRY (10000) +#define CQSPI_POLL_IDLE_RETRY (3) +#define CQSPI_FIFO_WIDTH (4) +#define CQSPI_STIG_DATA_LEN_MAX (8) +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) +#define CQSPI_DUMMY_CLKS_PER_BYTE (8) +#define CQSPI_DUMMY_BYTES_MAX (4) + +/* Controller sram size in word */ +#define CQSPI_REG_SRAM_SIZE_WORD (128) +#define CQSPI_REG_SRAM_RESV_WORDS (2) +#define CQSPI_REG_SRAM_PARTITION_WR (1) +#define CQSPI_REG_SRAM_PARTITION_RD \ + (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) +#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) +#define CQSPI_REG_SRAM_FILL_THRESHOLD \ + ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) + +#endif /* __CADENCE_QSPI_H__ */ -- 1.7.9.5

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[U-Boot] [PATCH 0/2 v2] socfpga: Adding Scan Manager
by Chin Liang See 09 Jan '14

09 Jan '14

Adding Scan Manager driver and handoff files. Scan Manager driver will be called to configure the IO buffer setting. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- Changes for v2 - Rebase with latest v2014.01-rc1 Chin Liang See (2): socfpga: Adding Scan Manager driver socfpga: Adding Scan Manager IOCSR handoff files arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 +++++++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + board/altera/socfpga/iocsr_config.c | 653 ++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 12 + include/configs/socfpga_cyclone5.h | 1 + 8 files changed, 1000 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h create mode 100644 board/altera/socfpga/iocsr_config.c create mode 100644 board/altera/socfpga/iocsr_config.h -- 1.7.9.5

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