June 2013 - U-Boot

[U-Boot] [PATCH] pxa: turn icache off in cpu_init_crit()
by Mike Dunn 17 Jun '13

17 Jun '13

The comment in the low-level initialization function cpu_init_crit() says that the caches are being disabled, but (oddly) the icache is actually turned on. This is probably not a good idea prior to relocating code, so this patch turns it off. Tested on the pxa270. Signed-off-by: Mike Dunn <mikedunn(a)newsguy.com> --- Because the current code seems quite deliberate in setting the icache bit, I looked for evidence of an errata on the pxa25x whereby the logic of this bit is inverted, but couldn't find any. arch/arm/cpu/pxa/start.S | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 2e3f65e..b1deb72 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -208,10 +208,9 @@ cpu_init_crit: * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -- 1.7.8.6

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[U-Boot] [PATCH] mpc83xx: add support for mpc8306
by Filip Brozovic 17 Jun '13

17 Jun '13

This processor is most similar to the MPC8309, but lacks PCI. Signed-off-by: Filip Brozovic <fbrozovic(a)gmail.com> --- arch/powerpc/cpu/mpc83xx/cpu.c | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 4 +++ arch/powerpc/cpu/mpc83xx/speed.c | 24 ++++++++++------ arch/powerpc/include/asm/global_data.h | 2 +- arch/powerpc/include/asm/immap_83xx.h | 52 ++++++++++++++++++++++++++++++++-- arch/powerpc/include/asm/immap_qe.h | 2 +- drivers/qe/qe.c | 4 +-- include/mpc83xx.h | 9 +++--- 8 files changed, 80 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index cc20234..13fd502 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -55,6 +55,7 @@ int checkcpu(void) char name[15]; u32 partid; } cpu_type_list [] = { + CPU_TYPE_ENTRY(8306), CPU_TYPE_ENTRY(8308), CPU_TYPE_ENTRY(8309), CPU_TYPE_ENTRY(8311), diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 5153351..8beefc1 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -334,7 +334,11 @@ void cpu_init_f (volatile immap_t * im) struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; /* Configure interface. */ +#ifdef CONFIG_MPC8306 + setbits_be32(&ehci->control, REFSEL_16MHZ | PHY_CLK_SEL_ULPI); +#else setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); +#endif /* Wait for clock to stabilize */ do { diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 6be0e3a..7c2a3bd 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -105,7 +105,7 @@ int get_clocks(void) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u32 usbdr_clk; #endif #ifdef CONFIG_MPC834x @@ -122,7 +122,7 @@ int get_clocks(void) #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) u32 enc_clk; #endif u32 lbiu_clk; @@ -166,7 +166,11 @@ int get_clocks(void) } spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; +#if defined(CONFIG_MPC8306) + csb_clk = CONFIG_83XX_CLKIN * spmf; +#else csb_clk = pci_sync_in * (1 + clkin_div) * spmf; +#endif sccr = im->clk.sccr; @@ -267,7 +271,7 @@ int get_clocks(void) return -6; } #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: enc_clk = 0; @@ -338,7 +342,7 @@ int get_clocks(void) i2c1_clk = sdhc_clk; #elif defined(CONFIG_MPC837x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) i2c1_clk = csb_clk; #endif #if !defined(CONFIG_MPC832x) @@ -458,7 +462,11 @@ int get_clocks(void) #if defined(CONFIG_QE) qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT; qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT; +#if defined(CONFIG_MPC8306) + qe_clk = (CONFIG_83XX_QE_CLKIN * qepmf) / (1 + qepdf); +#else qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); +#endif brg_clk = qe_clk / 2; #endif @@ -468,7 +476,7 @@ int get_clocks(void) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) gd->arch.usbdr_clk = usbdr_clk; #endif #if defined(CONFIG_MPC834x) @@ -485,7 +493,7 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) gd->arch.i2c2_clk = i2c2_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) gd->arch.enc_clk = enc_clk; #endif gd->arch.lbiu_clk = lbiu_clk; @@ -555,7 +563,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) printf(" SEC: %-4s MHz\n", strmhz(buf, gd->arch.enc_clk)); #endif @@ -581,7 +589,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index c02447f..f5341eb 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -51,7 +51,7 @@ struct arch_global_data { u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -# elif defined(CONFIG_MPC8309) +# elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u32 usbdr_clk; # endif # if defined(CONFIG_MPC834x) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 8ac13fc..127352a 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -78,7 +78,7 @@ typedef struct sysconf83xx { #else u32 pecr2; /* PCI Express control register 2 */ #endif -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u32 can_dbg_ctrl; u32 res9a; u32 gpr1; @@ -715,7 +715,7 @@ typedef struct serdes83xx { * On Chip ROM */ typedef struct rom83xx { -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u8 mem[0x8000]; #else u8 mem[0x10000]; @@ -983,6 +983,54 @@ typedef struct immap { u8 res8[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; +#elif defined(CONFIG_MPC8306) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[2]; /* General purpose I/O module */ + u8 res0[0x500]; + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + qepio83xx_t qepio; /* QE Parallel I/O ports */ + u8 res1[0x800]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x200]; + duart83xx_t duart1[2]; /* DUART */ + u8 res4[0x500]; + fsl_lbc_t im_lbc; /* Local Bus Controller Registers */ + u8 res5[0x1000]; + u8 spi[0x100]; + u8 res6[0xf00]; + dma83xx_t dma; /* DMA */ + u8 res7[0x100]; + ios83xx_t ios; /* Sequencer (IOS) */ + u8 res8[0x13B00]; + u8 can1[0x1000]; /* Flexcan 1 */ + u8 can2[0x1000]; /* Flexcan 2 */ + u8 res9[0x5000]; + usb83xx_t usb; + u8 res10[0x5000]; + u8 can3[0x1000]; /* Flexcan 3 */ + u8 can4[0x1000]; /* Flexcan 4 */ + u8 res11[0x1000]; + u8 dma1[0x2000]; /* DMA */ + sdhc83xx_t sdhc; /* SDHC Controller */ + u8 res12[0xC1000]; + rom83xx_t rom; /* On Chip ROM */ + u8 res13[0x8000]; + u8 qe[0x100000]; /* QE block */ + u8 res14[0xE00000]; +} immap_t; #elif defined(CONFIG_MPC8309) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index f0b989a..b42fe62 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -20,7 +20,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 5fd2135..2cd0949 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -114,8 +114,8 @@ static void qe_sdma_init(void) * we just need to know what the SNUMs are for the threads. */ static u8 thread_snum[] = { -/* Evthreads 16-29 are not supported in MPC8309 */ -#if !defined(CONFIG_MPC8309) +/* Evthreads 16-29 are not supported in MPC8306 and MPC8309 */ +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, diff --git a/include/mpc83xx.h b/include/mpc83xx.h index b295d6d..5744b95 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -73,6 +73,7 @@ #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) +#define SPR_8306 0x8110 #define SPR_8308 0x8100 #define SPR_8309 0x8110 #define SPR_831X_FAMILY 0x80B @@ -215,7 +216,7 @@ #define SICRH_UC2E1OBI 0x00000002 #define SICRH_UC2E2OBI 0x00000001 -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8306) /* SICRL bits - MPC832x specific */ #define SICRL_LDP_LCS_A 0x80000000 #define SICRL_IRQ_CKS 0x20000000 @@ -600,7 +601,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) || defined(CONFIG_MPC8306) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -646,7 +647,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -993,7 +994,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || defined(CONFIG_MPC8306) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 -- 1.8.1.2

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[U-Boot] [SPI-TEST]: Request for test u-boot-spi/master-work
by Jagan Teki 17 Jun '13

17 Jun '13

Hi All, In-fact this is a first time for sending test tagged mail. The reason for sending this is: We added many changes on spi_flash framework to support all sizes of flashes. I'd appreciate if anyone can test this master-work branch on u-boot-spi.git repo with your respective hw's $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b master-work origin/master-work Please let me know for any issues/concerns. Apologies, if anyone hurt this kind of mail. -- Thanks, Jagan.

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[U-Boot] [PATCH] checkpatch.pl: Do not hardcode perl path
by Jagannadha Sutradharudu Teki 17 Jun '13

17 Jun '13

From: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> checkpatch.pl requires perl v5.10.0 to run but it doesn't require to place in /usr/bin/perl Use env to ensure that the interpreter used is the first one on environment's $PATH on system with several versions of perl installed. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> --- tools/checkpatch.pl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl index 896e2bc..8dc5b9c 100755 --- a/tools/checkpatch.pl +++ b/tools/checkpatch.pl @@ -1,10 +1,11 @@ -#!/usr/bin/perl -w +#!/usr/bin/env perl # (c) 2001, Dave Jones. (the file handling bit) # (c) 2005, Joel Schopp <jschopp(a)austin.ibm.com> (the ugly bit) # (c) 2007,2008, Andy Whitcroft <apw(a)uk.ibm.com> (new conditions, test suite) # (c) 2008-2010 Andy Whitcroft <apw(a)canonical.com> # Licensed under the terms of the GNU GPL License version 2 +use warnings; use strict; my $P = $0; -- 1.8.3

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[U-Boot] [PATCH] image: Use ENOENT instead of ENOMEDIUM for better compatibility
by Simon Glass 17 Jun '13

17 Jun '13

This error may not be defined on some platforms such as MacOS so host compilation will fail. Use one of the more common errors instead. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- common/image-fit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/image-fit.c b/common/image-fit.c index 7bf82d3..f40f160 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1557,7 +1557,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr, if (fit_image_get_data(fit, noffset, &buf, &size)) { printf("Could not find %s subimage data!\n", prop_name); bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA); - return -ENOMEDIUM; + return -ENOENT; } len = (ulong)size; -- 1.8.3

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[U-Boot] [PATCH] ARM: mxs: Make the console buffer smaller
by Marek Vasut 17 Jun '13

17 Jun '13

Using 1024 bytes for console buffer is unnecessarily too much, lower the amount for all MXS boards to 256. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Lauri Hintsala <lauri.hintsala(a)bluegiga.com> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/mxs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Note: This depends on http://patchwork.ozlabs.org/patch/251631/ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index a684166..161d89d 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -92,7 +92,7 @@ #ifndef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "=> " #endif -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buffer size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ -- 1.7.10.4

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[U-Boot] [PATCH] spi: Use DIV_ROUND_UP at appropriate places
by Axel Lin 17 Jun '13

17 Jun '13

This change slightly improves readability. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/cf_qspi.c | 2 +- drivers/spi/mxc_spi.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c index a37ac4e..06bcf91 100644 --- a/drivers/spi/cf_qspi.c +++ b/drivers/spi/cf_qspi.c @@ -171,7 +171,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, volatile qspi_t *qspi = dev->regs; u8 *txbuf = (u8 *)dout; u8 *rxbuf = (u8 *)din; - u32 count = ((bitlen / 8) + (bitlen % 8 ? 1 : 0)); + u32 count = DIV_ROUND_UP(bitlen, 8); u32 n, i = 0; /* Sanitize arguments */ diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 5bed858..2ea3228 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -224,7 +224,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, const u8 *dout, u8 *din, unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); - int nbytes = (bitlen + 7) / 8; + int nbytes = DIV_ROUND_UP(bitlen, 8); u32 data, cnt, i; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; @@ -294,7 +294,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, /* Transfer completed, clear any pending request */ reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); - nbytes = (bitlen + 7) / 8; + nbytes = DIV_ROUND_UP(bitlen, 8); cnt = nbytes % 32; @@ -330,7 +330,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - int n_bytes = (bitlen + 7) / 8; + int n_bytes = DIV_ROUND_UP(bitlen, 8); int n_bits; int ret; u32 blk_size; -- 1.8.1.2

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[U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
by Sourav Poddar 17 Jun '13

17 Jun '13

Hi, I am working on qspi flash device S25FL256S at u-boot level. I am trying to make use of the existing spi_flash.c framework available at u-boot for erasing/reading/writing into the flash device. There are several issues(mentioned below), which I faced while using S25FL256s flash device with my dra7xx board which has a qspi controller to which the above mentioned flash device is attached. 1. Erase (spi_flash_cmd_erase) Issuing a command something like this.. sf erase 0x0 0x50000 - erases only first 0x20000 bytes of flash device, anything above that is not erase. I need to issue separate commands after 0x20000 for every 0x10000 bytes. Am i missing anything here? 2. read sf read 81000000 0 0x10000 Read is not happening properly. The last few byte along the 4k boundary always shows zero. Above 4k bytes, read is not happening. For ex: DRA752 EVM # md 81000f00 81000f00: ffffffff ffffffff ffffffff ffffffff ................ 81000f10: ffffffff ffffffff ffffffff ffffffff ................ 81000f20: ffffffff ffffffff ffffffff ffffffff ................ 81000f30: ffffffff ffffffff ffffffff ffffffff ................ 81000f40: ffffffff ffffffff ffffffff ffffffff ................ 81000f50: ffffffff ffffffff ffffffff ffffffff ................ 81000f60: ffffffff ffffffff ffffffff ffffffff ................ 81000f70: ffffffff ffffffff ffffffff ffffffff ................ 81000f80: ffffffff ffffffff ffffffff ffffffff ................ 81000f90: ffffffff ffffffff ffffffff ffffffff ................ 81000fa0: ffffffff ffffffff ffffffff ffffffff ................ 81000fb0: ffffffff ffffffff ffffffff ffffffff ................ 81000fc0: ffffffff ffffffff ffffffff ffffffff ................ 81000fd0: ffffffff ffffffff ffffffff ffffffff ................ 81000fe0: ffffffff ffffffff ffffffff ffffffff ................ 81000ff0: ffffffff ffffffff 00ffffff 00000000 ................ In this dump, if you see 81000ff0 the last column shows 000000 which is not expected. and it happens along every 4k bytes. So, to get rid of the above issue, I switched to page read with the below patch[1], which is giving me the correct result. [1]: @@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, size_t len, void *data) { - u8 cmd[5]; + unsigned long page_addr, byte_addr, page_size; + size_t chunk_len, actual; + int ret = 0; + u8 cmd[4]; /* Handle memory-mapped SPI */ if (flash->memory_map) memcpy(data, flash->memory_map + offset, len); + page_size = flash->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = CMD_READ_ARRAY_SLOW; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + ret = spi_flash_read_common(flash, cmd, sizeof(cmd), data + actual, chunk_len); + if (ret < 0) { + debug("SF: read failed"); + break; + } - cmd[0] = CMD_READ_ARRAY_FAST; - spi_flash_addr(offset, cmd); - cmd[4] = 0x00; + byte_addr += chunk_len; + if (byte_addr == page_size) { + page_addr++; + byte_addr = 0; + } + } - return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len); + return ret; } Any idea about this? 3. write (spi_flash_cmd_write_multi) write not happening properly. observations: only able to write single page, anything after a page is not getting written. Workaround: I did a write disable latch at the end of every write cycle(page program) and enable it again for the next loop. With this, I see I get rid of the above issue. @@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, if (ret) break; + ret = spi_flash_cmd_write_disable(flash); + if (ret < 0) { + printf("SF: disabling write failed\n"); + break; + } + Have anyone seen the above mentioned issues regarding read/write/erase? OR is there any configurations that I might be missing ?

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[U-Boot] TFTP timeouts, i.mx fec problem?
by Ruud Commandeur 17 Jun '13

17 Jun '13

Hi everyone, I have been testing for a while now on the i.mx28 evk, and I noticed that almost all tftp transfers take some time before they actually start. It will show a 'T' as first character, then followed by '#' chars. After enabling some debug info, it appeared that it would always start by sending an ARP request, but this ARP message does not get sent actually (monitored with Wireshark). After 5 seconds the 2nd ARP request is sent (this does get traced by Wireshark) and also responded and from that point all goes well. When tracing the code, it could see that fec_send is called for the 1st ARP request and also the return value indicates that sending should have been succeeded (fec_send: status 0xc00 index 0 ret 0). But no package is actually sent. My first guess would be that it has something to do with the TBD / DMA part. The fec_tbd_init also shows some note about a rare hardware condition regarding the WRAP bit (all in drivers/net/fec_mxc.c). Could it be that there is still another issue regarding the chip that causes this? If I do a tftp transfer from linux on the same board and in the same network, it does start immediately. =======================DEBUG LOG=========================== U-Boot > tftp versions.ini eth_halt: wait for stop regs eth_halt: done Trying FEC0 fec_init fec_tbd_init fec_mii_setspeed: mii_speed 0000003c fec_open: fec_open(dev) fec_open:Speed=100 TFTP blocksize = 1468, timeout = 5000 ms TFTP from server 192.168.0.100; our IP address is 192.168.0.109 Filename 'versions.ini'. Loading: send option "timeout 5" sending ARP for 192.168.0.100 ARP broadcast 1 fec_send: status 0xc00 index 0 ret 0 T send option "timeout 5" sending ARP for 192.168.0.100 ARP broadcast 1 fec_send: status 0x2c00 index 1 ret 0 Got ARP REPLY, set eth addr (00:0c:29:65:b4:8a) fec_send: status 0xc00 index 0 ret 0 received UDP (to=192.168.0.109, from=192.168.0.100, len=53) Got OACK: timeout 5 Blocksize ack: 1468, 1468 sending UDP to 192.168.0.100/00:0c:29:65:b4:8a fec_send: status 0x2c00 index 1 ret 0 received UDP (to=192.168.0.109, from=192.168.0.100, len=100) #sending UDP to 192.168.0.100/00:0c:29:65:b4:8a fec_send: status 0xc00 index 0 ret 0 0 Bytes/s done Bytes transferred = 68 (44 hex) eth_halt: wait for stop regs eth_halt: done U-Boot > ========================================================== Thanks in advance for any comments. Regards, Ruud

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[U-Boot] Porting U-boot-2013-04 to sdk for mips board
by krishna dwivedi 17 Jun '13

17 Jun '13

Hi, I am trying to port the u-boot2013:04 to sdk.During compilation,I am running into error:*Undefined reference to _GLOBAL_OFFSET_TABLE*.I checked in u-boot.lds file thr is no definition of _GLOBAL_OFFSET_TABLE.I have added this piece of code in u-boot.lds: .reloc : { KEEP(*(.got)) PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); } In addition,i see reference of GLOBAL_OFFSET_TABLE.But it is not defined in any file and even linker script. Can anyone please confirm,if this is common issue in u-boot version 2013:04. Regards, krishna

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