November 2013 - U-Boot

[U-Boot] [PATCH v15 00/10] arm64 patch
by fenghua＠phytium.com.cn 15 Jan '14

15 Jan '14

From: David Feng <fenghua(a)phytium.com.cn> Changes for v15: - modify boot process, u-boot will run at the highest exception level until it prepare jump to OS. - Fix a few bugs in cache.S.These bug is reported by York Sun <yorksun(a)freescale.com> and Scott Wood <scottwood(a)freescale.com>. - when booting, slaves will wait on WFI, master wakeup slaves by SGI interrupt. - add generic_timer.c to utilize the newest timer architecture. - add gic.S to support gic initialization and interrupt operations, currently only support GICv2. Changes for v14: - Merge rela relocation patches from Scott Wood <scottwood(a)freescale.com>. - Remove all CONFIG_NEED_MANUAL_RELOC and other fixups due to manual relocation. With rela relocation patches them are not needed. - Fix the bug of MEMORY_ATTRIBUTES definition due to assembler. That need put brackets around (MT_NORMAL*8). Otherwise the result is wrong.This bug is reported by York Sun <yorksun(a)freescale.com>. - -msoft-float is not supported by aarch64-gcc, make a test though $(call cc-option,-msoft-float). - Adjust the virtual address space to 42 bits. - Filter armv8 boards from LIST_arm in MAKEALL. - remove gpio.h in asm/arch-armv8/ and move mmu.h to asm/armv8/ directory. - remove vexpress64.dts from this patch, it could be accessed from linux kernel. Changes for v13: - fix the bug of board_r.c and arm/lib/board.c due to CONFIG_NEED_MANUAL_RELOC. adjust initr_serial() in board_r.c to the first entry of init_sequence_r[] and relocate serial_initialize() in arm/lib/board.c, routines of serial_device should be relocated firstly by serial_initialize(), so that printf access the correct puts function, otherwise uninitialized serial_current will be selected as the output device. - fix the bug of dcache_enable(). after mmu_setup the sctrl register value should be fetched again because it has been modifed by mmu_seup() function. This bug is reported by York Sun <yorksun(a)freescale.com>. - add macro branch_if_slave to macro.h, it choose processor with all zero affinity value as the master and is used in start.S. Changes for v12: - custom the patches to new format boards.cfg. Changes for v11: - Replace CONFIG_ARMV8 with CONFIG_ARM64. Currently, it's hard to distinguish what is armv8 specific and what is aarch64 specific, so we use CONFIG_ARM64 only, no CONFIG_ARMV8 used. - rename README.armv8 with README.arm64 and make some modification. Changes for v10: - add weak definition to include/linux/linkage.h and make setup_el2/setup_el3/lowlevel_init weak routines, so them can be easily overridden by processor specific code. - modify s-o-f of 0002-board-support-of-vexpress_aemv8a which use wrong mail address of Bhupesh Sharma. Changes for v9: - add Signed-off-by information to patch "board support of vexpress_aemv8a" which SMC91111 support is integrated from Sharma Bhupesh's patch. - adjust pt_regs struct and add exception state preservation in exception.S. Changes for v8: - Integrate SMC91111 patch of sharma bhupesh. - remove v8_outer_cache* which is not need currently. - Change license tag. - Mov crt0.S/relocate.S/interrupts.c to arm/lib and rename them with _64 suffix. - Make el3/el2 initializing process of start.S as two separate routines. It could be easier to be replaced with processor specific codes. - Remove exception stack save and restore routine, it is unnecessary now. - simplify __weak function declaration. Changes for v7: - Check the patches with checkpatch.pl and get rid of almost all warnings. There are a few warnings still, but I think it should be that. - change printf format in cmd_pxe.c, use %zd indtead of %ld to format size_t type variable. - add macro PGTABLE_SIZE to identify tlb table size. Changes for v6: - Make modification to inappropriate licensed file and bugs according to ScottWood's advice. Thanks Scott for his checking to these patches. - Enable u-boot's running at EL1. - Get rid of compiling warnings originated from cmd_pxe.c. Changes for v5: - fix the generic board_f.c, remove zero_global_data from init_sequence_f array and move it to board_init_f() function with CONFIG_X86 switch. The previous fixup is inaccurate. - Replace __ARMEB__ with __AARCH64EB__ in byteorder.h and unaligned.h, gcc for aarch64 use __AARCH64EB__ and __AARCH64EL__ to identify endian. - Some modification to README.armv8 Changes for v4: - merge arm64 to arm architecture. David Feng (10): fdt_support: 64bit initrd start address support cmd_pxe: remove compiling warnings add weak entry definition arm64: Add tool to statically apply RELA relocations arm64: Turn u-boot.bin back into an ELF file after relocate-rela arm64: Make checkarmreloc accept arm64 relocations arm64: core support arm64: generic board support arm64: board support of vexpress_aemv8a arm64: MAKEALL, filter armv8 boards from LIST_arm MAKEALL | 12 +- Makefile | 39 +++++- arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/Makefile | 17 +++ arch/arm/cpu/armv8/cache.S | 136 +++++++++++++++++++ arch/arm/cpu/armv8/cache_v8.c | 219 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/config.mk | 15 +++ arch/arm/cpu/armv8/cpu.c | 43 ++++++ arch/arm/cpu/armv8/exceptions.S | 113 ++++++++++++++++ arch/arm/cpu/armv8/generic_timer.c | 31 +++++ arch/arm/cpu/armv8/gic.S | 106 +++++++++++++++ arch/arm/cpu/armv8/start.S | 164 +++++++++++++++++++++++ arch/arm/cpu/armv8/tlb.S | 34 +++++ arch/arm/cpu/armv8/transition.S | 83 ++++++++++++ arch/arm/cpu/armv8/u-boot.lds | 89 +++++++++++++ arch/arm/include/asm/armv8/mmu.h | 111 ++++++++++++++++ arch/arm/include/asm/byteorder.h | 12 ++ arch/arm/include/asm/cache.h | 5 + arch/arm/include/asm/config.h | 6 + arch/arm/include/asm/gic.h | 49 ++++++- arch/arm/include/asm/global_data.h | 6 +- arch/arm/include/asm/io.h | 15 ++- arch/arm/include/asm/macro.h | 53 ++++++++ arch/arm/include/asm/posix_types.h | 10 ++ arch/arm/include/asm/proc-armv/ptrace.h | 21 +++ arch/arm/include/asm/proc-armv/system.h | 59 ++++++++- arch/arm/include/asm/system.h | 84 ++++++++++++ arch/arm/include/asm/types.h | 4 + arch/arm/include/asm/u-boot.h | 4 + arch/arm/include/asm/unaligned.h | 2 +- arch/arm/lib/Makefile | 20 ++- arch/arm/lib/board.c | 7 +- arch/arm/lib/bootm.c | 24 ++++ arch/arm/lib/crt0_64.S | 113 ++++++++++++++++ arch/arm/lib/interrupts_64.c | 120 +++++++++++++++++ arch/arm/lib/relocate_64.S | 58 ++++++++ board/armltd/vexpress64/Makefile | 8 ++ board/armltd/vexpress64/vexpress64.c | 56 ++++++++ boards.cfg | 1 + common/board_f.c | 20 ++- common/cmd_pxe.c | 4 +- common/fdt_support.c | 66 +++++----- common/image.c | 1 + doc/README.arm64 | 46 +++++++ examples/standalone/stubs.c | 15 +++ include/configs/vexpress_aemv8a.h | 189 ++++++++++++++++++++++++++ include/image.h | 1 + include/linux/linkage.h | 4 + tools/Makefile | 6 + tools/relocate-rela.c | 189 ++++++++++++++++++++++++++ 50 files changed, 2425 insertions(+), 68 deletions(-) create mode 100644 arch/arm/cpu/armv8/Makefile create mode 100644 arch/arm/cpu/armv8/cache.S create mode 100644 arch/arm/cpu/armv8/cache_v8.c create mode 100644 arch/arm/cpu/armv8/config.mk create mode 100644 arch/arm/cpu/armv8/cpu.c create mode 100644 arch/arm/cpu/armv8/exceptions.S create mode 100644 arch/arm/cpu/armv8/generic_timer.c create mode 100644 arch/arm/cpu/armv8/gic.S create mode 100644 arch/arm/cpu/armv8/start.S create mode 100644 arch/arm/cpu/armv8/tlb.S create mode 100644 arch/arm/cpu/armv8/transition.S create mode 100644 arch/arm/cpu/armv8/u-boot.lds create mode 100644 arch/arm/include/asm/armv8/mmu.h create mode 100644 arch/arm/lib/crt0_64.S create mode 100644 arch/arm/lib/interrupts_64.c create mode 100644 arch/arm/lib/relocate_64.S create mode 100644 board/armltd/vexpress64/Makefile create mode 100644 board/armltd/vexpress64/vexpress64.c create mode 100644 doc/README.arm64 create mode 100644 include/configs/vexpress_aemv8a.h create mode 100644 tools/relocate-rela.c -- 1.7.9.5

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[U-Boot] [PATCH] ARM: merge commonly-defined PLATFORM_RELFLAGS
by Masahiro Yamada 15 Jan '14

15 Jan '14

All arch/arm/cpu/${CPU}/config.mk had the same PLATFORM_RELFLAGS definitions. This commit merges them into arch/arm/config.mk. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/arm/config.mk | 4 +++- arch/arm/cpu/arm1136/config.mk | 7 ------- arch/arm/cpu/arm1176/config.mk | 8 -------- arch/arm/cpu/arm720t/config.mk | 8 -------- arch/arm/cpu/arm920t/config.mk | 7 ------- arch/arm/cpu/arm926ejs/config.mk | 7 ------- arch/arm/cpu/arm946es/config.mk | 7 ------- arch/arm/cpu/arm_intcm/config.mk | 7 ------- arch/arm/cpu/armv7/config.mk | 8 -------- arch/arm/cpu/ixp/config.mk | 8 -------- arch/arm/cpu/pxa/config.mk | 7 ------- arch/arm/cpu/sa1100/config.mk | 7 ------- 12 files changed, 3 insertions(+), 82 deletions(-) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index bdabcf4..e2ff323 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -17,7 +17,9 @@ endif LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ - -fno-common -ffixed-r9 -msoft-float + -fno-common -ffixed-r9 -msoft-float \ + $(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) # Support generic board on ARM __HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index b4d396d..f74228c 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -7,13 +7,6 @@ # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk index f4631cb..5dc2ebb 100644 --- a/arch/arm/cpu/arm1176/config.mk +++ b/arch/arm/cpu/arm1176/config.mk @@ -7,11 +7,3 @@ # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk index 2581f0a..772fb41 100644 --- a/arch/arm/cpu/arm720t/config.mk +++ b/arch/arm/cpu/arm720t/config.mk @@ -7,11 +7,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk index 67537dc..799afff 100644 --- a/arch/arm/cpu/arm920t/config.mk +++ b/arch/arm/cpu/arm920t/config.mk @@ -6,10 +6,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 12b0d09..4d9895f 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -6,13 +6,6 @@ # PLATFORM_CPPFLAGS += -march=armv5te -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk index eb81a57..438668d 100644 --- a/arch/arm/cpu/arm946es/config.mk +++ b/arch/arm/cpu/arm946es/config.mk @@ -6,10 +6,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk index eb81a57..438668d 100644 --- a/arch/arm/cpu/arm_intcm/config.mk +++ b/arch/arm/cpu/arm_intcm/config.mk @@ -6,10 +6,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index f0d9c04..38b7c40 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -10,14 +10,6 @@ PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) - # SEE README.arm-unaligned-accesses PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk index fd47c60..894861f 100644 --- a/arch/arm/cpu/ixp/config.mk +++ b/arch/arm/cpu/ixp/config.mk @@ -14,11 +14,3 @@ PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 PLATFORM_LDFLAGS += -EB USE_PRIVATE_LIBGCC = yes - -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index d8d263d..f09f3c5 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -7,10 +7,3 @@ # PLATFORM_CPPFLAGS += -mcpu=xscale -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk index b3026cc..3afa685 100644 --- a/arch/arm/cpu/sa1100/config.mk +++ b/arch/arm/cpu/sa1100/config.mk @@ -7,10 +7,3 @@ # PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) -- 1.8.3.2

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[U-Boot] [PATCH] arm: use canonical sub mnemonic
by Andreas Bießmann 14 Jan '14

14 Jan '14

Building some arm boards with older binutils may produce errors like this: ---8<--- crt0.S: Assembler messages: crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)' --->8--- Use canonical version of the subtract mnemonic to avoid those issues. Reported-by: Alexey Smishlayev <alexey(a)xtech2.lv> Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> --- arch/arm/cpu/armv7/lowlevel_init.S | 2 +- arch/arm/lib/crt0.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 69e3053..f1aea05 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -24,7 +24,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_SPL_BUILD ldr r9, =gdata #else - sub sp, #GD_SIZE + sub sp, sp, #GD_SIZE bic sp, sp, #7 mov r9, sp #endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index ac54b93..dfc2de9 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,7 +67,7 @@ ENTRY(_main) ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - sub sp, #GD_SIZE /* allocate one GD above SP */ + sub sp, sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r9, sp /* GD is above SP */ mov r0, #0 -- 1.7.10.4

2 3

[U-Boot] [PATCH 1/2] socfpga: Adding Scan Manager driver
by Chin Liang See 13 Jan '14

13 Jan '14

Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 ++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 ++++++++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + include/configs/socfpga_cyclone5.h | 1 + 6 files changed, 335 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3e84a0c..4edc5d4 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,4 +9,4 @@ obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c new file mode 100644 index 0000000..30cbb8b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/scan_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_scan_manager *scan_manager_base = + (void *)(SOCFPGA_SCANMGR_ADDRESS); +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Function to check IO scan chain engine status and wait if the engine is + * is active. Poll the IO scan chain engine till maximum iteration reached. + */ +static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter) +{ + uint32_t scanmgr_status; + + scanmgr_status = readl(&scan_manager_base->stat); + + /* Poll the engine until the scan engine is inactive */ + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) + || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) { + + max_iter--; + + if (max_iter > 0) + scanmgr_status = readl(&scan_manager_base->stat); + else + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE; + } + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE; +} + + + +/* Program HPS IO Scan Chain */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain) +{ + + uint16_t tdi_tdo_header; + uint32_t io_program_iter; + uint32_t io_scan_chain_data_residual; + uint32_t residual; + uint32_t i; + uint32_t index = 0; + + /* De-assert reinit if the IO scan chain is intended for HIO */ + if (3 == io_scan_chain_id) + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Check if the scan chain engine is inactive and the + * WFIFO is empty before enabling the IO scan chain + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + return 1; + } + + /* + * Enable IO Scan chain based on scan chain id + * Note: only one chain can be enabled at a time + */ + setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + + /* + * Calculate number of iteration needed for full 128-bit (4 x32-bits) + * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits + */ + io_program_iter = io_scan_chain_len_in_bits >> + IO_SCAN_CHAIN_128BIT_SHIFT; + io_scan_chain_data_residual = io_scan_chain_len_in_bits & + IO_SCAN_CHAIN_128BIT_MASK; + + /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD << + TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* Program IO scan chain in 128-bit iteration */ + for (i = 0; i < io_program_iter; i++) { + + /* write TDI_TDO packet header to scan manager */ + writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte); + + /* calculate array index */ + index = i * 4; + + /* write 4 successive 32-bit IO scan chain data into WFIFO */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 1], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 2], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 3], + &scan_manager_base->fifoquadbyte); + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + return 1; + } + } + + /* Calculate array index for final TDI_TDO packet */ + index = io_program_iter * 4; + + /* Final TDI_TDO packet if any */ + if (0 != io_scan_chain_data_residual) { + + /* + * Calculate number of quad bytes FIFO write + * needed for the final TDI_TDO packet + */ + io_program_iter = io_scan_chain_data_residual >> + IO_SCAN_CHAIN_32BIT_SHIFT; + + /* + * Construct TDI_TDO packet for remaining IO + * scan chain (2 bytes) + */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + ((io_scan_chain_data_residual - 1) + << TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* + * Program the last part of IO scan chain write TDI_TDO packet + * header (2 bytes) to scan manager + */ + writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte); + + for (i = 0; i < io_program_iter; i++) { + /* + * write remaining scan chain data into scan + * manager WFIFO with 4 bytes write + */ + writel(iocsr_scan_chain[index + i], + &scan_manager_base->fifoquadbyte); + } + + index += io_program_iter; + residual = io_scan_chain_data_residual & + IO_SCAN_CHAIN_32BIT_MASK; + + if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) { + /* + * write the last 4B scan chain data + * into scan manager WFIFO + */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifoquadbyte); + + } else { + /* + * write the remaining 1 - 3 bytes scan chain + * data into scan manager WFIFO byte by byte + * to prevent JTAG engine shifting unused data + * from the FIFO and mistaken the data as a + * valid command (even though unused bits are + * set to 0, but just to prevent hardware + * glitch) + */ + for (i = 0; i < residual; i += 8) { + writel(((iocsr_scan_chain[index] >> i) + & IO_SCAN_CHAIN_BYTE_MASK), + &scan_manager_base->fifosinglebyte); + + } + } + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + return 1; + } + } /* if (io_scan_chain_data_residual) */ + + /* Disable IO Scan chain when configuration done*/ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + + return 0; +} + +int scan_mgr_configure_iocsr(void) +{ + int status = 0; + + /* configure the IOCSR through scan chain */ + status |= scan_mgr_io_scan_chain_prg(0, + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table); + status |= scan_mgr_io_scan_chain_prg(1, + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table); + status |= scan_mgr_io_scan_chain_prg(2, + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table); + status |= scan_mgr_io_scan_chain_prg(3, + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table); + return status; +} + + + diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 36a00c3..8a49a1a 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -32,6 +32,10 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + /* configure the IOCSR / IO buffer settings */ + if (scan_mgr_configure_iocsr()) + hang(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h new file mode 100644 index 0000000..dfbfade --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifosinglebyte; + u32 fifodoublebyte; + u32 fifoquadbyte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT (7) + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK (0x7F) + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT (5) + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK (0x1F) + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK (0xFF) + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT (24) + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD (127) + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE (0x80) + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT (8) + +/* IO scan chain engine is idle */ +#define SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE (0) + +/* IO scan chain engine is active */ +#define SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE (1) + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define MAX_WAITING_DELAY_IO_SCAN_ENGINE (100) + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 50c4ebd..8d329cf 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -13,5 +13,6 @@ #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 980636c..981a26b 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" /* * High level configuration -- 1.7.9.5

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[U-Boot] [PATCH] arm: New stack pointer is already aligned
by Tom Rini 13 Jan '14

13 Jan '14

The code in arch/arm/lib/board.c::board_init_f that sets gd->start_addr_sp has already make sure we're 8-byte aligned, so we don't need to do that again. Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/lib/crt0.S | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index ac54b93..6b5ec01 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -82,7 +82,6 @@ ENTRY(_main) */ ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ sub r9, r9, #GD_SIZE /* new GD is below bd */ -- 1.7.9.5

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[U-Boot] [PATCH 2/2] ARM: versatile: pass console setting to the kernel
by Linus Walleij 13 Jan '14

13 Jan '14

The Versatiles come up with the primary UART set to ttyAMA0 at 38400 baud, and unless we pass this to the kernel it will assume it is set to 9600 baud which will be quite awkward for the terminal, let's try to be helpful and inform the kernel what setting is used. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- include/configs/versatile.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 10738ac24be0..29c32fee5178 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -101,7 +101,8 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ - "netdev=25,0,0xf1010000,0xf1010010,eth0" + "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ + "console=ttyAMA0,38400n1" /* * Static configuration when assigning fixed address -- 1.8.3.1

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[U-Boot] [PATCH 1/2] ARM: versatile: pass correct machine type for Versatile AB
by Linus Walleij 13 Jan '14

13 Jan '14

When U-Boot is configured for Versatile AB, it will still pass the machine ID of Versatile PB to the kernel. After this simple fix the system boots correctly. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/armltd/versatile/versatile.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 30a3b904db4c..4e2d3421d8b1 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -52,7 +52,11 @@ int board_early_init_f (void) int board_init (void) { /* arch number of Versatile Board */ +#ifdef CONFIG_ARCH_VERSATILE_AB + gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB; +#else gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; -- 1.8.3.1

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[U-Boot] [PATCH] cmd_sf: Mention in the help text that mode, addr, offset and len must be given in hex.
by Jakob Unterwurzacher 08 Jan '14

08 Jan '14

These parameters are always interpreted as hex, even without 0x prefix. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher(a)theobroma-systems.com> --- common/cmd_sf.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 0a17782..0f7c0a3 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -531,6 +531,7 @@ U_BOOT_CMD( "sf erase offset [+]len - erase `len' bytes from `offset'\n" " `+len' round up `len' to block size\n" "sf update addr offset len - erase and write `len' bytes from memory\n" - " at `addr' to flash at `offset'" + " at `addr' to flash at `offset'\n" + "Parameters mode, addr, offset and len must be in hex." SF_TEST_HELP ); -- 1.7.2.5

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[U-Boot] [PATCH] spi: soft_spi: Support NULL din/dout buffers
by Andrew Ruder 08 Jan '14

08 Jan '14

This mirrors the conventions used in other SPI drivers (kirkwood, davinci, atmel, et al) where the din/dout buffer can be NULL when the received/transmitted data isn't important. This reduces the need for allocating additional buffers when write-only/read-only functionality is needed. In the din == NULL case, the received data is simply not stored. In the dout == NULL case, zeroes are transmitted. Signed-off-by: Andrew Ruder <andrew.ruder(a)elecsyscorp.com> --- drivers/spi/soft_spi.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 5d22351..5fdd091 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -137,9 +137,15 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, * Check if it is time to work on a new byte. */ if((j % 8) == 0) { - tmpdout = *txd++; + if (txd) { + tmpdout = *txd++; + } else { + tmpdout = 0; + } if(j != 0) { - *rxd++ = tmpdin; + if (rxd) { + *rxd++ = tmpdin; + } } tmpdin = 0; } @@ -164,9 +170,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, * bits over to left-justify them. Then store the last byte * read in. */ - if((bitlen % 8) != 0) - tmpdin <<= 8 - (bitlen % 8); - *rxd++ = tmpdin; + if (rxd) { + if((bitlen % 8) != 0) + tmpdin <<= 8 - (bitlen % 8); + *rxd++ = tmpdin; + } if (flags & SPI_XFER_END) spi_cs_deactivate(slave); -- 1.8.4.rc3

2 1

[U-Boot] [PATCH] Fix problems in chip select selection in imx23, 28 spi code
by Asok Subramanian 08 Jan '14

08 Jan '14

Fix problems in chip select selection in imx23,28 spi code The spi function code for imx23,28 currently does not work for chip select other than 0. This is because the register HW_SSP_CTRL0 is first reset and the code does not load the CS bits again into HW_SSP_CTRL0 after the reset. The proposed fix reloads the CS bits after the reset. Signed-off-by: Asok Subramanian <asok at vyassoft.com> --- drivers/spi/mxs_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 3cf7142..15681dc 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -32,6 +32,7 @@ struct mxs_spi_slave { uint32_t max_khz; uint32_t mode; struct mxs_ssp_regs *regs; + unsigned int cs; }; static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) @@ -74,6 +75,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxs_slave->max_khz = max_hz / 1000; mxs_slave->mode = mode; mxs_slave->regs = mxs_ssp_regs_by_bus(bus); + mxs_slave->cs = cs; ssp_regs = mxs_slave->regs; reg = readl(&ssp_regs->hw_ssp_ctrl0); @@ -102,7 +104,7 @@ int spi_claim_bus(struct spi_slave *slave) mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); - writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0); + writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT | (mxs_slave->cs) << MXS_SSP_CHIPSELECT_SHIFT, &ssp_regs->hw_ssp_ctrl0); reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; -- 1.7.9.5

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