November 2013 - U-Boot

[U-Boot] [PATCH] sandbox: Use system headers first for sandbox's os.c in a different way
by Masahiro Yamada 29 Jan '14

29 Jan '14

Commit cbe5cdfcd changed config.mk and arch/sandbox/cpu/Makefile to use -idirafter instead of -I and remove -nostdinc. But * Sandbox-specific code dirties config.mk * os.c is compiled without such compiler flags as: -Wall -Wstrict-prototypes -Wno-format-security -fno-builtin -ffreestanding -fno-stack-protector -fstack-usage -Wno-format-nonliteral This commit use -idirafter and remove the -nostdinc differently and more simply. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Simon Glass <sjg(a)chromium.org> --- Hello Simon Could you check if this patch works for you? arch/sandbox/cpu/Makefile | 8 ++++---- config.mk | 9 ++------- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 58c2537..b564294 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -10,7 +10,7 @@ obj-y := cpu.o os.o start.o state.o # os.c is build in the system environment, so needs standard includes -$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \ - $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) -$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \ - $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) +$(obj)os.o: CFLAGS := $(filter-out -nostdinc,\ + $(patsubst -I%,-idirafter%,$(CFLAGS))) +$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,\ + $(patsubst -I%,-idirafter%,$(CPPFLAGS))) diff --git a/config.mk b/config.mk index d5b09a0..206de20 100644 --- a/config.mk +++ b/config.mk @@ -250,16 +250,11 @@ Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file) endif endif -# Sandbox needs the base flags and includes, so keep them around -BASE_CPPFLAGS := $(CPPFLAGS) - ifneq ($(OBJTREE),$(SRCTREE)) -BASE_INCLUDE_DIRS := $(OBJTREE)/include +CPPFLAGS += -I$(OBJTREE)/include endif -BASE_INCLUDE_DIRS += $(TOPDIR)/include $(SRCTREE)/arch/$(ARCH)/include - -CPPFLAGS += $(patsubst %, -I%, $(BASE_INCLUDE_DIRS)) +CPPFLAGS += -I$(TOPDIR)/include -I$(SRCTREE)/arch/$(ARCH)/include CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) -- 1.8.3.2

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[U-Boot] [PATCH v4 0/8] Provide a mechanism to avoid using #ifdef everywhere
by Simon Glass 26 Jan '14

26 Jan '14

Many parts of the U-Boot code base are sprinkled with #ifdefs. This makes different boards compile different versions of the source code, meaning that we must build all boards to check for failures. It is easy to misspell an #ifdef and there is not as much checking of this by the compiler. Multiple dependent #ifdefs are harder to do than with if..then..else. Variable declarations must be #idefed as well as the code that uses them, often much later in the file/function. #ifdef indents don't match code indents and have their own separate indent feature. Overall, excessive use of #idef hurts readability and makes the code harder to modify and refactor. For people coming newly into the code base, #ifdefs can be a big barrier. The use of #ifdef in U-Boot has possibly got a little out of hand. In an attempt to turn the tide, this series includes a patch which provides a way to make CONFIG macros available to C code without using the preprocessor. This makes it possible to use standard C conditional features such as if/then instead of #ifdef. A README update exhorts compliance. As an example of how to use this, this series replaces all but two #ifdefs from the main code body of common/main.c, which is one of the largest users of #ifdef, even after a recent cleanup: $ for f in $(find . -name *.c); do echo $(grep -c "ifdef" $f) $f; \ done |sort -nr |head 82 ./common/board_r.c 57 ./common/board_f.c 57 ./arch/powerpc/cpu/mpc83xx/cpu_init.c 49 ./common/main.c 49 ./arch/powerpc/lib/board.c 45 ./drivers/video/cfb_console.c 40 ./drivers/mtd/cfi_flash.c 38 ./net/tftp.c 37 ./drivers/usb/host/ohci-hcd.c 36 ./drivers/fpga/ivm_core.c Code size for this series seems to be roughly neutral (below numbers are average change in byte size for each region: blackfin: (for 21/35 boards) all -13.7 text -13.7 x86: (for 1/1 boards) bss +4.0 data +4.0 text -8.0 avr32: (for 10/10 boards) all -7.2 data -2.0 text -5.2 m68k: (for 35/50 boards) all -30.9 text -30.9 powerpc: (for 673/675 boards) all -20.8 bss +0.4 data +0.0 rodata -0.7 spl/u-boot-spl:all +0.1 spl/u-boot-spl:data +0.1 text -20.5 sandbox: (for 1/1 boards) all +16.0 bss +16.0 sh: (for 16/21 boards) all -76.2 bss +3.2 rodata -15.5 text -64.0 nios2: (for 3/3 boards) all +18.7 bss +1.3 data -1.3 text +18.7 microblaze: (for 1/1 boards) all -864.0 bss +8.0 rodata -216.0 text -656.0 arm: (for 286/344 boards) all -51.7 bss -5.7 data +0.2 rodata -3.9 spl/u-boot-spl:all +0.2 spl/u-boot-spl:bss +0.2 text -42.4 nds32: (for 3/3 boards) all -52.0 text -52.0 Note that a config_drop.h file is added - this defines all the CONFIGs which are not used in any board config file. Without this, autoconf cannot define the macros for this CONFIGs. Compile time for main.c does not seem to be any different in my tests. The time to perform the 'dep' step (which now creates autoconf.h) increases, from about 2.8s to about 4.6s. This additional time is used to grep, sed and sort the contents of all the header file in U-Boot. The time for an incremental build is not affected. It would be much more efficient to maintain a list of all available CONFIG defines, but no such list exists at present. Buildman output shows no additional failures from mainline (commit 02 is a bug in buildman and commit 11 will be sent separately): $ ./tools/buildman/buildman -b us-config7 -s Summary of 10 commits for 1178 boards (32 threads, 1 job per thread) 01: usb: rename board_usb_init_type to usb_init_type blackfin: + bf561-acvilon cm-bf561 blackstamp br4 bct-brettl2 cm-bf527 dnp5370 bf506f-ezkit ip04 bf527-sdp bf609-ezkit bf537-stamp bf527-ezkit-v2 cm-bf537e tcm-bf518 cm-bf537u bf537-pnav cm-bf533 pr1 bf533-ezkit ibf-dsp561 bf537-srv1 cm-bf548 bf537-minotaur bf538f-ezkit bf548-ezkit bf525-ucr2 blackvme bf527-ezkit tcm-bf537 bf533-stamp bf518f-ezbrd bf527-ad7160-eval bf526-ezbrd bf561-ezkit m68k: + M54455EVB_a66 M5329AFEE M5249EVB idmr M5208EVBE eb_cpu5282 M5475FFE M54451EVB astro_mcf5373l M54418TWR_serial_rmii M54455EVB_intel M5282EVB M54455EVB_i66 M5475GFE M5253DEMO M54455EVB_stm33 M5485BFE M5485DFE TASREG M5329BFEE M52277EVB M5475EFE M5475CFE cobra5272 M5485AFE M53017EVB M5485HFE M5235EVB M5253EVBE M54418TWR_nand_mii M54418TWR_nand_rmii_lowfreq M5475BFE M5475DFE M5275EVB M52277EVB_stmicro eb_cpu5282_internal M54451EVB_stmicro M5271EVB M5485GFE M5485EFE M5485FFE M54418TWR M5235EVB_Flash32 M5373EVB M54418TWR_nand_rmii M54418TWR_serial_mii M5485CFE M54455EVB M5475AFE M5272C3 powerpc: + MVBLM7 MVSMR lcd4_lwmon5 sparc: + grsim grsim_leon2 gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60 sh: + rsk7269 rsk7264 sh7752evb rsk7203 sh7757lcr microblaze: + microblaze-generic openrisc: + openrisc-generic arm: + pm9g45 qong palmtc zipitz2 omap3_zoom1 omap3_overo goflexhome davinci_sonata VCMA9 iconnect km_kirkwood_pci ib62x0 lubbock ethernut5 zynq_dcc vpac270_nor_128 colibri_pxa270 sheevaplug kzm9g am3517_crane zynq tnetv107x_evm xaeniax magnesium palmtreo680 kmsuv31 polaris omap3_sdp3430 imx27lite mgcoge3un vpac270_nor_256 pxa255_idp kmnusa kmcoge5un am3517_evm nhk8815_onenand openrd_client openrd_base nhk8815 km_kirkwood dns325 mcx lp8x4x vpac270_ond_256 smdk2410 h2200 jornada balloon3 omap3_evm omap3_logic dockstar portl2 palmld openrd_ultimate trizepsiv pogo_e02 pm9263 devkit8000 02: Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> arm: + am43xx_evm dra7xx_evm powerpc: + T1040QDS 03: Implement autoconf header file arm: am43xx_evm dra7xx_evm powerpc: T1040QDS 04: main: Use autoconf for boot retry feature 05: main: Remove CONFIG #ifdefs from the abortboot() code 06: main: Use autoconf to remove #ifdefs around process_boot_delay() 07: main: Use autoconf for boot_delay code 08: main: Use autoconf for parser selection 09: main: Use autoconf in command line reading 10: main: Use autoconf in main_loop() 11: fix Cover-letter-cc Changes in v4: - Rebase on current master - Split out new patch to remove #ifdefs around process_boot_delay() - Tidy up code style nits with new checkpatch Changes in v3: - Add comment as to why we use [A-Za-z0-9_][A-Za-z0-9_]* - Fix missing && in if() statement - Remove the extra config_of_libfdt() condition in main_loop() - Remove unneeded retry_min variable - Rename sed scripts to more useful names - Simplify code for finding out bootdelay from config or environment - Update config_xxx() to autoconf_xxx() in comments/README/sed - Update config_xxx_enabled() to autoconf_has_xxx() in comments/README/sed Changes in v2: - Add a grep to the sed/sort pipe to speed up processing - Fix up a few errors and comments in the original RFC - Split out changes to main.c into separate patches - Use autoconf_...() instead of config_...() - Use autoconf_has_...() instead of config_..._enabled() Simon Glass (8): Implement autoconf header file main: Use autoconf for boot retry feature main: Remove CONFIG #ifdefs from the abortboot() code main: Use autoconf to remove #ifdefs around process_boot_delay() main: Use autoconf for boot_delay code main: Use autoconf for parser selection main: Use autoconf in command line reading main: Use autoconf in main_loop() Makefile | 43 ++- README | 87 +++++- common/main.c | 629 ++++++++++++++++++----------------------- include/command.h | 2 - include/common.h | 6 +- include/config_drop.h | 17 ++ include/fdt_support.h | 4 +- include/hush.h | 2 - include/menu.h | 2 - tools/scripts/define2value.sed | 37 +++ tools/scripts/define2zero.sed | 32 +++ 11 files changed, 492 insertions(+), 369 deletions(-) create mode 100644 include/config_drop.h create mode 100644 tools/scripts/define2value.sed create mode 100644 tools/scripts/define2zero.sed -- 1.8.4.1

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[U-Boot] fdt performance
by Aaron Williams 26 Jan '14

26 Jan '14

Hi all, In our bootloader based off of 2013.07 we make extensive use of the flat device tree. In profiling our bootloader in our simulator I found that the function eating up the most time is fdt_next_tag. Looking at it, especially fdt_offset_ptr, it looks like there is a lot of room for improvement especially in the skip name section. Some of the checks in fdt_offset_ptr also look useless, such as if ((offset + len) < offset) which will always be false, or if (p + len < p) len is always positive. -Aaron -- Aaron Williams Software Engineer Cavium, Inc. (408) 943-7198 (510) 789-8988 (cell)

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[U-Boot] [PATCH 2/2] ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL
by Jassi Brar 24 Jan '14

24 Jan '14

The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh(a)linaro.org> --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 - arch/arm/include/asm/arch-omap4/sys_proto.h | 1 - arch/arm/include/asm/arch-omap5/sys_proto.h | 1 - board/ti/omap5_evm/evm.c | 11 - board/ti/omap5_evm/mux_data.h | 234 ------------------------ board/ti/panda/panda.c | 28 --- board/ti/panda/panda_mux_data.h | 186 ------------------- board/ti/sdp4430/sdp.c | 18 -- board/ti/sdp4430/sdp4430_mux_data.h | 197 -------------------- 9 files changed, 0 insertions(+), 682 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 459ebb5..077fc27 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -51,16 +51,10 @@ static void set_mux_conf_regs(void) set_muxconf_regs_essential(); break; case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: set_muxconf_regs_essential(); -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; } } diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index d633573..90befa1 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,7 +37,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 74feb90..9a49393 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -38,7 +38,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c index c8dfdf8..4b61819 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_evm/evm.c @@ -80,17 +80,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h index a82795d..c5af6cd 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_evm/mux_data.h @@ -67,238 +67,4 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - - {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ - {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ - {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ - {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ - {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ - {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ - {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ - {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ - {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ - {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ - {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ - {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ - {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ - {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ - {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ - {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ - {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ - {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ - {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ - {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ - {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ - {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ - {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ - {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ - {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ - {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ - {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ - {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ - {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ - {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ - {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ - {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ - {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ - {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ - {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ - {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ - {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ - {HSI1_CADATA, (M6)}, /* GPIO3_71 */ - {UART1_TX, (M0)}, /* UART1_TX */ - {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ - {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ - {UART1_RTS, (M0)}, /* UART1_RTS */ - {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ - {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ - {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ - {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ - {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ - {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ - {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ - {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ - {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ - {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ - {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ - {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ - {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ - {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ - {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ - {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ - {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ - {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ - {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ - {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ - {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ - {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ - {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ - {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ - {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ - {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ - {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ - {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ - {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ - {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ - {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ - {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ - {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ - {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ - {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ - {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ - {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ - {RFBI_RE, (M4)}, /* KBD_COL4 */ - {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ - {RFBI_DATA8, (M4)}, /* KBD_COL3 */ - {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ - {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ - {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ - {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ - {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ - {RFBI_DATA14, (M4)}, /* KBD_COL7 */ - {RFBI_DATA15, (M4)}, /* KBD_COL6 */ - {GPIO6_182, (M6)}, /* GPIO6_182 */ - {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ - {GPIO6_184, (M4)}, /* KBD_COL2 */ - {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ - {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ - {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ - {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ - {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ - {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ - {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ - {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ - {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ - {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ - {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ - {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ - {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ - {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ - {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ - {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ - {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ - {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ - {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ - {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ - {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ - {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ - {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ - {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ - {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ - {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ - {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ - {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ - {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ - {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ - {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ - {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ - {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ - {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ - {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ - {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ - {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ - {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ - {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ - {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ - {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ - {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ - {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ - {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ - {CAM_STROBE, (M0)}, /* CAM_STROBE */ - {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ - {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ - {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ - {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ - {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ - {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ - {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ - {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ - {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ - {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ - {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ - {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ - {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ - {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ - {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ - {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ - {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ - {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ - {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ - {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ - {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ - {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ - {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ - {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ - {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ - {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ - {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ - {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ - {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ - {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ - {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ - {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ - {UART5_TX, (M0)}, /* UART5_TX */ - {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ - {UART5_RTS, (M0)}, /* UART5_RTS */ - {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ - {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ - {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ - {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ - {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ - {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ - {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ - {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ - {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ - {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ - {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ - {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ - {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ - {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ - {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - -/* - * This pad keeps C2C Module always enabled. - * Putting this in safe mode do not cause the issue. - * C2C driver could enable this mux setting if needed. - */ - {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ - {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ - {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ - {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ - {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ - {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ - {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ - {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ - {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ - {JTAG_TDO, (M0)}, /* JTAG_TDO */ - {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ - {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ - {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ - {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ - {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ - {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ - {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ - {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ - {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ - {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ - {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ - {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ - {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ - {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ - {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ - -}; - #endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index ee82771..25cbc7c 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -148,34 +148,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_CORE, - core_padconf_array_non_essential_4430, - sizeof(core_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - else - do_set_mux(CONTROL_PADCONF_CORE, - core_padconf_array_non_essential_4460, - sizeof(core_padconf_array_non_essential_4460) / - sizeof(struct pad_conf_entry)); - - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_WKUP, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 5939257..4300401 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -100,190 +100,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ - {UART2_RTS, (M7)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ - {UART2_TX, (M7)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { - {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ - {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ -}; - #endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 982c771..4d31dac 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -87,24 +87,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) { - do_set_mux(CONTROL_PADCONF_WKUP, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - } -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 0760dad..76a9331 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -81,201 +81,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ -}; - #endif /* _SDP4430_MUX_DATA_H */ -- 1.7.4.1

2 1

[U-Boot] [PATCH 1/2] ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL
by Jassi Brar 24 Jan '14

24 Jan '14

The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh(a)linaro.org> --- Hi, The commit f3f98bb0 seems to suggest we want to move these settings into the kernel, but perhaps we should also evaluate the option of making these inits fully board specific but in u-boot? Thanks. arch/arm/cpu/armv7/omap-common/clocks-common.c | 47 ------------- arch/arm/cpu/armv7/omap4/clocks.c | 84 ----------------------- arch/arm/cpu/armv7/omap5/clocks.c | 87 ------------------------ arch/arm/include/asm/arch-omap4/clocks.h | 1 - arch/arm/include/asm/arch-omap5/clocks.h | 1 - 5 files changed, 0 insertions(+), 220 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277..fc14465 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -326,49 +326,6 @@ static void setup_dplls(void) #endif } -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL -static void setup_non_essential_dplls(void) -{ - u32 abe_ref_clk; - const struct dpll_params *params; - - /* IVA */ - clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, - CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - - params = get_iva_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); - - /* Configure ABE dpll */ - params = get_abe_dpll_params(); -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; -#else - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; - /* - * We need to enable some additional options to achieve - * 196.608MHz from 32768 Hz - */ - setbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| - CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| - CM_CLKMODE_DPLL_LPMODE_EN_MASK| - CM_CLKMODE_DPLL_REGM4XEN_MASK); - /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_RAMP_RATE_MASK, - 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); -#endif - - /* Select the right reference clk */ - clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, - CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, - abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); - /* Lock the dpll */ - do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); -} -#endif - void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv) { u32 step; @@ -584,10 +541,6 @@ void prcm_init(void) enable_basic_clocks(); scale_vcores(); setup_dplls(); -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL - setup_non_essential_dplls(); - enable_non_essential_clocks(); -#endif break; default: break; diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 5bd0a88..b3fc652 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -431,87 +431,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); } - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - &prcm->cm_l4per_mcbsp4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index eecfbad..6c5441f 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -405,90 +405,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); } - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_mpu_m3_mpu_m3_clkctrl, - &prcm->cm_ivahd_ivahd_clkctrl, - &prcm->cm_ivahd_sl2_clkctrl, - &prcm->cm_dsp_dsp_clkctrl, - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index be20fc0..eff7d02 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -753,7 +753,6 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto, u32 *const *clk_modules_explicit_en, diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 5f1a7aa..4f387a7 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -726,7 +726,6 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv); void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); -void enable_non_essential_clocks(void); void enable_basic_uboot_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto, -- 1.7.4.1

3 2

[U-Boot] U-boot for 64bit ARMv8
by Richard Schmitt 24 Jan '14

24 Jan '14

Is anyone considering porting/supporting uboot for ARMv8. Our initial investigation of boot loader support for ARMv8 indicates that the only boot loader currently being targeted is UEFI. The decisions we need to make are: - Do we move to UEFI on ARM? - Can we leverage someone else's enablement of ARMv8? - Do we provide our own enablement of ARMv8? Any opinions? Rich

5 6

[U-Boot] [PATCH 1/8] Tegra124: Add arch-tegra124 include/header files
by Tom Warren 23 Jan '14

23 Jan '14

No real HW change on T124 for 90% of the toys, so just include a common T1x4 header file (based on T114 headers), and if a new register/bit is needed, add it at the end. Some headers (clk_rst, clock-tables, pinmux, etc.) had too many changes in structs, devices, etc. added/removed, so they are added as complete new files for T124, and can be diffed against T114 headers to see what's changed (again, not a lot). In a future (RSN) patch I'll point the T114 headers at the new common tegra1x4-xxx files, too. Change-Id: I02a37e1a6bee0c62721f1ffb3968379b36d0f2dd Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/include/asm/arch-tegra/clk_rst.h | 160 +++++- arch/arm/include/asm/arch-tegra/pmc.h | 2 +- arch/arm/include/asm/arch-tegra/spl.h | 13 + arch/arm/include/asm/arch-tegra/tegra1x4_ahb.h | 91 +++ arch/arm/include/asm/arch-tegra/tegra1x4_clock.h | 19 + arch/arm/include/asm/arch-tegra/tegra1x4_emc.h | 76 +++ arch/arm/include/asm/arch-tegra/tegra1x4_flow.h | 40 ++ arch/arm/include/asm/arch-tegra/tegra1x4_fush.h | 28 + .../include/asm/arch-tegra/tegra1x4_gp_padctrl.h | 74 +++ arch/arm/include/asm/arch-tegra/tegra1x4_pmu.h | 14 + arch/arm/include/asm/arch-tegra/tegra1x4_spi.h | 23 +- arch/arm/include/asm/arch-tegra/tegra1x4_sysctr.h | 26 + arch/arm/include/asm/arch-tegra/tegra1x4_usb.h | 272 +++++++++ arch/arm/include/asm/arch-tegra124/ahb.h | 13 + arch/arm/include/asm/arch-tegra124/clock-tables.h | 496 +++++++++++++++++ arch/arm/include/asm/arch-tegra124/clock.h | 15 + arch/arm/include/asm/arch-tegra124/emc.h | 13 + arch/arm/include/asm/arch-tegra124/flow.h | 13 + arch/arm/include/asm/arch-tegra124/funcmux.h | 23 + arch/arm/include/asm/arch-tegra124/fuse.h | 13 + arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 13 + arch/arm/include/asm/arch-tegra124/gpio.h | 303 ++++++++++ arch/arm/include/asm/arch-tegra124/hardware.h | 16 + arch/arm/include/asm/arch-tegra124/pinmux.h | 618 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra124/pmc.h | 368 ++++++++++++ arch/arm/include/asm/arch-tegra124/pmu.h | 13 + arch/arm/include/asm/arch-tegra124/spl.h | 13 + arch/arm/include/asm/arch-tegra124/sysctr.h | 13 + arch/arm/include/asm/arch-tegra124/tegra.h | 30 + arch/arm/include/asm/arch-tegra124/usb.h | 13 + 30 files changed, 2773 insertions(+), 51 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/spl.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_ahb.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_clock.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_emc.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_flow.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_fush.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_pmu.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_sysctr.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra1x4_usb.h create mode 100644 arch/arm/include/asm/arch-tegra124/ahb.h create mode 100644 arch/arm/include/asm/arch-tegra124/clock-tables.h create mode 100644 arch/arm/include/asm/arch-tegra124/clock.h create mode 100644 arch/arm/include/asm/arch-tegra124/emc.h create mode 100644 arch/arm/include/asm/arch-tegra124/flow.h create mode 100644 arch/arm/include/asm/arch-tegra124/funcmux.h create mode 100644 arch/arm/include/asm/arch-tegra124/fuse.h create mode 100644 arch/arm/include/asm/arch-tegra124/gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra124/gpio.h create mode 100644 arch/arm/include/asm/arch-tegra124/hardware.h create mode 100644 arch/arm/include/asm/arch-tegra124/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra124/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h create mode 100644 arch/arm/include/asm/arch-tegra124/spl.h create mode 100644 arch/arm/include/asm/arch-tegra124/sysctr.h create mode 100644 arch/arm/include/asm/arch-tegra124/tegra.h create mode 100644 arch/arm/include/asm/arch-tegra124/usb.h diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 7045266..b5f4708 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -10,9 +10,10 @@ /* PLL registers - there are several PLLs in the clock controller */ struct clk_pll { - uint pll_base; /* the control register */ - uint pll_out[2]; /* output control */ - uint pll_misc; /* other misc things */ + uint pll_base; /* the control register */ + /* pll_out[0] is output A control, pll_out[1] is output B control */ + uint pll_out[2]; + uint pll_misc; /* other misc things */ }; /* PLL registers - there are several PLLs in the clock controller */ @@ -21,6 +22,13 @@ struct clk_pll_simple { uint pll_misc; /* other misc things */ }; +struct clk_pllm { + uint pllm_base; /* the control register */ + uint pllm_out; /* output control */ + uint pllm_misc1; /* misc1 */ + uint pllm_misc2; /* misc2 */ +}; + /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ struct clk_set_clr { uint set; @@ -38,7 +46,8 @@ enum { TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/ + TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ + TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ }; /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ @@ -47,7 +56,7 @@ struct clk_rst_ctlr { uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ uint crc_reserved0; /* reserved_0, 0x1C */ - uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ + uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ @@ -75,7 +84,21 @@ struct clk_rst_ctlr { uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */ + uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */ + + uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + + uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + + uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ + + uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + + uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; @@ -105,10 +128,10 @@ struct clk_rst_ctlr { uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */ + uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */ + uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ @@ -142,6 +165,47 @@ struct clk_rst_ctlr { uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ + + uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ + uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ + uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ + uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ + uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ + uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ + uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ + uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ + uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ + uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ + uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ + uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ + uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ + uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ + uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ + uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ + uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ + uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ + uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ + uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ + uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ + uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ + uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ + uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ + uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ + uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ + uint crc_reserved51[1]; /* _reserved_51, 0x538 */ + uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ + uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ + uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ + uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ + uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ + uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ + uint crc_reserved52[1]; /* _reserved_52, 0x554 */ + uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ + uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ + + /* T124 - skip to 0x600 here for new CLK_SOURCE_ regs */ + uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ + uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ }; /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ @@ -226,9 +290,15 @@ enum { #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_XOBP_SHIFT 1 -#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) +/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ +#define OSC_XOE_SHIFT 0 +#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) +#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) +#define OSC_XOBP_SHIFT 1 +#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) +#define OSC_XOFS_SHIFT 4 +#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) +#define OSC_DRIVE_STRENGTH 7 /* * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits @@ -300,7 +370,7 @@ enum { #define SUPER_SCLK_DIVISOR_SHIFT 0 #define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) -/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */ +/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 #define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) #define CLK_SYS_RATE_AHB_RATE_SHIFT 4 @@ -310,23 +380,53 @@ enum { #define CLK_SYS_RATE_APB_RATE_SHIFT 0 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) -/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_NONCPURESET (1 << 29) +/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ +#define CLR_CPURESET0 (1 << 0) +#define CLR_CPURESET1 (1 << 1) +#define CLR_CPURESET2 (1 << 2) +#define CLR_CPURESET3 (1 << 3) +#define CLR_DBGRESET0 (1 << 12) +#define CLR_DBGRESET1 (1 << 13) +#define CLR_DBGRESET2 (1 << 14) +#define CLR_DBGRESET3 (1 << 15) +#define CLR_CORERESET0 (1 << 16) +#define CLR_CORERESET1 (1 << 17) +#define CLR_CORERESET2 (1 << 18) +#define CLR_CORERESET3 (1 << 19) +#define CLR_CXRESET0 (1 << 20) +#define CLR_CXRESET1 (1 << 21) +#define CLR_CXRESET2 (1 << 22) +#define CLR_CXRESET3 (1 << 23) +#define CLR_L2RESET (1 << 24) +#define CLR_NONCPURESET (1 << 29) +#define CLR_PRESETDBG (1 << 30) + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ +#define CLR_CPU3_CLK_STP (1 << 11) +#define CLR_CPU2_CLK_STP (1 << 10) +#define CLR_CPU1_CLK_STP (1 << 9) +#define CLR_CPU0_CLK_STP (1 << 8) + +/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ +#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) + +/* CRC_CLK_ENB_V_SET_0 0x440 */ +#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) +#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) +#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ +#define PLLU_POWERDOWN (1 << 16) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLL_ACTIVE_POWERDOWN (1 << 12) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) + +/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ +#define PLLX_IDDQ_SHIFT 3 +#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) #endif /* _TEGRA_CLK_RST_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index ba22236..84e4147 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -21,7 +21,7 @@ struct pmc_ctlr { uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ - uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ + uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */ uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ diff --git a/arch/arm/include/asm/arch-tegra/spl.h b/arch/arm/include/asm/arch-tegra/spl.h new file mode 100644 index 0000000..76af1f7 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/spl.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARCH_TEGRA_SPL_H_ +#define _ARCH_TEGRA_SPL_H_ + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_ahb.h b/arch/arm/include/asm/arch-tegra/tegra1x4_ahb.h new file mode 100644 index 0000000..f140607 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_ahb.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_AHB_H_ +#define _TEGRA1x4_AHB_H_ + +struct ahb_ctlr { + u32 reserved0; /* 00h */ + u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ + u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ + u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ + u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ + u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ + u32 reserved6[2]; /* 18h, 1ch */ + u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ + u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ + u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ + u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ + u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ + u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ + u32 reserved13[2]; /* 38h, 3ch */ + u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ + u32 reserved15; /* 44h */ + u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ + u32 reserved17; /* 4ch */ + u32 gizmo_se; /* _GIZMO_SE_0, 50h */ + u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ + u32 reserved20[3]; /* 58h, 5ch, 60h */ + u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ + u32 reserved22[3]; /* 68h, 6ch, 70h */ + u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ + u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ + u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ + u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ + u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ + u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ + u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ + u32 reserved30[13]; /* 90h ~ c0h */ + u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ + u32 reserved32[5]; /* c8h ~ d8h */ + u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ + u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ + u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ + u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ + u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ + u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ + u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ + u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ + /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ + u32 arbitration_ahb_mem_wrque_mst_id; + u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ + u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ + u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ + u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ + u32 reserved46[4]; /* 110h ~ 11ch */ + u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ + u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ + u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ + u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ + u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ + u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ + /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ + u32 axicif_fastsync0_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ + u32 axicif_fastsync1_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ + u32 axicif_fastsync2_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ + u32 axicif_fastsync0_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ + u32 axicif_fastsync1_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ + u32 axicif_fastsync2_mcclk_to_cpuclk; +}; + +#define PPSB_STOPCLK_ENABLE (1 << 2) + +#define GIZ_ENABLE_SPLIT (1 << 0) +#define GIZ_ENB_FAST_REARB (1 << 2) +#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) + +#define GIZ_USB_IMMEDIATE (1 << 18) + +/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ +#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) + +#endif /* _TEGRA1x4_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_clock.h b/arch/arm/include/asm/arch-tegra/tegra1x4_clock.h new file mode 100644 index 0000000..e652b50 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_clock.h @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra1x4 clock control functions */ + +#ifndef _TEGRA1x4_CLOCK_H_ +#define _TEGRA1x4_CLOCK_H_ + +#include <asm/arch-tegra/clock.h> + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +#endif /* _TEGRA1x4_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_emc.h b/arch/arm/include/asm/arch-tegra/tegra1x4_emc.h new file mode 100644 index 0000000..921a530 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_emc.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_EMC_H_ +#define _TEGRA1x4_EMC_H_ + +#define TEGRA_EMC_NUM_REGS 46 + +/* EMC Registers */ +struct emc_ctlr { + u32 cfg; /* 0x00: EMC_CFG */ + u32 reserved0[3]; /* 0x04 ~ 0x0C */ + u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ + u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ + u32 reserved1[2]; /* 0x18 ~ 0x18 */ + u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ + u32 pin; /* 0x24: EMC_PIN */ + u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ + u32 rc; /* 0x2C: EMC_RC */ + u32 rfc; /* 0x30: EMC_RFC */ + u32 ras; /* 0x34: EMC_RAS */ + u32 rp; /* 0x38: EMC_RP */ + u32 r2w; /* 0x3C: EMC_R2W */ + u32 w2r; /* 0x40: EMC_W2R */ + u32 r2p; /* 0x44: EMC_R2P */ + u32 w2p; /* 0x48: EMC_W2P */ + u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ + u32 wd_rcd; /* 0x50: EMC_WD_RCD */ + u32 rrd; /* 0x54: EMC_RRD */ + u32 rext; /* 0x58: EMC_REXT */ + u32 wdv; /* 0x5C: EMC_WDV */ + u32 quse; /* 0x60: EMC_QUSE */ + u32 qrst; /* 0x64: EMC_QRST */ + u32 qsafe; /* 0x68: EMC_QSAFE */ + u32 rdv; /* 0x6C: EMC_RDV */ + u32 refresh; /* 0x70: EMC_REFRESH */ + u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ + u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ + u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ + u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ + u32 act2pden; /* 0x84: EMC_ACT2PDEN */ + u32 ar2pden; /* 0x88: EMC_AR2PDEN */ + u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ + u32 txsr; /* 0x90: EMC_TXSR */ + u32 tcke; /* 0x94: EMC_TCKE */ + u32 tfaw; /* 0x98: EMC_TFAW */ + u32 trpab; /* 0x9C: EMC_TRPAB */ + u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ + u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ + u32 trefbw; /* 0xA8: EMC_TREFBW */ + u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ + u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ + u32 odt_read; /* 0xB4: EMC_ODT_READ */ + u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ + u32 mrs; /* 0xCC: EMC_MRS */ + u32 emrs; /* 0xD0: EMC_EMRS */ + u32 ref; /* 0xD4: EMC_REF */ + u32 pre; /* 0xD8: EMC_PRE */ + u32 nop; /* 0xDC: EMC_NOP */ + u32 self_ref; /* 0xE0: EMC_SELF_REF */ + u32 dpd; /* 0xE4: EMC_DPD */ + u32 mrw; /* 0xE8: EMC_MRW */ + u32 mrr; /* 0xEC: EMC_MRR */ + u32 reserved3; /* 0xF0: */ + u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ + u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ + u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ + u32 fbio_spare; /* 0x100: SBIO_SPARE */ + /* There are more registers ... */ +}; + +#endif /* _TEGRA1x4_EMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_flow.h b/arch/arm/include/asm/arch-tegra/tegra1x4_flow.h new file mode 100644 index 0000000..4654191 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_flow.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_FLOW_H_ +#define _TEGRA1x4_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +#endif /* _TEGRA1x4_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_fush.h b/arch/arm/include/asm/arch-tegra/tegra1x4_fush.h new file mode 100644 index 0000000..bafbc56 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_fush.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_FUSE_H_ +#define _TEGRA1x4_FUSE_H_ + +/* FUSE registers */ +struct fuse_regs { + u32 reserved0[9]; /* 0x00 - 0x20: */ + u32 fuse_bypass; /* 0x24: FUSE_FUSEBYPASS */ + u32 private_key_disable; /* 0x28: FUSE_PRIVATEKEYDISABLE */ + u32 disable_reg_program; /* 0x2C: FUSE_DISABLEREGPROGRAM */ + u32 write_access_sw; /* 0x30: FUSE_WRITE_ACCESS_SW */ + u32 reserved01[51]; /* 0x34 - 0xFC: */ + u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */ + u32 reserved1[3]; /* 0x104 - 0x10c: */ + u32 sku_info; /* 0x110 */ + u32 reserved2[13]; /* 0x114 - 0x144: */ + u32 fa; /* 0x148: FUSE_FA */ + u32 reserved3[21]; /* 0x14C - 0x19C: */ + u32 security_mode; /* 0x1A0 - FUSE_SECURITY_MODE */ +}; + +#endif /* _TEGRA1x4_FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_gp_padctrl.h b/arch/arm/include/asm/arch-tegra/tegra1x4_gp_padctrl.h new file mode 100644 index 0000000..f47a2db --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_gp_padctrl.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_GP_PADCTRL_H_ +#define _TEGRA1x4_GP_PADCTRL_H_ + +#include <asm/arch-tegra/gp_padctrl.h> + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x8C: */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0xC8-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ +}; + +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + +#endif /* _TEGRA1x4_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_pmu.h b/arch/arm/include/asm/arch-tegra/tegra1x4_pmu.h new file mode 100644 index 0000000..30d87fd --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_pmu.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_PMU_H_ +#define _TEGRA1x4_PMU_H_ + +/* Set core and CPU voltages to nominal levels */ +int pmu_set_nominal(void); + +#endif /* _TEGRA1x4_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_spi.h b/arch/arm/include/asm/arch-tegra/tegra1x4_spi.h index 93aa9ac..e797214 100644 --- a/arch/arm/include/asm/arch-tegra/tegra1x4_spi.h +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_spi.h @@ -1,25 +1,8 @@ /* - * NVIDIA Tegra SPI controller + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA1x4_SPI_H_ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_sysctr.h b/arch/arm/include/asm/arch-tegra/tegra1x4_sysctr.h new file mode 100644 index 0000000..71a2ef2 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_sysctr.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_SYSCTR_H_ +#define _TEGRA1x4_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA1x4_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra1x4_usb.h b/arch/arm/include/asm/arch-tegra/tegra1x4_usb.h new file mode 100644 index 0000000..d4d098e --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_usb.h @@ -0,0 +1,272 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA1x4_USB_H_ +#define _TEGRA1x4_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[2]; + + /* 0x130 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x140 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint reserved5_1; + + /* 0x150 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; + uint icusb_ctrl; + + /* 0x160 */ + uint ulpi_viewport; + uint reserved7; + uint reserved7_0; + uint reserved7_1; + + /* 0x170 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x190 */ + uint reserved9[8]; + + /* 0x1b0 */ + uint reserved10; + uint hostpc1_devlc; + uint reserved10_1[2]; + + /* 0x1c0 */ + uint reserved10_2[4]; + + /* 0x1d0 */ + uint reserved10_3[4]; + + /* 0x1e0 */ + uint reserved10_4[4]; + + /* 0x1f0 */ + uint reserved10_5; + uint otgsc; + uint usb_mode; + uint reserved10_6; + + /* 0x200 */ + uint endpt_nak; + uint endpt_nak_enable; + uint endpt_setup_stat; + uint reserved11_1[0x7D]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) +#define USB_SUSP_CLR (1 << 5) + +/* USBx_UTMIP_MISC_CFG0 */ +#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* Moved to Clock and Reset register space */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +/* Moved to Clock and Reset register space */ +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) + +/* USBx_UTMIP_PLL_CFG1_0 */ +/* Moved to Clock and Reset register space */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG0_0 */ +#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) +#define UTMIP_OTGPD (1 << 11) +#define UTMIP_BIASPD (1 << 10) +#define UTMIP_HSDISCON_LEVEL_SHIFT 2 +#define UTMIP_HSDISCON_LEVEL_MASK \ + (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) +#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 +#define UTMIP_HSSQUELCH_LEVEL_MASK \ + (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_FORCE_PDTRK_POWERDOWN 1 +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG0_1 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */ +#define PTS1_SHIFT 31 +#define PTS1_MASK (1 << PTS1_SHIFT) +#define STS1 (1 << 30) + +/* USB2D_HOSTPC1_DEVLC_0 */ +#define PTS_SHIFT 29 +#define PTS_MASK (0x7U << PTS_SHIFT) +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULPI 2 +#define PTS_ICUSB_SER 3 +#define PTS_HSIC 4 + +#define STS (1 << 28) + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define WKOC (1 << 22) +#define WKDS (1 << 21) +#define WKCN (1 << 20) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) +#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 +#define UTMIP_XCVR_HSSLEW_MSB_MASK \ + (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 +#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) +#define UTMIP_XCVR_SETUP_SHIFT 0 +#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 +#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ + (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) + + +/* Setup USB on the board */ +int board_usb_init(const void *blob); + +#endif /* _TEGRA1x4_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h new file mode 100644 index 0000000..3479d96 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/ahb.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_AHB_H_ +#define _TEGRA124_AHB_H_ + +#include <asm/arch-tegra/tegra1x4_ahb.h> + +#endif /* _TEGRA124_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h new file mode 100644 index 0000000..79a04a4 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -0,0 +1,496 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 clock PLL tables */ + +#ifndef _TEGRA124_CLOCK_TABLES_H_ +#define _TEGRA124_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SOC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + + CLOCK_ID_COUNT, /* number of PLLs */ + + /* + * These are clock ids that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 (DEVICES_L) */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_ISPB, + PERIPH_ID_RESERVED4, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_RESERVED13, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TCW, + PERIPH_ID_PWM, + PERIPH_ID_I2S2, + PERIPH_ID_RESERVED19, + PERIPH_ID_VI, + PERIPH_ID_RESERVED21, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S0, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 (DEVICES_H) */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_RESERVED36, + PERIPH_ID_STAT_MON, + PERIPH_ID_RESERVED38, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_I2C5, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_RESERVED53, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_MIPI_CAL, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_RESERVED60, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 (DEVICES_U) */ + PERIPH_ID_RESERVED64, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_LA, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, + + /* 88 */ + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_XUSB_DEV, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_V_RESERVED2, + PERIPH_ID_MSELECT, + PERIPH_ID_V_RESERVED4, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_I2C4, + + /* 104 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_HDA2CODEC2X, + + /* 112 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, + PERIPH_ID_ACTMON, + + /* 120 */ + PERIPH_ID_EXTPERIPH1, + PERIPH_ID_EXTPERIPH2, + PERIPH_ID_EXTPERIPH3, + PERIPH_ID_OOB, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, + + /* 136 */ + PERIPH_ID_CEC, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, + + /* 144 */ + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_DDS, + PERIPH_ID_W_RESERVED23, + + /* 152 */ + PERIPH_ID_DP2, + PERIPH_ID_AMX0, + PERIPH_ID_ADX0, + PERIPH_ID_DVFS, + PERIPH_ID_XUSB_SS, + PERIPH_ID_W_RESERVED29, + PERIPH_ID_W_RESERVED30, + PERIPH_ID_W_RESERVED31, + + PERIPH_ID_X_FIRST, + /* X word: 31:0 */ + PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, + PERIPH_ID_X_RESERVED1, + PERIPH_ID_X_RESERVED2, + PERIPH_ID_X_RESERVED3, + PERIPH_ID_CAM_MCLK, + PERIPH_ID_CAM_MCLK2, + PERIPH_ID_I2C6, + PERIPH_ID_X_RESERVED7, + + /* 168 */ + PERIPH_ID_X_RESERVED8, + PERIPH_ID_X_RESERVED9, + PERIPH_ID_X_RESERVED10, + PERIPH_ID_VIM2_CLK, + PERIPH_ID_X_RESERVED12, + PERIPH_ID_X_RESERVED13, + PERIPH_ID_EMC_DLL, + PERIPH_ID_X_RESERVED15, + + /* 176 */ + PERIPH_ID_HDMI_AUDIO, + PERIPH_ID_CLK72MHZ, + PERIPH_ID_VIC, + PERIPH_ID_X_RESERVED19, + PERIPH_ID_ADX1, + PERIPH_ID_DPAUX, + PERIPH_ID_SOR0, + PERIPH_ID_X_RESERVED23, + + /* 184 */ + PERIPH_ID_GPU, + PERIPH_ID_AMX1, + PERIPH_ID_X_RESERVED26, + PERIPH_ID_X_RESERVED27, + PERIPH_ID_X_RESERVED28, + PERIPH_ID_X_RESERVED29, + PERIPH_ID_X_RESERVED30, + PERIPH_ID_X_RESERVED31, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S1, + PERIPHC_I2S2, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_I2C5, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_10h, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_18h, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_1Bh, + PERIPHC_1Ch, + PERIPHC_HSI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_22h, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_25h, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S0, + PERIPHC_DTV, + + /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ + PERIPHC_40h = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S3, + PERIPHC_I2S4, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x48 */ + PERIPHC_AUDIO, + PERIPHC_49h, + PERIPHC_DAM0, + PERIPHC_DAM1, + PERIPHC_DAM2, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x50 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_52h, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, /* 0x428 */ + PERIPHC_5fh, + + PERIPHC_X_FIRST, + /* 0x60 */ + PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ + PERIPHC_XUSB_FALCON, + PERIPHC_XUSB_FS, + PERIPHC_XUSB_CORE_DEV, + PERIPHC_XUSB_SS, + PERIPHC_CILAB, + PERIPHC_CILCD, + PERIPHC_CILE, + + /* 0x68 */ + PERIPHC_DSIA_LP, + PERIPHC_DSIB_LP, + PERIPHC_ENTROPY, + PERIPHC_DVFS_REF, + PERIPHC_DVFS_SOC, + PERIPHC_TRACECLKIN, + PERIPHC_ADX0, + PERIPHC_AMX0, + + /* 0x70 */ + PERIPHC_EMC_LATENCY, + PERIPHC_SOC_THERM, + PERIPHC_72h, + PERIPHC_73h, + PERIPHC_74h, + PERIPHC_75h, + PERIPHC_VI_SENSOR2, + PERIPHC_I2C6, + + /* 0x78 */ + PERIPHC_78h, + PERIPHC_EMC_DLL, + PERIPHC_HDMI_AUDIO, + PERIPHC_CLK72MHZ, + PERIPHC_ADX1, + PERIPHC_AMX1, + PERIPHC_VIC, + PERIPHC_7fh, + + PERIPHC_COUNT, + + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA124_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h new file mode 100644 index 0000000..8298133 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 clock control functions */ + +#ifndef _TEGRA124_CLOCK_H_ +#define _TEGRA124_CLOCK_H_ + +#include <asm/arch-tegra/tegra1x4_clock.h> + +#endif /* _TEGRA124_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/emc.h b/arch/arm/include/asm/arch-tegra124/emc.h new file mode 100644 index 0000000..eb4a7c9 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/emc.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_EMC_H_ +#define _TEGRA124_EMC_H_ + +#include <asm/arch-tegra/tegra1x4_emc.h> + +#endif /* _TEGRA124_EMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h new file mode 100644 index 0000000..41758d8 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_FLOW_H_ +#define _TEGRA124_FLOW_H_ + +#include <asm/arch-tegra/tegra1x4_flow.h> + +#endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h new file mode 100644 index 0000000..df94d13 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/funcmux.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra124 high-level function multiplexing */ + +#ifndef _TEGRA124_FUNCMUX_H_ +#define _TEGRA124_FUNCMUX_H_ + +#include <asm/arch-tegra/funcmux.h> + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_KBC = 0, + FUNCMUX_UART4_GPIO = 0, +}; +#endif /* _TEGRA124_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/fuse.h b/arch/arm/include/asm/arch-tegra124/fuse.h new file mode 100644 index 0000000..de3ad6f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/fuse.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_FUSE_H_ +#define _TEGRA124_FUSE_H_ + +#include <asm/arch-tegra/tegra1x4_fuse.h> + +#endif /* _TEGRA124_FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h new file mode 100644 index 0000000..bb8ef45 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_GP_PADCTRL_H_ +#define _TEGRA124_GP_PADCTRL_H_ + +#include <asm/arch-tegra/tegra1x4_gp_padctrl.h> + +#endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h new file mode 100644 index 0000000..1a6dcb8 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/gpio.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_GPIO_H_ +#define _TEGRA124_GPIO_H_ + +/* + * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include <asm/arch-tegra/gpio.h> + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +enum gpio_pin { + GPIO_PA0 = 0, /* pin 0 */ + GPIO_PA1, + GPIO_PA2, + GPIO_PA3, + GPIO_PA4, + GPIO_PA5, + GPIO_PA6, + GPIO_PA7, + GPIO_PB0, /* pin 8 */ + GPIO_PB1, + GPIO_PB2, + GPIO_PB3, + GPIO_PB4, + GPIO_PB5, + GPIO_PB6, + GPIO_PB7, + GPIO_PC0, /* pin 16 */ + GPIO_PC1, + GPIO_PC2, + GPIO_PC3, + GPIO_PC4, + GPIO_PC5, + GPIO_PC6, + GPIO_PC7, + GPIO_PD0, /* pin 24 */ + GPIO_PD1, + GPIO_PD2, + GPIO_PD3, + GPIO_PD4, + GPIO_PD5, + GPIO_PD6, + GPIO_PD7, + GPIO_PE0, /* pin 32 */ + GPIO_PE1, + GPIO_PE2, + GPIO_PE3, + GPIO_PE4, + GPIO_PE5, + GPIO_PE6, + GPIO_PE7, + GPIO_PF0, /* pin 40 */ + GPIO_PF1, + GPIO_PF2, + GPIO_PF3, + GPIO_PF4, + GPIO_PF5, + GPIO_PF6, + GPIO_PF7, + GPIO_PG0, /* pin 48 */ + GPIO_PG1, + GPIO_PG2, + GPIO_PG3, + GPIO_PG4, + GPIO_PG5, + GPIO_PG6, + GPIO_PG7, + GPIO_PH0, /* pin 56 */ + GPIO_PH1, + GPIO_PH2, + GPIO_PH3, + GPIO_PH4, + GPIO_PH5, + GPIO_PH6, + GPIO_PH7, + GPIO_PI0, /* pin 64 */ + GPIO_PI1, + GPIO_PI2, + GPIO_PI3, + GPIO_PI4, + GPIO_PI5, + GPIO_PI6, + GPIO_PI7, + GPIO_PJ0, /* pin 72 */ + GPIO_PJ1, + GPIO_PJ2, + GPIO_PJ3, + GPIO_PJ4, + GPIO_PJ5, + GPIO_PJ6, + GPIO_PJ7, + GPIO_PK0, /* pin 80 */ + GPIO_PK1, + GPIO_PK2, + GPIO_PK3, + GPIO_PK4, + GPIO_PK5, + GPIO_PK6, + GPIO_PK7, + GPIO_PL0, /* pin 88 */ + GPIO_PL1, + GPIO_PL2, + GPIO_PL3, + GPIO_PL4, + GPIO_PL5, + GPIO_PL6, + GPIO_PL7, + GPIO_PM0, /* pin 96 */ + GPIO_PM1, + GPIO_PM2, + GPIO_PM3, + GPIO_PM4, + GPIO_PM5, + GPIO_PM6, + GPIO_PM7, + GPIO_PN0, /* pin 104 */ + GPIO_PN1, + GPIO_PN2, + GPIO_PN3, + GPIO_PN4, + GPIO_PN5, + GPIO_PN6, + GPIO_PN7, + GPIO_PO0, /* pin 112 */ + GPIO_PO1, + GPIO_PO2, + GPIO_PO3, + GPIO_PO4, + GPIO_PO5, + GPIO_PO6, + GPIO_PO7, + GPIO_PP0, /* pin 120 */ + GPIO_PP1, + GPIO_PP2, + GPIO_PP3, + GPIO_PP4, + GPIO_PP5, + GPIO_PP6, + GPIO_PP7, + GPIO_PQ0, /* pin 128 */ + GPIO_PQ1, + GPIO_PQ2, + GPIO_PQ3, + GPIO_PQ4, + GPIO_PQ5, + GPIO_PQ6, + GPIO_PQ7, + GPIO_PR0, /* pin 136 */ + GPIO_PR1, + GPIO_PR2, + GPIO_PR3, + GPIO_PR4, + GPIO_PR5, + GPIO_PR6, + GPIO_PR7, + GPIO_PS0, /* pin 144 */ + GPIO_PS1, + GPIO_PS2, + GPIO_PS3, + GPIO_PS4, + GPIO_PS5, + GPIO_PS6, + GPIO_PS7, + GPIO_PT0, /* pin 152 */ + GPIO_PT1, + GPIO_PT2, + GPIO_PT3, + GPIO_PT4, + GPIO_PT5, + GPIO_PT6, + GPIO_PT7, + GPIO_PU0, /* pin 160 */ + GPIO_PU1, + GPIO_PU2, + GPIO_PU3, + GPIO_PU4, + GPIO_PU5, + GPIO_PU6, + GPIO_PU7, + GPIO_PV0, /* pin 168 */ + GPIO_PV1, + GPIO_PV2, + GPIO_PV3, + GPIO_PV4, + GPIO_PV5, + GPIO_PV6, + GPIO_PV7, + GPIO_PW0, /* pin 176 */ + GPIO_PW1, + GPIO_PW2, + GPIO_PW3, + GPIO_PW4, + GPIO_PW5, + GPIO_PW6, + GPIO_PW7, + GPIO_PX0, /* pin 184 */ + GPIO_PX1, + GPIO_PX2, + GPIO_PX3, + GPIO_PX4, + GPIO_PX5, + GPIO_PX6, + GPIO_PX7, + GPIO_PY0, /* pin 192 */ + GPIO_PY1, + GPIO_PY2, + GPIO_PY3, + GPIO_PY4, + GPIO_PY5, + GPIO_PY6, + GPIO_PY7, + GPIO_PZ0, /* pin 200 */ + GPIO_PZ1, + GPIO_PZ2, + GPIO_PZ3, + GPIO_PZ4, + GPIO_PZ5, + GPIO_PZ6, + GPIO_PZ7, + GPIO_PAA0, /* pin 208 */ + GPIO_PAA1, + GPIO_PAA2, + GPIO_PAA3, + GPIO_PAA4, + GPIO_PAA5, + GPIO_PAA6, + GPIO_PAA7, + GPIO_PBB0, /* pin 216 */ + GPIO_PBB1, + GPIO_PBB2, + GPIO_PBB3, + GPIO_PBB4, + GPIO_PBB5, + GPIO_PBB6, + GPIO_PBB7, + GPIO_PCC0, /* pin 224 */ + GPIO_PCC1, + GPIO_PCC2, + GPIO_PCC3, + GPIO_PCC4, + GPIO_PCC5, + GPIO_PCC6, + GPIO_PCC7, + GPIO_PDD0, /* pin 232 */ + GPIO_PDD1, + GPIO_PDD2, + GPIO_PDD3, + GPIO_PDD4, + GPIO_PDD5, + GPIO_PDD6, + GPIO_PDD7, + GPIO_PEE0, /* pin 240 */ + GPIO_PEE1, + GPIO_PEE2, + GPIO_PEE3, + GPIO_PEE4, + GPIO_PEE5, + GPIO_PEE6, + GPIO_PEE7, + GPIO_PFF0, /* pin 248 */ + GPIO_PFF1, + GPIO_PFF2, + GPIO_PFF3, + GPIO_PFF4, + GPIO_PFF5, + GPIO_PFF6, + GPIO_PFF7, /* pin 255 */ +}; + +#endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h new file mode 100644 index 0000000..faaad91 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/hardware.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_HARDWARE_H_ +#define _TEGRA124_HARDWARE_H_ + +/* + * Include Tegra-specific hardware definitions + * Nothing needed currently for T124 + */ + +#endif /* _TEGRA124_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h new file mode 100644 index 0000000..1317148 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -0,0 +1,618 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_PINMUX_H_ +#define _TEGRA124_PINMUX_H_ + +/* + * Pin groups which we adjust. There are three basic attributes of each pin + * group which use this enum: + * + * - function + * - pullup / pulldown + * - tristate or normal + */ +enum pmux_pingrp { + PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ + PINGRP_ULPI_DATA1, + PINGRP_ULPI_DATA2, + PINGRP_ULPI_DATA3, + PINGRP_ULPI_DATA4, + PINGRP_ULPI_DATA5, + PINGRP_ULPI_DATA6, + PINGRP_ULPI_DATA7, + PINGRP_ULPI_CLK, + PINGRP_ULPI_DIR, + PINGRP_ULPI_NXT, + PINGRP_ULPI_STP, + PINGRP_DAP3_FS, + PINGRP_DAP3_DIN, + PINGRP_DAP3_DOUT, + PINGRP_DAP3_SCLK, + PINGRP_GPIO_PV0, + PINGRP_GPIO_PV1, + PINGRP_SDMMC1_CLK, + PINGRP_SDMMC1_CMD, + PINGRP_SDMMC1_DAT3, + PINGRP_SDMMC1_DAT2, + PINGRP_SDMMC1_DAT1, + PINGRP_SDMMC1_DAT0, + PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3, + PINGRP_CLK2_REQ, + PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41, + PINGRP_DDC_SCL, + PINGRP_DDC_SDA, + PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19, + PINGRP_UART2_TXD, + PINGRP_UART2_RTS_N, + PINGRP_UART2_CTS_N, + PINGRP_UART3_TXD, + PINGRP_UART3_RXD, + PINGRP_UART3_CTS_N, + PINGRP_UART3_RTS_N, + PINGRP_GPIO_PU0, + PINGRP_GPIO_PU1, + PINGRP_GPIO_PU2, + PINGRP_GPIO_PU3, + PINGRP_GPIO_PU4, + PINGRP_GPIO_PU5, + PINGRP_GPIO_PU6, + PINGRP_GEN1_I2C_SDA, + PINGRP_GEN1_I2C_SCL, + PINGRP_DAP4_FS, + PINGRP_DAP4_DIN, + PINGRP_DAP4_DOUT, + PINGRP_DAP4_SCLK, + PINGRP_CLK3_OUT, + PINGRP_CLK3_REQ, + /* Renamed on T124, from GMI_xx to GPIO_Pxx */ + PINGRP_GPIO_PC7, /* offset 0x31c0 */ + PINGRP_GPIO_PI5, + PINGRP_GPIO_PI7, + PINGRP_GPIO_PK0, + PINGRP_GPIO_PK1, + PINGRP_GPIO_PJ0, + PINGRP_GPIO_PJ2, + PINGRP_GPIO_PK3, + PINGRP_GPIO_PK4, + PINGRP_GPIO_PK2, + PINGRP_GPIO_PI3, + PINGRP_GPIO_PI6, + PINGRP_GPIO_PG0, + PINGRP_GPIO_PG1, + PINGRP_GPIO_PG2, + PINGRP_GPIO_PG3, + PINGRP_GPIO_PG4, + PINGRP_GPIO_PG5, + PINGRP_GPIO_PG6, + PINGRP_GPIO_PG7, + PINGRP_GPIO_PH0, + PINGRP_GPIO_PH1, + PINGRP_GPIO_PH2, + PINGRP_GPIO_PH3, + PINGRP_GPIO_PH4, + PINGRP_GPIO_PH5, + PINGRP_GPIO_PH6, + PINGRP_GPIO_PH7, + PINGRP_GPIO_PJ7, + PINGRP_GPIO_PB0, + PINGRP_GPIO_PB1, + PINGRP_GPIO_PK7, + PINGRP_GPIO_PI0, + PINGRP_GPIO_PI1, + PINGRP_GPIO_PI2, + PINGRP_GPIO_PI4, /* offset 0x324c */ + PINGRP_GEN2_I2C_SCL, + PINGRP_GEN2_I2C_SDA, + PINGRP_SDMMC4_CLK, + PINGRP_SDMMC4_CMD, + PINGRP_SDMMC4_DAT0, + PINGRP_SDMMC4_DAT1, + PINGRP_SDMMC4_DAT2, + PINGRP_SDMMC4_DAT3, + PINGRP_SDMMC4_DAT4, + PINGRP_SDMMC4_DAT5, + PINGRP_SDMMC4_DAT6, + PINGRP_SDMMC4_DAT7, + PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2, + PINGRP_GPIO_PCC1, + PINGRP_GPIO_PBB0, + PINGRP_CAM_I2C_SCL, + PINGRP_CAM_I2C_SDA, + PINGRP_GPIO_PBB3, + PINGRP_GPIO_PBB4, + PINGRP_GPIO_PBB5, + PINGRP_GPIO_PBB6, + PINGRP_GPIO_PBB7, + PINGRP_GPIO_PCC2, + PINGRP_JTAG_RTCK, + PINGRP_PWR_I2C_SCL, + PINGRP_PWR_I2C_SDA, + PINGRP_KB_ROW0, + PINGRP_KB_ROW1, + PINGRP_KB_ROW2, + PINGRP_KB_ROW3, + PINGRP_KB_ROW4, + PINGRP_KB_ROW5, + PINGRP_KB_ROW6, + PINGRP_KB_ROW7, + PINGRP_KB_ROW8, + PINGRP_KB_ROW9, + PINGRP_KB_ROW10, + PINGRP_KB_ROW11, + PINGRP_KB_ROW12, + PINGRP_KB_ROW13, + PINGRP_KB_ROW14, + PINGRP_KB_ROW15, + PINGRP_KB_COL0, /* offset 0x32fc */ + PINGRP_KB_COL1, + PINGRP_KB_COL2, + PINGRP_KB_COL3, + PINGRP_KB_COL4, + PINGRP_KB_COL5, + PINGRP_KB_COL6, + PINGRP_KB_COL7, + PINGRP_CLK_32K_OUT, + PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */ + PINGRP_CPU_PWR_REQ, + PINGRP_PWR_INT_N, + PINGRP_CLK_32K_IN, + PINGRP_OWR, + PINGRP_DAP1_FS, + PINGRP_DAP1_DIN, + PINGRP_DAP1_DOUT, + PINGRP_DAP1_SCLK, + PINGRP_CLK1_REQ, + PINGRP_CLK1_OUT, + PINGRP_SPDIF_IN, + PINGRP_SPDIF_OUT, + PINGRP_DAP2_FS, + PINGRP_DAP2_DIN, + PINGRP_DAP2_DOUT, + PINGRP_DAP2_SCLK, + PINGRP_DVFS_PWM, + PINGRP_GPIO_X1_AUD, + PINGRP_GPIO_X3_AUD, + PINGRP_DVFS_CLK, + PINGRP_GPIO_X4_AUD, + PINGRP_GPIO_X5_AUD, + PINGRP_GPIO_X6_AUD, + PINGRP_GPIO_X7_AUD, + PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3, + PINGRP_SDMMC3_CMD, + PINGRP_SDMMC3_DAT0, + PINGRP_SDMMC3_DAT1, + PINGRP_SDMMC3_DAT2, + PINGRP_SDMMC3_DAT3, + PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */ + PINGRP_PEX_L0_CLKREQ, + PINGRP_PEX_WAKE, + PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2, + PINGRP_PEX_L1_CLKREQ, + PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */ + PINGRP_SDMMC1_WP_N, + PINGRP_SDMMC3_CD_N, + PINGRP_GPIO_W2_AUD, + PINGRP_GPIO_W3_AUD, + PINGRP_USB_VBUS_EN0, + PINGRP_USB_VBUS_EN1, + PINGRP_SDMMC3_CLK_LB_IN, + PINGRP_SDMMC3_CLK_LB_OUT, + PINGRP_GMI_CLK_LB, + PINGRP_RESET_OUT_N, + PINGRP_KB_ROW16, /* offset 0x340c */ + PINGRP_KB_ROW17, + PINGRP_USB_VBUS_EN2, + PINGRP_GPIO_PFF2, + PINGRP_DP_HPD, /* last reg offset = 0x3430 */ + PINGRP_COUNT, +}; + +enum pdrive_pingrp { + PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ + PDRIVE_PINGROUP_AO2, + PDRIVE_PINGROUP_AT1, + PDRIVE_PINGROUP_AT2, + PDRIVE_PINGROUP_AT3, + PDRIVE_PINGROUP_AT4, + PDRIVE_PINGROUP_AT5, + PDRIVE_PINGROUP_CDEV1, + PDRIVE_PINGROUP_CDEV2, + PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */ + PDRIVE_PINGROUP_DAP2, + PDRIVE_PINGROUP_DAP3, + PDRIVE_PINGROUP_DAP4, + PDRIVE_PINGROUP_DBG, + PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */ + PDRIVE_PINGROUP_SPI, + PDRIVE_PINGROUP_UAA, + PDRIVE_PINGROUP_UAB, + PDRIVE_PINGROUP_UART2, + PDRIVE_PINGROUP_UART3, + PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */ + PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */ + PDRIVE_PINGROUP_GMA, + PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */ + PDRIVE_PINGROUP_GMF, + PDRIVE_PINGROUP_GMG, + PDRIVE_PINGROUP_GMH, + PDRIVE_PINGROUP_OWR, + PDRIVE_PINGROUP_UAD, + PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ + PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ + PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */ + PDRIVE_PINGROUP_DAP5, + PDRIVE_PINGROUP_VBUS, + PDRIVE_PINGROUP_AO3, + PDRIVE_PINGROUP_HVC, + PDRIVE_PINGROUP_SDIO4, + PDRIVE_PINGROUP_AO0, + PDRIVE_PINGROUP_COUNT, +}; + +/* + * Functions which can be assigned to each of the pin groups. The values here + * bear no relation to the values programmed into pinmux registers and are + * purely a convenience. The translation is done through a table search. + */ +enum pmux_func { + PMUX_FUNC_AHB_CLK, + PMUX_FUNC_APB_CLK, + PMUX_FUNC_AUDIO_SYNC, + PMUX_FUNC_CRT, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, + PMUX_FUNC_DAP3, + PMUX_FUNC_DAP4, + PMUX_FUNC_DAP5, + PMUX_FUNC_DISPA, + PMUX_FUNC_DISPB, + PMUX_FUNC_EMC_TEST0_DLL, + PMUX_FUNC_EMC_TEST1_DLL, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_INT, + PMUX_FUNC_HDMI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_IDE, + PMUX_FUNC_KBC, + PMUX_FUNC_MIO, + PMUX_FUNC_MIPI_HS, + PMUX_FUNC_NAND, + PMUX_FUNC_OSC, + PMUX_FUNC_OWR, + PMUX_FUNC_PCIE, + PMUX_FUNC_PLLA_OUT, + PMUX_FUNC_PLLC_OUT1, + PMUX_FUNC_PLLM_OUT1, + PMUX_FUNC_PLLP_OUT2, + PMUX_FUNC_PLLP_OUT3, + PMUX_FUNC_PLLP_OUT4, + PMUX_FUNC_PWM, + PMUX_FUNC_PWR_INTR, + PMUX_FUNC_PWR_ON, + PMUX_FUNC_RTCK, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SFLASH, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI2_ALT, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_TRACE, + PMUX_FUNC_TWC, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_UARTE, + PMUX_FUNC_ULPI, + PMUX_FUNC_VI, + PMUX_FUNC_VI_SENSOR_CLK, + PMUX_FUNC_XIO, + /* End of Tegra2 MUX selectors */ + PMUX_FUNC_BLINK, + PMUX_FUNC_CEC, + PMUX_FUNC_CLK12, + PMUX_FUNC_DAP, + PMUX_FUNC_DAPSDMMC2, + PMUX_FUNC_DDR, + PMUX_FUNC_DEV3, + PMUX_FUNC_DTV, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT2, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_EMC_DLL, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HSI, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2C5, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_NAND_ALT, + PMUX_FUNC_POPSDIO4, + PMUX_FUNC_POPSDMMC4, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_SATA, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYSCLK, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + /* End of Tegra3 MUX selectors */ + PMUX_FUNC_USB, + PMUX_FUNC_SOC, + PMUX_FUNC_CPU, + PMUX_FUNC_CLK, + PMUX_FUNC_PWRON, + PMUX_FUNC_PMI, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_RESET_OUT_N, + /* End of Tegra114 MUX selectors */ + + PMUX_FUNC_SAFE, + PMUX_FUNC_MAX, + + PMUX_FUNC_INVALID = 0x4000, + PMUX_FUNC_RSVD1 = 0x8000, + PMUX_FUNC_RSVD2 = 0x8001, + PMUX_FUNC_RSVD3 = 0x8002, + PMUX_FUNC_RSVD4 = 0x8003, +}; + +/* return 1 if a pmux_func is in range */ +#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \ + || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) + +/* return 1 if a pingrp is in range */ +#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) + +/* The pullup/pulldown state of a pin group */ +enum pmux_pull { + PMUX_PULL_NORMAL = 0, + PMUX_PULL_DOWN, + PMUX_PULL_UP, +}; +/* return 1 if a pin_pupd_is in range */ +#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ + ((pupd) <= PMUX_PULL_UP)) + +/* Defines whether a pin group is tristated or in normal operation */ +enum pmux_tristate { + PMUX_TRI_NORMAL = 0, + PMUX_TRI_TRISTATE = 1, +}; +/* return 1 if a pin_tristate_is in range */ +#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \ + && ((tristate) <= PMUX_TRI_TRISTATE)) + +enum pmux_pin_io { + PMUX_PIN_OUTPUT = 0, + PMUX_PIN_INPUT = 1, + PMUX_PIN_NONE, +}; +/* return 1 if a pin_io_is in range */ +#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ + ((io) <= PMUX_PIN_INPUT)) + +enum pmux_pin_lock { + PMUX_PIN_LOCK_DEFAULT = 0, + PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_ENABLE, +}; +/* return 1 if a pin_lock is in range */ +#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ + ((lock) <= PMUX_PIN_LOCK_ENABLE)) + +enum pmux_pin_od { + PMUX_PIN_OD_DEFAULT = 0, + PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_ENABLE, +}; +/* return 1 if a pin_od is in range */ +#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ + ((od) <= PMUX_PIN_OD_ENABLE)) + +enum pmux_pin_ioreset { + PMUX_PIN_IO_RESET_DEFAULT = 0, + PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_ENABLE, +}; +/* return 1 if a pin_ioreset_is in range */ +#define pmux_pin_ioreset_isvalid(ioreset) \ + (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ + ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) + +enum pmux_pin_rcv_sel { + PMUX_PIN_RCV_SEL_DEFAULT = 0, + PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_HIGH, +}; +/* return 1 if a pin_rcv_sel_is in range */ +#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ + (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ + ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) + +/* Available power domains used by pin groups */ +enum pmux_vddio { + PMUX_VDDIO_BB = 0, + PMUX_VDDIO_LCD, + PMUX_VDDIO_VI, + PMUX_VDDIO_UART, + PMUX_VDDIO_DDR, + PMUX_VDDIO_NAND, + PMUX_VDDIO_SYS, + PMUX_VDDIO_AUDIO, + PMUX_VDDIO_SD, + PMUX_VDDIO_CAM, + PMUX_VDDIO_GMI, + PMUX_VDDIO_PEXCTL, + PMUX_VDDIO_SDMMC1, + PMUX_VDDIO_SDMMC3, + PMUX_VDDIO_SDMMC4, + + PMUX_VDDIO_NONE +}; + +#define PGRP_SLWF_NONE -1 +#define PGRP_SLWF_MAX 3 +#define PGRP_SLWR_NONE PGRP_SLWF_NONE +#define PGRP_SLWR_MAX PGRP_SLWF_MAX + +#define PGRP_DRVUP_NONE -1 +#define PGRP_DRVUP_MAX 127 +#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE +#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX + +#define PGRP_SCHMT_NONE -1 +#define PGRP_HSM_NONE PGRP_SCHMT_NONE + +/* return 1 if a padgrp is in range */ +#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) + +/* return 1 if a slew-rate rising/falling edge value is in range */ +#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \ + (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))) + +/* return 1 if a driver output pull-up/down strength code value is in range */ +#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \ + (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))) + +/* return 1 if a low-power mode value is in range */ +#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \ + (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))) + +/* Defines a pin group cfg's low-power mode select */ +enum pgrp_lpmd { + PGRP_LPMD_X8 = 0, + PGRP_LPMD_X4, + PGRP_LPMD_X2, + PGRP_LPMD_X, + PGRP_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pgrp_schmt { + PGRP_SCHMT_DISABLE = 0, + PGRP_SCHMT_ENABLE = 1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pgrp_hsm { + PGRP_HSM_DISABLE = 0, + PGRP_HSM_ENABLE = 1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct padctrl_config { + enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ + int slwf; /* falling edge slew */ + int slwr; /* rising edge slew */ + int drvup; /* pull-up drive strength */ + int drvdn; /* pull-down drive strength */ + enum pgrp_lpmd lpmd; /* low-power mode selection */ + enum pgrp_schmt schmt; /* schmidt enable */ + enum pgrp_hsm hsm; /* high-speed mode enable */ +}; + +/* t124 pin drive group and pin mux registers */ +#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) +#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ + PDRIVE_PINGROUP_COUNT) +struct pmux_tri_ctlr { + uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */ + uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ + + uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ + + uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ + uint pmt_reserved5[PMUX_OFFSET]; + uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ +}; + +/* + * This defines the configuration for a pin, including the function assigned, + * pull up/down settings and tristate settings. Having set up one of these + * you can call pinmux_config_pingroup() to configure a pin in one step. Also + * available is pinmux_config_table() to configure a list of pins. + */ +struct pingroup_config { + enum pmux_pingrp pingroup; /* pin group PINGRP_... */ + enum pmux_func func; /* function to assign FUNC_... */ + enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ + enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ + enum pmux_pin_io io; /* input or output PMUX_PIN_... */ + enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ + enum pmux_pin_od od; /* open-drain or push-pull driver */ + enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ + /* VIL/VIH receivers */ +}; + +/* Set a pin group to tristate */ +void pinmux_tristate_enable(enum pmux_pingrp pin); + +/* Set a pin group to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pingrp pin); + +/* Set the pull up/down feature for a pin group */ +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); + +/* Set the mux function for a pin group */ +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); + +/* Set the complete configuration for a pin group */ +void pinmux_config_pingroup(struct pingroup_config *config); + +/* Set a pin group to tristate or normal */ +void pinmux_set_tristate(enum pmux_pingrp pin, int enable); + +/* Set a pin group as input or output */ +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); + +/** + * Configure a list of pin groups + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_table(struct pingroup_config *config, int len); + +/* Set a group of pins from a table */ +void pinmux_init(void); + +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void padgrp_config_table(struct padctrl_config *config, int len); + +#endif /* _TEGRA124_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pmc.h b/arch/arm/include/asm/arch-tegra124/pmc.h new file mode 100644 index 0000000..fa6ef10 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pmc.h @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_PMC_H_ +#define _TEGRA124_PMC_H_ + +/* Power Management Controller (APBDEV_PMC_) registers */ +struct pmc_ctlr { + uint pmc_cntrl; /* _CNTRL_0, offset 00 */ + uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ + uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ + uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ + uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ + uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ + uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ + uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ + uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ + uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ + uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ + uint pmc_clamp_status; /* _PMC_CLAMP_STATUS_0, offset 2C */ + uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ + uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ + uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ + uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ + uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ + uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ + uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */ + uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ + + uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */ + uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */ + uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */ + uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */ + uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */ + uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */ + uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */ + uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */ + uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */ + uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */ + uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */ + uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */ + uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */ + uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */ + uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */ + uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */ + uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */ + uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */ + uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */ + uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */ + uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */ + uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */ + uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */ + uint pmc_scratch23; /* _SCRATCH23_0, offset AC */ + + uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ + uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ + uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ + uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ + uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ + uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ + + uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ + uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ + uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */ + uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ + uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ + uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ + uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ + uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ + uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ + uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ + uint pmc_usb_ao; /* _USB_AO_0, offset F0 */ + uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ + uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ + + uint pmc_scratch24; /* _SCRATCH24_0, offset FC */ + uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */ + uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */ + uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */ + uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */ + uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */ + uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */ + uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */ + uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */ + uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */ + uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */ + uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */ + uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */ + uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */ + uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */ + uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */ + uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */ + uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */ + uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */ + + uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ + uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ + uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ + uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ + uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ + uint pmc_gate; /* _GATE_0, offset 15C */ + uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ + uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ + uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ + uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ + uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ + uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ + uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ + uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ + uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ + uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ + uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ + uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ + uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ + uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ + uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ + uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ + uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ + uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ + uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ + uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ + uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ + uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ + uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ + uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ + uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ + uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ + uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ + uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ + + uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ + uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ + uint pmc_reserved0; /* _RESERVED, offset 1D8 */ + uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ + uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ + uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ + uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ + uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ + uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ + uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ + uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ + uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ + + uint pmc_todo_0[9]; /* offset 200-220 */ + uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ + uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ + uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */ + uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */ + uint pmc_scratch45; + uint pmc_scratch46; + uint pmc_scratch47; + uint pmc_scratch48; + uint pmc_scratch49; + uint pmc_scratch50; + uint pmc_scratch51; + uint pmc_scratch52; + uint pmc_scratch53; + uint pmc_scratch54; + uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */ + uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */ + uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */ + uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */ + uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ + uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ + uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ + uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ + uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ + uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ + uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ + uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ + uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ + uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ + uint pmc_secure_scratch9; + uint pmc_secure_scratch10; + uint pmc_secure_scratch11; + uint pmc_secure_scratch12; + uint pmc_secure_scratch13; + uint pmc_secure_scratch14; + uint pmc_secure_scratch15; + uint pmc_secure_scratch16; + uint pmc_secure_scratch17; + uint pmc_secure_scratch18; + uint pmc_secure_scratch19; + uint pmc_secure_scratch20; + uint pmc_secure_scratch21; + uint pmc_secure_scratch22; + uint pmc_secure_scratch23; + uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */ + uint pmc_secure_scratch25; + uint pmc_secure_scratch26; + uint pmc_secure_scratch27; + uint pmc_secure_scratch28; + uint pmc_secure_scratch29; + uint pmc_secure_scratch30; + uint pmc_secure_scratch31; + uint pmc_secure_scratch32; + uint pmc_secure_scratch33; + uint pmc_secure_scratch34; + uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */ + + uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */ + uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */ + uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */ + uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */ + uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */ + uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */ + uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */ + + uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */ + uint pmc_scratch57; + uint pmc_scratch58; + uint pmc_scratch59; + uint pmc_scratch60; + uint pmc_scratch61; + uint pmc_scratch62; + uint pmc_scratch63; + uint pmc_scratch64; + uint pmc_scratch65; + uint pmc_scratch66; + uint pmc_scratch67; + uint pmc_scratch68; + uint pmc_scratch69; + uint pmc_scratch70; + uint pmc_scratch71; + uint pmc_scratch72; + uint pmc_scratch73; + uint pmc_scratch74; + uint pmc_scratch75; + uint pmc_scratch76; + uint pmc_scratch77; + uint pmc_scratch78; + uint pmc_scratch79; + uint pmc_scratch80; + uint pmc_scratch81; + uint pmc_scratch82; + uint pmc_scratch83; + uint pmc_scratch84; + uint pmc_scratch85; + uint pmc_scratch86; + uint pmc_scratch87; + uint pmc_scratch88; + uint pmc_scratch89; + uint pmc_scratch90; + uint pmc_scratch91; + uint pmc_scratch92; + uint pmc_scratch93; + uint pmc_scratch94; + uint pmc_scratch95; + uint pmc_scratch96; + uint pmc_scratch97; + uint pmc_scratch98; + uint pmc_scratch99; + uint pmc_scratch100; + uint pmc_scratch101; + uint pmc_scratch102; + uint pmc_scratch103; + uint pmc_scratch104; + uint pmc_scratch105; + uint pmc_scratch106; + uint pmc_scratch107; + uint pmc_scratch108; + uint pmc_scratch109; + uint pmc_scratch110; + uint pmc_scratch111; + uint pmc_scratch112; + uint pmc_scratch113; + uint pmc_scratch114; + uint pmc_scratch115; + uint pmc_scratch116; + uint pmc_scratch117; + uint pmc_scratch118; + uint pmc_scratch119; + uint pmc_scratch1_eco; /* offset 700 */ +}; + +#define CPU_PWRED 1 +#define CPU_CLMP 1 + +#define PARTID_CP 0xFFFFFFF8 +#define START_CP (1 << 8) + +#define CPUPWRREQ_OE (1 << 16) +#define CPUPWRREQ_POL (1 << 15) + +#define CRAILID (0) +#define CE0ID (14) +#define C0NCID (15) +#define CRAIL (1 << CRAILID) +#define CE0 (1 << CE0ID) +#define C0NC (1 << C0NCID) + +#define PMC_XOFS_SHIFT 1 +#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) + +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 2 +#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) +#define MULT_1 0 +#define MULT_2 1 +#define MULT_4 2 +#define MULT_8 3 + +#define AMAP_WRITE_SHIFT 20 +#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) + +/* SEC_DISABLE_0, 0x04 */ +#define SEC_DISABLE_WRITE0_ON (1 << 4) +#define SEC_DISABLE_READ0_ON (1 << 5) +#define SEC_DISABLE_WRITE1_ON (1 << 6) +#define SEC_DISABLE_READ1_ON (1 << 7) +#define SEC_DISABLE_WRITE2_ON (1 << 8) +#define SEC_DISABLE_READ2_ON (1 << 9) +#define SEC_DISABLE_WRITE3_ON (1 << 10) +#define SEC_DISABLE_READ3_ON (1 << 11) +#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) + +/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ +#define PWRGATE_TOGGLE_PARTID_CRAIL 0 +#define PWRGATE_TOGGLE_PARTID_TD 1 +#define PWRGATE_TOGGLE_PARTID_VE 2 +#define PWRGATE_TOGGLE_PARTID_VDE 4 +#define PWRGATE_TOGGLE_PARTID_L2C 5 +#define PWRGATE_TOGGLE_PARTID_MPE 6 +#define PWRGATE_TOGGLE_PARTID_HEG 7 +#define PWRGATE_TOGGLE_PARTID_CE1 9 +#define PWRGATE_TOGGLE_PARTID_CE2 10 +#define PWRGATE_TOGGLE_PARTID_CE3 11 +#define PWRGATE_TOGGLE_PARTID_CELP 12 +#define PWRGATE_TOGGLE_PARTID_CE0 14 +#define PWRGATE_TOGGLE_PARTID_C0NC 15 +#define PWRGATE_TOGGLE_PARTID_C1NC 16 +#define PWRGATE_TOGGLE_PARTID_DIS 18 +#define PWRGATE_TOGGLE_PARTID_DISB 19 +#define PWRGATE_TOGGLE_PARTID_XUSBA 20 +#define PWRGATE_TOGGLE_PARTID_XUSBB 21 +#define PWRGATE_TOGGLE_PARTID_XUSBC 22 +#define PWRGATE_TOGGLE_START (1 << 8) + +/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ +#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) +#define PWRGATE_STATUS_TD_ENABLE (1 << 1) +#define PWRGATE_STATUS_VE_ENABLE (1 << 2) +#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) +#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) +#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) +#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) +#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) +#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) +#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) +#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) +#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) +#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) +#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) +#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) +#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) +#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) +#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) +#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) + +/* APBDEV_PMC_CNTRL2_0 0x440 */ +#define HOLD_CKE_LOW_EN (1 << 12) + +#endif /* _TEGRA124_PMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h new file mode 100644 index 0000000..deb9244 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pmu.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_PMU_H_ +#define _TEGRA124_PMU_H_ + +#include <asm/arch-tegra/tegra1x4_pmu.h> + +#endif /* _TEGRA124_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h new file mode 100644 index 0000000..918124e --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/spl.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_SPL_H_ +#define _TEGRA124_SPL_H_ + +#include <asm/arch-tegra/spl.h> + +#endif /* TEGRA124_SPL_H */ diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h new file mode 100644 index 0000000..078ed9c --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/sysctr.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_SYSCTR_H_ +#define _TEGRA124_SYSCTR_H_ + +#include <asm/arch-tegra/tegra1x4_sysctr.h> + +#endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h new file mode 100644 index 0000000..feadd2f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/tegra.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_H_ +#define _TEGRA124_H_ + +#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T1x4 */ +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ +#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ + +#include <asm/arch-tegra/tegra.h> + +#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 +#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) + +#define TEGRA_USB1_BASE 0x7D000000 + +#endif /* _TEGRA124_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h new file mode 100644 index 0000000..806c4ac --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/usb.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_USB_H_ +#define _TEGRA124_USB_H_ + +#include <asm/arch-tegra/tegra1x4_usb.h> + +#endif /* _TEGRA124_USB_H_ */ -- 1.8.1.5

3 18

[U-Boot] [PATCH v2] Tegra114: Add support for more clock sources for T114 periphs
by Tom Warren 22 Jan '14

22 Jan '14

Some T114 peripherals can take up to 8 different clock sources (parents), including 4 new ones that don't exist on previous chips (PLLC2/C3/MEM2/SRC2). Expand clock/pll code/tables to support these additional bits/sources. Changes were made to some common code. Testing on T30/T20 showed no changes in periph clock sources/divisors. Also, peripheral clock sources that no longer exist on T114 were removed from the clock_periph_type table (CVE, TVDAC, etc.), and periphs that are gone or not needed in early init are no longer brought out of reset/enabled (FUSE, IRAMA/B/C/D, etc.). Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- v2: - Removed some periph enables/resets that are not needed for early init - Fixed an assert test for a divisor value (s/b >0, not >=0) - Remove some unused code arch/arm/cpu/arm720t/tegra114/cpu.c | 8 - arch/arm/cpu/tegra-common/clock.c | 21 +- arch/arm/cpu/tegra114-common/clock.c | 422 +++++++++++++--------- arch/arm/cpu/tegra30-common/clock.c | 6 - arch/arm/include/asm/arch-tegra/clk_rst.h | 3 + arch/arm/include/asm/arch-tegra/clock.h | 17 + arch/arm/include/asm/arch-tegra114/clock-tables.h | 178 +++++---- 7 files changed, 390 insertions(+), 265 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 8f7bce4..c8e54b6 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -152,18 +152,11 @@ void t114_init_clocks(void) clock_set_enable(PERIPH_ID_CACHE2, 1); clock_set_enable(PERIPH_ID_GPIO, 1); clock_set_enable(PERIPH_ID_TMR, 1); - clock_set_enable(PERIPH_ID_RTC, 1); clock_set_enable(PERIPH_ID_CPU, 1); clock_set_enable(PERIPH_ID_EMC, 1); clock_set_enable(PERIPH_ID_I2C5, 1); - clock_set_enable(PERIPH_ID_FUSE, 1); - clock_set_enable(PERIPH_ID_PMC, 1); clock_set_enable(PERIPH_ID_APBDMA, 1); clock_set_enable(PERIPH_ID_MEM, 1); - clock_set_enable(PERIPH_ID_IRAMA, 1); - clock_set_enable(PERIPH_ID_IRAMB, 1); - clock_set_enable(PERIPH_ID_IRAMC, 1); - clock_set_enable(PERIPH_ID_IRAMD, 1); clock_set_enable(PERIPH_ID_CORESIGHT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_EMC1, 1); @@ -192,7 +185,6 @@ void t114_init_clocks(void) reset_set_enable(PERIPH_ID_COP, 0); reset_set_enable(PERIPH_ID_EMC, 0); reset_set_enable(PERIPH_ID_I2C5, 0); - reset_set_enable(PERIPH_ID_FUSE, 0); reset_set_enable(PERIPH_ID_APBDMA, 0); reset_set_enable(PERIPH_ID_MEM, 0); reset_set_enable(PERIPH_ID_CORESIGHT, 0); diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 268fb91..62a2191 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -304,13 +304,24 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, /* work out the source clock and set it */ if (source < 0) return -1; - if (mux_bits == 4) { - clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, - source << OUT_CLK_SOURCE4_SHIFT); - } else { + + switch (mux_bits) { + case MASK_BITS_31_30: clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, source << OUT_CLK_SOURCE_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE3_MASK, + source << OUT_CLK_SOURCE3_SHIFT); + break; + + case MASK_BITS_29_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, + source << OUT_CLK_SOURCE4_SHIFT); + break; } + udelay(2); return 0; } @@ -332,7 +343,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, if (extra_div) *extra_div = xdiv; - assert(divider >= 0); + assert(divider > 0); if (adjust_periph_pll(periph_id, source, mux_bits, divider)) return -1U; debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate, diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index e9a1a80..0626bcd 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -46,13 +46,22 @@ enum clock_type_id { CLOCK_TYPE_MCPT, CLOCK_TYPE_PCM, CLOCK_TYPE_PCMT, - CLOCK_TYPE_PCMT16, CLOCK_TYPE_PDCT, CLOCK_TYPE_ACPT, CLOCK_TYPE_ASPTE, CLOCK_TYPE_PMDACD2T, CLOCK_TYPE_PCST, + CLOCK_TYPE_PC2CC3M, + CLOCK_TYPE_PC2CC3S_T, + CLOCK_TYPE_PC2CC3M_T, + CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ + CLOCK_TYPE_MC2CC3P_A, + CLOCK_TYPE_M, + CLOCK_TYPE_MCPTM2C2C3, + CLOCK_TYPE_PC2CC3T_S, + CLOCK_TYPE_AC2CC3P_TS2, + CLOCK_TYPE_COUNT, CLOCK_TYPE_NONE = -1, /* invalid clock type */ }; @@ -61,12 +70,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. @@ -92,9 +95,6 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_30}, - { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), - CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_31_30}, { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_30}, @@ -109,7 +109,45 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_29_28} + MASK_BITS_29_28}, + + /* Additional clock types on T114 */ + /* CLOCK_TYPE_PC2CC3M */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3S_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_MC2CC3P_A */ + { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_M */ + { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + /* CLOCK_TYPE_MCPTM2C2C3 */ + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3T_S */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_AC2CC3P_TS2 */ + { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), + MASK_BITS_31_29}, }; /* @@ -122,110 +160,120 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM), - TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), + TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), /* 0x08 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), /* 0x10 */ - TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA), + TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_G3D, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_G2D, CLOCK_TYPE_MC2CC3P_A), /* 0x18 */ - TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */ - TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_EPP, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_MPE, CLOCK_TYPE_M), + TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), /* 0x20 */ - TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT), + TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), + TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), /* 0x28 */ - TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), /* 0x30 */ - TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - - /* 0x38h */ /* Jumps to reg offset 0x3B0h */ - TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */ + TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), + + /* 0x38 */ + TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), + + /* 0x40 */ + TYPE(PERIPHC_G3D2, CLOCK_TYPE_MC2CC3P_A), /* start with 0x3b0 */ + TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), - /* 0x40 */ - TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */ + /* 0x48 */ + TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), - /* 0x48 */ + /* 0x50 */ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), - TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */ + TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - - /* 0x50 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */ + TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), + + /* 0x58 */ + TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), }; /* @@ -244,7 +292,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(COP), NONE(TRIGSYS), NONE(RESERVED3), - NONE(RTC), + NONE(RESERVED4), NONE(TMR), PERIPHC_UART1, PERIPHC_UART2, /* and vfir 0x68 */ @@ -252,7 +300,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 8 */ NONE(GPIO), PERIPHC_SDMMC2, - NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */ + PERIPHC_SPDIF_IN, PERIPHC_I2S1, PERIPHC_I2C1, PERIPHC_NDFLASH, @@ -291,7 +339,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 40 */ NONE(KFUSE), - NONE(SBC1), /* SBC1, 0x34, is this SPI1? */ + NONE(SBC1), /* SBC1, SPI1 */ PERIPHC_NOR, NONE(RESERVED43), PERIPHC_SBC2, @@ -301,16 +349,16 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 48 */ NONE(DSI), - PERIPHC_TVO, /* also CVE 0x40 */ - PERIPHC_MIPI, + NONE(RESERVED49), + PERIPHC_HSI, PERIPHC_HDMI, NONE(CSI), - PERIPHC_TVDAC, + NONE(RESERVED53), PERIPHC_I2C2, PERIPHC_UART3, /* 56 */ - NONE(RESERVED56), + NONE(MIPI_CAL), PERIPHC_EMC, NONE(USB2), NONE(USB3), @@ -320,7 +368,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(BSEV), /* Upper word 95:64 */ - PERIPHC_SPEEDO, + NONE(RESERVED64), PERIPHC_UART4, PERIPHC_UART5, PERIPHC_I2C3, @@ -335,41 +383,41 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(PCIEXCLK), NONE(AVPUCQ), NONE(RESERVED76), - NONE(RESERVED77), - NONE(RESERVED78), + NONE(TRACECLKIN), + NONE(SOC_THERM), NONE(DTV), /* 80 */ PERIPHC_NANDSPEED, PERIPHC_I2CSLOW, NONE(DSIB), - NONE(RESERVED83), - NONE(IRAMA), - NONE(IRAMB), - NONE(IRAMC), - NONE(IRAMD), + PERIPHC_TSEC, + NONE(RESERVED84), + NONE(RESERVED85), + NONE(RESERVED86), + NONE(EMUCIF), /* 88 */ - NONE(CRAM2), - NONE(RESERVED89), - NONE(MDOUBLER), - NONE(RESERVED91), - NONE(SUSOUT), + NONE(RESERVED88), + NONE(XUSB_HOST), + NONE(RESERVED90), + PERIPHC_MSENC, + NONE(RESERVED92), NONE(RESERVED93), NONE(RESERVED94), - NONE(RESERVED95), + NONE(XUSB_DEV), /* V word: 31:0 */ NONE(CPUG), NONE(CPULP), PERIPHC_G3D2, PERIPHC_MSELECT, - PERIPHC_TSENSOR, + NONE(V_RESERVED4), PERIPHC_I2S3, PERIPHC_I2S4, PERIPHC_I2C4, - /* 08 */ + /* 104 */ PERIPHC_SBC5, PERIPHC_SBC6, PERIPHC_AUDIO, @@ -379,63 +427,63 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { PERIPHC_DAM2, PERIPHC_HDA2CODEC2X, - /* 16 */ + /* 112 */ NONE(ATOMICS), - NONE(RESERVED17), - NONE(RESERVED18), - NONE(RESERVED19), - NONE(RESERVED20), - NONE(RESERVED21), - NONE(RESERVED22), + NONE(V_RESERVED17), + NONE(V_RESERVED18), + NONE(V_RESERVED19), + NONE(V_RESERVED20), + NONE(V_RESERVED21), + NONE(V_RESERVED22), PERIPHC_ACTMON, - /* 24 */ - NONE(RESERVED24), - NONE(RESERVED25), - NONE(RESERVED26), - NONE(RESERVED27), + /* 120 */ + NONE(V_RESERVED24), + NONE(V_RESERVED25), + NONE(V_RESERVED26), + NONE(V_RESERVED27), PERIPHC_SATA, PERIPHC_HDA, - NONE(RESERVED30), - NONE(RESERVED31), + NONE(V_RESERVED30), + NONE(V_RESERVED31), /* W word: 31:0 */ NONE(HDA2HDMICODEC), - NONE(RESERVED1_SATACOLD), - NONE(RESERVED2_PCIERX0), - NONE(RESERVED3_PCIERX1), - NONE(RESERVED4_PCIERX2), - NONE(RESERVED5_PCIERX3), - NONE(RESERVED6_PCIERX4), - NONE(RESERVED7_PCIERX5), - - /* 40 */ + NONE(SATACOLD), + NONE(W_RESERVED2), + NONE(W_RESERVED3), + NONE(W_RESERVED4), + NONE(W_RESERVED5), + NONE(W_RESERVED6), + NONE(W_RESERVED7), + + /* 136 */ NONE(CEC), - NONE(PCIE2_IOBIST), - NONE(EMC_IOBIST), - NONE(HDMI_IOBIST), - NONE(SATA_IOBIST), - NONE(MIPI_IOBIST), - NONE(EMC1_IOBIST), - NONE(XUSB), - - /* 48 */ - NONE(CILAB), - NONE(CILCD), - NONE(CILE), - NONE(DSIA_LP), - NONE(DSIB_LP), - NONE(RESERVED21_ENTROPY), - NONE(RESERVED22_W), - NONE(RESERVED23_W), - - /* 56 */ - NONE(RESERVED24_W), + NONE(W_RESERVED9), + NONE(W_RESERVED10), + NONE(W_RESERVED11), + NONE(W_RESERVED12), + NONE(W_RESERVED13), + NONE(XUSB_PADCTL), + NONE(W_RESERVED15), + + /* 144 */ + NONE(W_RESERVED16), + NONE(W_RESERVED17), + NONE(W_RESERVED18), + NONE(W_RESERVED19), + NONE(W_RESERVED20), + NONE(ENTROPY), + NONE(W_RESERVED22), + NONE(W_RESERVED23), + + /* 152 */ + NONE(W_RESERVED24), NONE(AMX0), NONE(ADX0), NONE(DVFS), NONE(XUSB_SS), - NONE(EMC_DLL), + NONE(W_RESERVED29), NONE(MC1), NONE(EMC1), }; @@ -510,7 +558,7 @@ int get_periph_clock_source(enum periph_id periph_id, *mux_bits = clock_source[type][CLOCK_MAX_MUX]; - if (type == CLOCK_TYPE_PCMT16) + if (type == CLOCK_TYPE_PC2CC3M_T16) *divider_bits = 16; else *divider_bits = 8; @@ -583,21 +631,61 @@ enum periph_id clk_id_to_periph_id(int clk_id) switch (clk_id) { case PERIPH_ID_RESERVED3: + case PERIPH_ID_RESERVED4: case PERIPH_ID_RESERVED16: - case PERIPH_ID_RESERVED24: + case PERIPH_ID_RESERVED25: case PERIPH_ID_RESERVED35: + case PERIPH_ID_RESERVED36: + case PERIPH_ID_RESERVED38: + case PERIPH_ID_RESERVED39: case PERIPH_ID_RESERVED43: case PERIPH_ID_RESERVED45: - case PERIPH_ID_RESERVED56: + case PERIPH_ID_RESERVED49: + case PERIPH_ID_RESERVED53: + case PERIPH_ID_RESERVED64: case PERIPH_ID_RESERVED76: - case PERIPH_ID_RESERVED77: - case PERIPH_ID_RESERVED78: - case PERIPH_ID_RESERVED83: - case PERIPH_ID_RESERVED89: - case PERIPH_ID_RESERVED91: + case PERIPH_ID_RESERVED84: + case PERIPH_ID_RESERVED85: + case PERIPH_ID_RESERVED86: + case PERIPH_ID_RESERVED88: + case PERIPH_ID_RESERVED90: + case PERIPH_ID_RESERVED92: case PERIPH_ID_RESERVED93: case PERIPH_ID_RESERVED94: - case PERIPH_ID_RESERVED95: + case PERIPH_ID_V_RESERVED4: + case PERIPH_ID_V_RESERVED17: + case PERIPH_ID_V_RESERVED18: + case PERIPH_ID_V_RESERVED19: + case PERIPH_ID_V_RESERVED20: + case PERIPH_ID_V_RESERVED21: + case PERIPH_ID_V_RESERVED22: + case PERIPH_ID_V_RESERVED24: + case PERIPH_ID_V_RESERVED25: + case PERIPH_ID_V_RESERVED26: + case PERIPH_ID_V_RESERVED27: + case PERIPH_ID_V_RESERVED30: + case PERIPH_ID_V_RESERVED31: + case PERIPH_ID_W_RESERVED2: + case PERIPH_ID_W_RESERVED3: + case PERIPH_ID_W_RESERVED4: + case PERIPH_ID_W_RESERVED5: + case PERIPH_ID_W_RESERVED6: + case PERIPH_ID_W_RESERVED7: + case PERIPH_ID_W_RESERVED9: + case PERIPH_ID_W_RESERVED10: + case PERIPH_ID_W_RESERVED11: + case PERIPH_ID_W_RESERVED12: + case PERIPH_ID_W_RESERVED13: + case PERIPH_ID_W_RESERVED15: + case PERIPH_ID_W_RESERVED16: + case PERIPH_ID_W_RESERVED17: + case PERIPH_ID_W_RESERVED18: + case PERIPH_ID_W_RESERVED19: + case PERIPH_ID_W_RESERVED20: + case PERIPH_ID_W_RESERVED22: + case PERIPH_ID_W_RESERVED23: + case PERIPH_ID_W_RESERVED24: + case PERIPH_ID_W_RESERVED29: return PERIPH_ID_NONE; default: return clk_id; diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index 74bd22b..89c3529 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -60,12 +60,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index a4c17e7..8200090 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -243,6 +243,9 @@ enum { #define OUT_CLK_SOURCE_SHIFT 30 #define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define OUT_CLK_SOURCE3_SHIFT 29 +#define OUT_CLK_SOURCE3_MASK (7U << OUT_CLK_SOURCE3_SHIFT) + #define OUT_CLK_SOURCE4_SHIFT 28 #define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd..9495179 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -20,6 +20,12 @@ enum clock_osc_freq { CLOCK_OSC_FREQ_COUNT, }; +enum { + MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ + MASK_BITS_31_29, + MASK_BITS_29_28, +}; + #include <asm/arch/clock-tables.h> /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 @@ -305,4 +311,15 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); /* SoC-specific TSC init */ void arch_timer_init(void); +/** + * Enable a peripheral clock with a certain clock source/divisor + * + * @param periph_id peripheral to enable/change + * @param src PLL id of required parent clock + * @param divisor required integer divisor (not 7.1) + * @return 0 if ok + * -1 on error (bad divisor, etc.). + */ +int clock_periph_enable(enum periph_id pid, int src, int divisor); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index d8fa0e1..19b8acf 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -40,7 +40,17 @@ enum clock_id { CLOCK_ID_OSC, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ + + /* + * These are clock ids that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + CLOCK_ID_NONE = -1, }; @@ -53,7 +63,7 @@ enum periph_id { PERIPH_ID_COP, PERIPH_ID_TRIGSYS, PERIPH_ID_RESERVED3, - PERIPH_ID_RTC, + PERIPH_ID_RESERVED4, PERIPH_ID_TMR, PERIPH_ID_UART1, PERIPH_ID_UART2, @@ -80,7 +90,7 @@ enum periph_id { /* 24 */ PERIPH_ID_3D, - PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, PERIPH_ID_DISP2, PERIPH_ID_DISP1, PERIPH_ID_HOST1X, @@ -93,10 +103,10 @@ enum periph_id { PERIPH_ID_AHBDMA, PERIPH_ID_APBDMA, PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, + PERIPH_ID_RESERVED36, PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, + PERIPH_ID_RESERVED38, + PERIPH_ID_RESERVED39, /* 40 */ PERIPH_ID_KFUSE, @@ -110,16 +120,16 @@ enum periph_id { /* 48 */ PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, PERIPH_ID_HDMI, PERIPH_ID_CSI, - PERIPH_ID_TVDAC, + PERIPH_ID_RESERVED53, PERIPH_ID_I2C2, PERIPH_ID_UART3, /* 56 */ - PERIPH_ID_RESERVED56, + PERIPH_ID_MIPI_CAL, PERIPH_ID_EMC, PERIPH_ID_USB2, PERIPH_ID_USB3, @@ -129,7 +139,7 @@ enum periph_id { PERIPH_ID_BSEV, /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_SPEEDO, + PERIPH_ID_RESERVED64, PERIPH_ID_UART4, PERIPH_ID_UART5, PERIPH_ID_I2C3, @@ -144,29 +154,29 @@ enum periph_id { PERIPH_ID_PCIEXCLK, PERIPH_ID_AVPUCQ, PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, PERIPH_ID_DTV, /* 80 */ PERIPH_ID_NANDSPEED, PERIPH_ID_I2CSLOW, PERIPH_ID_DSIB, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_RESERVED89, - PERIPH_ID_MDOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUSOUT, + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, PERIPH_ID_RESERVED93, PERIPH_ID_RESERVED94, - PERIPH_ID_RESERVED95, + PERIPH_ID_XUSB_DEV, PERIPH_ID_VW_FIRST, /* V word: 31:0 */ @@ -174,7 +184,7 @@ enum periph_id { PERIPH_ID_CPULP, PERIPH_ID_3D2, PERIPH_ID_MSELECT, - PERIPH_ID_TSENSOR, + PERIPH_ID_V_RESERVED4, PERIPH_ID_I2S3, PERIPH_ID_I2S4, PERIPH_ID_I2C4, @@ -191,61 +201,61 @@ enum periph_id { /* 112 */ PERIPH_ID_ATOMICS, - PERIPH_ID_EX_RESERVED17, - PERIPH_ID_EX_RESERVED18, - PERIPH_ID_EX_RESERVED19, - PERIPH_ID_EX_RESERVED20, - PERIPH_ID_EX_RESERVED21, - PERIPH_ID_EX_RESERVED22, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, PERIPH_ID_ACTMON, /* 120 */ - PERIPH_ID_EX_RESERVED24, - PERIPH_ID_EX_RESERVED25, - PERIPH_ID_EX_RESERVED26, - PERIPH_ID_EX_RESERVED27, + PERIPH_ID_V_RESERVED24, + PERIPH_ID_V_RESERVED25, + PERIPH_ID_V_RESERVED26, + PERIPH_ID_V_RESERVED27, PERIPH_ID_SATA, PERIPH_ID_HDA, - PERIPH_ID_EX_RESERVED30, - PERIPH_ID_EX_RESERVED31, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, /* W word: 31:0 */ PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_RESERVED1_SATACOLD, - PERIPH_ID_RESERVED2_PCIERX0, - PERIPH_ID_RESERVED3_PCIERX1, - PERIPH_ID_RESERVED4_PCIERX2, - PERIPH_ID_RESERVED5_PCIERX3, - PERIPH_ID_RESERVED6_PCIERX4, - PERIPH_ID_RESERVED7_PCIERX5, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, /* 136 */ PERIPH_ID_CEC, - PERIPH_ID_PCIE2_IOBIST, - PERIPH_ID_EMC_IOBIST, - PERIPH_ID_HDMI_IOBIST, - PERIPH_ID_SATA_IOBIST, - PERIPH_ID_MIPI_IOBIST, - PERIPH_ID_EMC1_IOBIST, - PERIPH_ID_XUSB, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, /* 144 */ - PERIPH_ID_CILAB, - PERIPH_ID_CILCD, - PERIPH_ID_CILE, - PERIPH_ID_DSIA_LP, - PERIPH_ID_DSIB_LP, - PERIPH_ID_RESERVED21_ENTROPY, - PERIPH_ID_RESERVED22_W, - PERIPH_ID_RESERVED23_W, + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_W_RESERVED22, + PERIPH_ID_W_RESERVED23, /* 152 */ - PERIPH_ID_RESERVED24_W, + PERIPH_ID_W_RESERVED24, PERIPH_ID_AMX0, PERIPH_ID_ADX0, PERIPH_ID_DVFS, PERIPH_ID_XUSB_SS, - PERIPH_ID_EMC_DLL, + PERIPH_ID_W_RESERVED29, PERIPH_ID_MC1, PERIPH_ID_EMC1, @@ -290,7 +300,7 @@ enum periphc_internal_id { PERIPHC_DISP2, /* 0x10 */ - PERIPHC_CVE, + PERIPHC_10h, PERIPHC_11h, PERIPHC_VI, PERIPHC_13h, @@ -305,17 +315,17 @@ enum periphc_internal_id { PERIPHC_VFIR, PERIPHC_EPP, PERIPHC_MPE, - PERIPHC_MIPI, + PERIPHC_HSI, PERIPHC_UART1, PERIPHC_UART2, /* 0x20 */ PERIPHC_HOST1X, PERIPHC_21h, - PERIPHC_TVO, + PERIPHC_22h, PERIPHC_HDMI, PERIPHC_24h, - PERIPHC_TVDAC, + PERIPHC_25h, PERIPHC_I2C2, PERIPHC_EMC, @@ -337,10 +347,20 @@ enum periphc_internal_id { PERIPHC_NOR, PERIPHC_CSITE, PERIPHC_I2S0, - PERIPHC_37h, + PERIPHC_DTV, - PERIPHC_VW_FIRST, /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ PERIPHC_G3D2 = PERIPHC_VW_FIRST, PERIPHC_MSELECT, PERIPHC_TSENSOR, @@ -350,9 +370,9 @@ enum periphc_internal_id { PERIPHC_SBC5, PERIPHC_SBC6, - /* 0x40 */ + /* 0x48 */ PERIPHC_AUDIO, - PERIPHC_41h, + PERIPHC_49h, PERIPHC_DAM0, PERIPHC_DAM1, PERIPHC_DAM2, @@ -360,21 +380,21 @@ enum periphc_internal_id { PERIPHC_ACTMON, PERIPHC_EXTPERIPH1, - /* 0x48 */ + /* 0x50 */ PERIPHC_EXTPERIPH2, PERIPHC_EXTPERIPH3, PERIPHC_NANDSPEED, PERIPHC_I2CSLOW, PERIPHC_SYS, - PERIPHC_SPEEDO, - PERIPHC_4eh, - PERIPHC_4fh, - - /* 0x50 */ - PERIPHC_50h, - PERIPHC_51h, - PERIPHC_52h, - PERIPHC_53h, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, PERIPHC_SATAOOB, PERIPHC_SATA, PERIPHC_HDA, -- 1.8.1.5

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[U-Boot] Compiling fw_printenv tool
by Alexey Smishlayev 17 Jan '14

17 Jan '14

Hello! I'm trying to compile fw_printenv, to work with U-Boot environment variables under my linux os. I'm using commands: $ cd u-boot/ $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- env The tool compiles successfully, I get the executable under u-boot/tools/env/fw_printenv, but it seem to be compiled for my host machine. On my device it says: # ./fw_printenv: line 1: syntax error: "(" unexpected How do I cross compile it for my embedded system? Do I just set the HOSTCC environment variable in the Makefile? Best regards, Alexey Smishlayev

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[U-Boot] Boot Linux kernel with initramfs fails
by Axel Lin 17 Jan '14

17 Jan '14

Hi, When I boot Linux kernel with FIT Image, the kernel does not unpacking initramfs. ( The root cause is "initrd_start is NULL".) The initramfs is built-in with kernel, so I don't specify ramdisk in my kernel.its file. Is this a known issue or do I need special setting to boot a Linux kernel with initramfs? BTW, bootm shows below messages: => bootm ## Loading kernel from FIT Image at 00400000 ... Using 'conf@1' configuration Trying 'kernel@1' kernel subimage Description: kernel Type: Kernel Image Compression: uncompressed Data Start: 0x004000e8 Data Size: 2496848 Bytes = 2.4 MiB Architecture: ARM OS: Linux Load Address: 0x00000000 Entry Point: 0x00000000 Verifying Hash Integrity ... OK ## Loading fdt from FIT Image at 00400000 ... Using 'conf@1' configuration Trying 'fdt@1' fdt subimage Description: gpl327xx.dtb Type: Flat Device Tree Compression: uncompressed Data Start: 0x00661ae8 Data Size: 2174 Bytes = 2.1 KiB Architecture: ARM Hash algo: sha1 Hash value: 674b5443523a23ad8de49b161932fd3a1d7f90ea Verifying Hash Integrity ... sha1+ OK Booting using the fdt blob at 0x661ae8 Loading Kernel Image ... OK ## initrd_high = 0xffffffff, copy_to_ram = 1 ramdisk load start = 0x00000000, ramdisk load end = 0x00000000 Loading Device Tree to 019b4000, end 019b787d ... OK Below is part of my boot messages: NET: Registered protocol family 1 BEGIN::: populate_rootfs... ^^^ My debug message, so I know populate_rootfs() is executed. populate_rootfs... initrd_start is NULL ^^^ My debug message, I got "initrd_start is NULL". That is why the initramfs is not unpack. ROMFS MTD (C) 2007 Red Hat, Inc. io scheduler noop registered (default) TCP: cubic registered NET: Registered protocol family 10 sit: IPv6 over IPv4 tunneling driver Warning: unable to open an initial console. VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6 Please append a correct "root=" boot option; here are the available partitions: Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) CPU: 0 PID: 1 Comm: swapper Not tainted 3.11.0-rc1-00018-g16fc5bc-dirty #131 [<0000bda8>] (unwind_backtrace+0x0/0xf0) from [<0000ac0c>] (show_stack+0x10/0x14) [<0000ac0c>] (show_stack+0x10/0x14) from [<001fcff8>] (panic+0x7c/0x1c4) [<001fcff8>] (panic+0x7c/0x1c4) from [<0026ddb4>] (mount_block_root+0x1f4/0x2b4) [<0026ddb4>] (mount_block_root+0x1f4/0x2b4) from [<0026e000>] (prepare_namespace+0x128/0x18c) [<0026e000>] (prepare_namespace+0x128/0x18c) from [<0026da74>] (kernel_init_freeable+0x164/0x1a8) [<0026da74>] (kernel_init_freeable+0x164/0x1a8) from [<001fb808>] (kernel_init+0x8/0xe4) [<001fb808>] (kernel_init+0x8/0xe4) from [<00008f70>] (ret_from_fork+0x14/0x24) (Test on latest u-boot git tree.) Regards, Axel

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