November 2013 - U-Boot

[U-Boot] [PATCH] arm: am335x: Add DT (FDT) support to Siemens boards
by Stefan Roese 04 Dec '13

04 Dec '13

Enable FDT support for all Siemens AM335x boards. To support newer Linux kernels with DT booting. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> Cc: Roger Meier <r.meier(a)siemens.com> Cc: Lukas Stockmann <lukas.stockmann(a)siemens.com> Cc: Tom Rini <trini(a)ti.com> --- include/configs/siemens-am33x-common.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 745e3be..b6534cc 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -455,4 +455,8 @@ #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ "press \"<Esc><Esc>\" to stop\n", bootdelay +/* Enable Device-Tree (FDT) support */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_FDT + #endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ -- 1.8.4.3

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[U-Boot] [PATCH] pcm051: Support for revision 3
by Lars Poeschel 04 Dec '13

04 Dec '13

From: Lars Poeschel <poeschel(a)lemonage.de> Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on the board. The difference for u-boot is that is has other DDR3 RAM on it: 1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and 2. Both configurations are 512 MiB. Configure your u-boot build with pcm051_rev3 for the new RAM and pcm051_rev1 for the old RAM configuration. Board revision 2 has to use pcm051_rev1 also. Signed-off-by: Lars Poeschel <poeschel(a)lemonage.de> --- board/phytec/pcm051/board.c | 53 ++++++++++++++++++++++++++++++++++++++++----- boards.cfg | 3 ++- 2 files changed, 49 insertions(+), 7 deletions(-) diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index e40b0bd..629bc52 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -49,6 +49,7 @@ const struct dpll_params *get_dpll_ddr_params(void) return &dpll_ddr; } +#ifdef CONFIG_REV1 static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, @@ -82,6 +83,52 @@ static struct emif_regs ddr3_emif_reg_data = { PHY_EN_DYN_PWRDN, }; +void sdram_init(void) +{ + config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#else +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +void sdram_init(void) +{ + config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif + void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -95,12 +142,6 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } - -void sdram_init(void) -{ - config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} #endif /* diff --git a/boards.cfg b/boards.cfg index 9fc77fb..c2e24d6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -244,7 +244,8 @@ Active arm armv7 - armltd vexpress Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel(a)linaro.org> Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel(a)linaro.org> Active arm armv7 am33xx isee igep0033 igep0033 - Enric Balletbo i Serra <eballetbo(a)iseebcn.com> -Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel <poeschel(a)lemonage.de> +Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel(a)lemonage.de> +Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel(a)lemonage.de> Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier(a)siemens.com> -- 1.8.4.2

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[U-Boot] [PATCH] am335x_evm: Update nandboot to use partitions and DT
by Tom Rini 04 Dec '13

04 Dec '13

Signed-off-by: Tom Rini <trini(a)ti.com> --- include/configs/am335x_evm.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index f35ed6f..a1a5096 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -42,12 +42,11 @@ "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ "nandrootfstype=ubifs rootwait=1\0" \ - "nandsrcaddr=0x280000\0" \ - "nandboot=echo Booting from nand ...; " \ + "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ - "bootz ${loadaddr}\0" \ - "nandimgsize=0x500000\0" + "nand read ${fdtaddr} u-boot-spl-os; " \ + "nand read ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" #else #define NANDARGS "" #endif -- 1.7.9.5

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[U-Boot] [PATCH] arm: omap3: Add uart4 omap3 adddress
by Michael Trimarchi 04 Dec '13

04 Dec '13

This patch add the OMAP34XX_UART4 memory address Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- arch/arm/include/asm/arch-omap3/omap3.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 7fb549a..65a5995 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -55,6 +55,7 @@ struct control_prog_io { #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) +#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) /* General Purpose Timers */ #define OMAP34XX_GPT1 0x48318000 -- 1.8.1.2

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[U-Boot] [PATCH] ARM: OMAP5+: Remove unnecessary EFUSE settings
by Lokesh Vutla 04 Dec '13

04 Dec '13

Certain EFUSE settings were recommended for the first four lots of OMAP5 ES1.0 silicon. These are not applicable for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings. Reported-by: Griffis, Brad <bgriffis(a)ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- arch/arm/cpu/armv7/omap5/hwinit.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 1065891..8a5e6ed 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -168,12 +168,6 @@ void do_io_settings(void) io_settings_lpddr2(); else io_settings_ddr3(); - - /* Efuse settings */ - writel(EFUSE_1, (*ctrl)->control_efuse_1); - writel(EFUSE_2, (*ctrl)->control_efuse_2); - writel(EFUSE_3, (*ctrl)->control_efuse_3); - writel(EFUSE_4, (*ctrl)->control_efuse_4); } static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { -- 1.7.9.5

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[U-Boot] [PATCH V2 0/3] OMAP5/DRA7: EMIF fixes for lowpower usecases
by Sricharan R 04 Dec '13

04 Dec '13

1) Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases 2) When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Sricharan R (3): ARM: DRA7: Add is_dra7xx cpu check definition ARM: DRA: EMIF: Change DDR3 settings to use hw leveling ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039 arch/arm/cpu/armv7/omap-common/emif-common.c | 142 +++++++++++++---- arch/arm/cpu/armv7/omap5/hw_data.c | 9 +- arch/arm/cpu/armv7/omap5/hwinit.c | 12 +- arch/arm/cpu/armv7/omap5/sdram.c | 214 ++++++++++++++++++-------- arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/emif.h | 14 +- arch/arm/include/asm/omap_common.h | 8 + 7 files changed, 301 insertions(+), 99 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH] am33xx: Stop modifying certain EMIF4D registers
by Tom Rini 04 Dec '13

04 Dec '13

Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo(a)iseebcn.com> Cc: Javier Martinez Canillas <javier(a)dowhile0.org> Cc: Heiko Schocher <hs(a)denx.de> Cc: Matt Porter <matt.porter(a)linaro.org> Cc: Lars Poeschel <poeschel(a)lemonage.de> Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/am33xx/ddr.c | 7 ------ arch/arm/include/asm/arch-am33xx/ddr_defs.h | 31 ++++++--------------------- board/isee/igep0033/board.c | 4 ---- board/phytec/pcm051/board.c | 4 ---- board/siemens/dxr2/board.c | 4 ---- board/siemens/pxm2/board.c | 5 ----- board/siemens/rut/board.c | 5 ----- board/ti/am335x/board.c | 17 --------------- board/ti/ti814x/evm.c | 5 ----- board/ti/ti816x/evm.c | 17 --------------- 10 files changed, 6 insertions(+), 93 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fa697c7..5b0454c 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -89,15 +89,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); - writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff); writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); - writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff); writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); - writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff); writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); } @@ -121,10 +118,6 @@ void config_ddr_data(const struct ddr_data *data, int nr) &(ddr_data_reg[nr]+i)->dt0fwsratio0); writel(data->datawrsratio0, &(ddr_data_reg[nr]+i)->dt0wrsratio0); - writel(data->datauserank0delay, - &(ddr_data_reg[nr]+i)->dt0rdelays0); - writel(data->datadldiff0, - &(ddr_data_reg[nr]+i)->dt0dldiff0); } } diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index fe48b5f..e5bda64 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -18,7 +18,6 @@ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) #define VTP_CTRL_START_EN (0x1) -#define PHY_DLL_LOCK_DIFF 0x0 #define DDR_CKE_CTRL_NORMAL 0x1 #define PHY_EN_DYN_PWRDN (0x1 << 20) @@ -29,7 +28,6 @@ #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a -#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 #define MT47H128M16RT25E_RATIO 0x80 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 @@ -38,7 +36,6 @@ #define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 -#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B /* Micron MT41J128M16JT-125 */ @@ -49,7 +46,6 @@ #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 #define MT41J128MJT125_EMIF_SDREF 0x0000093B #define MT41J128MJT125_ZQ_CFG 0x50074BE4 -#define MT41J128MJT125_DLL_LOCK_DIFF 0x1 #define MT41J128MJT125_RATIO 0x40 #define MT41J128MJT125_INVERT_CLKOUT 0x1 #define MT41J128MJT125_RD_DQS 0x3B @@ -66,7 +62,6 @@ #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 -#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 #define MT41J256M8HX15E_RATIO 0x40 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 #define MT41J256M8HX15E_RD_DQS 0x3B @@ -83,7 +78,6 @@ #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 -#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 #define MT41K256M16HA125E_RATIO 0x80 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 #define MT41K256M16HA125E_RD_DQS 0x38 @@ -100,7 +94,6 @@ #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 -#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1 #define MT41J512M8RH125_RATIO 0x80 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 #define MT41J512M8RH125_RD_DQS 0x3B @@ -117,7 +110,6 @@ #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 -#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 #define K4B2G1646EBIH9_RATIO 0x80 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 #define K4B2G1646EBIH9_RD_DQS 0x35 @@ -149,18 +141,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr); struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv1[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int resv1[3]; unsigned int cm0iclkout; /* offset 0x02C */ unsigned int resv2[8]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv3[3]; unsigned int cm1iclkout; /* offset 0x060 */ unsigned int resv4[8]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv5[3]; unsigned int cm2iclkout; /* offset 0x094 */ unsigned int resv6[3]; }; @@ -197,24 +186,21 @@ struct ddr_regs { unsigned int cm0configclk; /* offset 0x010 */ unsigned int resv1[2]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv2[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int resv2[3]; unsigned int cm0iclkout; /* offset 0x02C */ unsigned int resv3[4]; unsigned int cm1config; /* offset 0x040 */ unsigned int cm1configclk; /* offset 0x044 */ unsigned int resv4[2]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv5[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv5[3]; unsigned int cm1iclkout; /* offset 0x060 */ unsigned int resv6[4]; unsigned int cm2config; /* offset 0x074 */ unsigned int cm2configclk; /* offset 0x078 */ unsigned int resv7[2]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv8[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv8[3]; unsigned int cm2iclkout; /* offset 0x094 */ unsigned int resv9[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ @@ -243,17 +229,14 @@ struct cmd_control { unsigned long cmd0csratio; unsigned long cmd0csforce; unsigned long cmd0csdelay; - unsigned long cmd0dldiff; unsigned long cmd0iclkout; unsigned long cmd1csratio; unsigned long cmd1csforce; unsigned long cmd1csdelay; - unsigned long cmd1dldiff; unsigned long cmd1iclkout; unsigned long cmd2csratio; unsigned long cmd2csforce; unsigned long cmd2csdelay; - unsigned long cmd2dldiff; unsigned long cmd2iclkout; }; @@ -267,8 +250,6 @@ struct ddr_data { unsigned long datagiratio0; unsigned long datafwsratio0; unsigned long datawrsratio0; - unsigned long datauserank0delay; - unsigned long datadldiff0; }; /** diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 0b8356d..6a8ca2b 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -35,20 +35,16 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = K4B2G1646EBIH9_RATIO, - .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd1csratio = K4B2G1646EBIH9_RATIO, - .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd2csratio = K4B2G1646EBIH9_RATIO, - .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, }; diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index dafb1eb..83ee51e 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -54,20 +54,16 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = MT41J256M8HX15E_WR_DQS, .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J256M8HX15E_RATIO, - .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, .cmd1csratio = MT41J256M8HX15E_RATIO, - .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, .cmd2csratio = MT41J256M8HX15E_RATIO, - .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, }; diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index af9d84f..c9b7951 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -139,13 +139,9 @@ struct emif_regs dxr2_ddr3_emif_reg_data = { }; struct ddr_data dxr2_ddr3_data = { - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; struct cmd_control dxr2_ddr3_cmd_ctrl_data = { - .cmd0dldiff = 0, - .cmd1dldiff = 0, - .cmd2dldiff = 0, }; /* pass values from eeprom */ dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 2c1841f..36b3776 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -58,19 +58,14 @@ struct ddr_data pxm2_ddr3_data = { .datawdsratio0 = 0, .datafwsratio0 = 0x8020080, .datawrsratio0 = 0x4010040, - .datauserank0delay = 1, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; struct cmd_control pxm2_ddr3_cmd_ctrl_data = { .cmd0csratio = 0x80, - .cmd0dldiff = 0, .cmd0iclkout = 0, .cmd1csratio = 0x80, - .cmd1dldiff = 0, .cmd1iclkout = 0, .cmd2csratio = 0x80, - .cmd2dldiff = 0, .cmd2iclkout = 0, }; diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 5de8fc6..60bad11 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -63,19 +63,14 @@ struct ddr_data rut_ddr3_data = { .datawdsratio0 = 0x85, .datafwsratio0 = 0x100, .datawrsratio0 = 0xc1, - .datauserank0delay = 1, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; struct cmd_control rut_ddr3_cmd_ctrl_data = { .cmd0csratio = 0x40, - .cmd0dldiff = 0, .cmd0iclkout = 1, .cmd1csratio = 0x40, - .cmd1dldiff = 0, .cmd1iclkout = 1, .cmd2csratio = 0x40, - .cmd2dldiff = 0, .cmd2iclkout = 1, }; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57fedab..1459fae 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -107,21 +107,16 @@ static const struct ddr_data ddr2_data = { (MT47H128M16RT25E_PHY_WR_DATA<<20) | (MT47H128M16RT25E_PHY_WR_DATA<<10) | (MT47H128M16RT25E_PHY_WR_DATA<<0)), - .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; @@ -139,7 +134,6 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = MT41J128MJT125_WR_DQS, .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct ddr_data ddr3_beagleblack_data = { @@ -147,7 +141,6 @@ static const struct ddr_data ddr3_beagleblack_data = { .datawdsratio0 = MT41K256M16HA125E_WR_DQS, .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct ddr_data ddr3_evm_data = { @@ -155,48 +148,38 @@ static const struct ddr_data ddr3_evm_data = { .datawdsratio0 = MT41J512M8RH125_WR_DQS, .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, - .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd1csratio = MT41J128MJT125_RATIO, - .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd2csratio = MT41J128MJT125_RATIO, - .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, }; static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd0csratio = MT41J512M8RH125_RATIO, - .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd1csratio = MT41J512M8RH125_RATIO, - .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd2csratio = MT41J512M8RH125_RATIO, - .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, }; diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index e406326..0b76a77 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -33,15 +33,12 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_SPL_BUILD static const struct cmd_control evm_ddr2_cctrl_data = { .cmd0csratio = 0x80, - .cmd0dldiff = 0x04, .cmd0iclkout = 0x00, .cmd1csratio = 0x80, - .cmd1dldiff = 0x04, .cmd1iclkout = 0x00, .cmd2csratio = 0x80, - .cmd2dldiff = 0x04, .cmd2iclkout = 0x00, }; @@ -77,8 +74,6 @@ static const struct ddr_data evm_ddr2_data = { .datagiratio0 = ((0<<10) | (0<<0)), .datafwsratio0 = ((0x90<<10) | (0x90<<0)), .datawrsratio0 = ((0x50<<10) | (0x50<<0)), - .datauserank0delay = 1, - .datadldiff0 = 0x4, }; void set_uart_mux_conf(void) diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index 74d35e9..a53859e 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -59,21 +59,16 @@ static struct ddr_data ddr2_data = { .datagiratio0 = ((0x0<<10) | (0x0<<0)), .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), - .datauserank0delay = 0x1, - .datadldiff0 = 0x0, /* depend on cpu rev, set later */ }; static struct cmd_control ddr2_ctrl = { .cmd0csratio = 0x80, - .cmd0dldiff = 0x04, /* reset value is 0x4 */ .cmd0iclkout = 0x00, .cmd1csratio = 0x80, - .cmd1dldiff = 0x04, /* reset value is 0x4 */ .cmd1iclkout = 0x00, .cmd2csratio = 0x80, - .cmd2dldiff = 0x04, /* reset value is 0x4 */ .cmd2iclkout = 0x00, }; @@ -150,21 +145,16 @@ static struct ddr_data ddr3_data = { .datagiratio0 = ((0x20<<10) | 0x20<<0), .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), - .datauserank0delay = 0x1, - .datadldiff0 = 0x0, /* depend on cpu rev, set later */ }; static const struct cmd_control ddr3_ctrl = { .cmd0csratio = 0x100, - .cmd0dldiff = 0x004, /* reset value is 0x4 */ .cmd0iclkout = 0x001, .cmd1csratio = 0x100, - .cmd1dldiff = 0x004, /* reset value is 0x4 */ .cmd1iclkout = 0x001, .cmd2csratio = 0x100, - .cmd2dldiff = 0x004, /* reset value is 0x4 */ .cmd2iclkout = 0x001, }; @@ -198,11 +188,6 @@ void sdram_init(void) config_dmm(&evm_lisa_map_regs); #ifdef CONFIG_TI816X_EVM_DDR2 - ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - if (CONFIG_TI816X_USE_EMIF0) { ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); @@ -217,8 +202,6 @@ void sdram_init(void) #endif #ifdef CONFIG_TI816X_EVM_DDR3 - ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - if (CONFIG_TI816X_USE_EMIF0) config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); -- 1.7.9.5

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[U-Boot] [PATCH 0/3] Add support for CM-T335 board
by Ilya Ledvich 04 Dec '13

04 Dec '13

This patch series adds support for the Compulab CM-T335 board. The board is based on TI Sitara AM3352/4 SoC and provides folowing features: - 128MB to 512MB DDR3 - 128MB to 1GB NAND as a main storage - Micro SD/MMC card as a secondary storage - USB2.0 x4 host ports or USB2.0 x1 OTG port - Gigabit Ethernet, WiFi 802.11, Bluetooth, CAN bus, UART - LCD/DVI/LVDS display, touchscreen - Analog audio Ilya Ledvich (3): cm_t335: add cm_t335 board support cm_t335: add support for status LED cm_t335: add support for pca9555 i2c gpio extender arch/arm/include/asm/arch-am33xx/ddr_defs.h | 6 + board/compulab/cm_t335/Makefile | 32 +++++ board/compulab/cm_t335/cm_t335.c | 162 ++++++++++++++++++++++++ board/compulab/cm_t335/mux.c | 117 +++++++++++++++++ board/compulab/cm_t335/spl.c | 110 ++++++++++++++++ board/compulab/cm_t335/u-boot.lds | 101 +++++++++++++++ boards.cfg | 1 + include/configs/cm_t335.h | 182 +++++++++++++++++++++++++++ 8 files changed, 711 insertions(+) create mode 100644 board/compulab/cm_t335/Makefile create mode 100644 board/compulab/cm_t335/cm_t335.c create mode 100644 board/compulab/cm_t335/mux.c create mode 100644 board/compulab/cm_t335/spl.c create mode 100644 board/compulab/cm_t335/u-boot.lds create mode 100644 include/configs/cm_t335.h -- 1.7.9.5

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[U-Boot] [RFC PATCH v2 0/2] ARMV7: OMAP4: Add support for twl6032
by Oleg Kosheliev 04 Dec '13

04 Dec '13

From: Oleg Kosheliev <oleg.kosheliev(a)globallogic.com> TWL6032 is a companion Power Management IC (PMIC) of OMAP4470. This chip is similar to TWL6030 but has slight difference in some registers e.g. for GPADC. In u-boot only TWL6030 is supported now, thus there is no ability to boot OMAP4470 with TWL6032 because u-boot hangs when attempts to get the battery voltage from GPADC using false ctrl register address. These patches add the detection of the TWL chip type and support for TWL6032 chip in the battery charger driver. Changes in v2: - removed typedef for twl603x_chip_type - printf replaced with puts Oleg Kosheliev (2): ARMV7: OMAP4: Add struct for twl603x data ARMV7: OMAP4: Add twl6032 support drivers/power/twl6030.c | 77 +++++++++++++++++++++++++++++++++++++++++------ include/twl6030.h | 38 +++++++++++++++++++++++ 2 files changed, 105 insertions(+), 10 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH] ARM: mx6: Remove the FDT loading address to avoid overlaping
by Otavio Salvador 04 Dec '13

04 Dec '13

This patch fixes allow for the DeviceTree and initrd relocation fixing the boot of FSL 3.10.9-1.0.0-alpha kernel. This changes following boards: - mx6sabreauto - mx6sabresd - wandboard - udoo - nitrogen6x - cgtqmx6eval The reasoning, as explained by Hui Liu, is: ,---- | The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel | Boot up, it will decompress the compressed kernel image and place the decompressed | kernel image at the low end of the DDR memory and start running from it. If the | decompressed kernel image is bigger for example than 16M, it may over written the | fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000 | | To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override | Since we will not likely have one kernel image larger than 128MB. `---- Removing the fdt_high and initrd_high this allows for those to be relocated. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- include/configs/cgtqmx6eval.h | 2 -- include/configs/mx6sabre_common.h | 2 -- include/configs/nitrogen6x.h | 2 -- include/configs/udoo.h | 2 -- include/configs/wandboard.h | 2 -- 5 files changed, 10 deletions(-) diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index d5db8f5..48acf50 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -79,8 +79,6 @@ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "boot_dir=/boot\0" \ "console=ttymxc1\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "fdt_addr=0x11000000\0" \ "boot_fdt=try\0" \ "mmcdev=1\0" \ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 4b4f640..01acd7f 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -108,8 +108,6 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONFIG_CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 3df8de0..93c88c9 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -186,8 +186,6 @@ "script=boot.scr\0" \ "uimage=uImage\0" \ "console=ttymxc1\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "fdt_file=imx6q-sabrelite.dtb\0" \ "fdt_addr=0x11000000\0" \ "boot_fdt=try\0" \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 78df071..e38a598 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -74,8 +74,6 @@ "uimage=uImage\0" \ "console=ttymxc1\0" \ "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x11000000\0" \ "boot_fdt=try\0" \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 68ff724..8d9b5d8 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -118,8 +118,6 @@ "uimage=uImage\0" \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x11000000\0" \ "boot_fdt=try\0" \ -- 1.8.4.3

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