November 2013 - U-Boot

[U-Boot] [PATCH] drivers:power:exynos-tmu: add support for Exynos5260
by Naveen Krishna Chatradhi 05 Dec '13

05 Dec '13

This patch adds support for TMU on Exynos5260 Register bit fields are little different from the previous versions. Change-Id: Ibe835abe9cb255d2f8375c8e9e32d32cff19c093 Signed-off-by: Naveen Krishna Chatradhi <ch.naveen(a)samsung.com> --- arch/arm/include/asm/arch-exynos/tmu.h | 11 +++++++++++ drivers/power/exynos-tmu.c | 25 +++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/tmu.h b/arch/arm/include/asm/arch-exynos/tmu.h index cad3569..19b8f62 100644 --- a/arch/arm/include/asm/arch-exynos/tmu.h +++ b/arch/arm/include/asm/arch-exynos/tmu.h @@ -26,7 +26,11 @@ struct exynos5_tmu_reg { u32 triminfo_control; u32 rsvd5[2]; u32 tmu_control; +#ifdef CONFIG_EXYNOS5260 + u32 tmu_control1; +#else u32 rsvd7; +#endif u32 tmu_status; u32 sampling_internal; u32 counter_value0; @@ -41,10 +45,17 @@ struct exynos5_tmu_reg { u32 past_temp7_4; u32 past_temp11_8; u32 past_temp15_12; +#ifdef CONFIG_EXYNOS5260 + u32 rsvd15[16]; +#endif u32 inten; u32 intstat; u32 intclear; +#ifdef CONFIG_EXYNOS5260 + u32 rsvd31[17]; +#else u32 rsvd15; +#endif u32 emul_con; }; #endif /* __ASM_ARCH_TMU_H */ diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c index 9a093a5..de3ff82 100644 --- a/drivers/power/exynos-tmu.c +++ b/drivers/power/exynos-tmu.c @@ -31,7 +31,13 @@ #define INTEN_RISE0 1 #define INTEN_RISE1 (1 << 4) #define INTEN_RISE2 (1 << 8) + +#ifdef CONFIG_EXYNOS5250 +#define INTEN_FALL0 (1 << 12) +#else #define INTEN_FALL0 (1 << 16) +#endif + #define INTEN_FALL1 (1 << 20) #define INTEN_FALL2 (1 << 24) @@ -43,9 +49,24 @@ #define INTCLEAR_FALL0 (1 << 16) #define INTCLEAR_FALL1 (1 << 20) #define INTCLEAR_FALL2 (1 << 24) + +#ifdef CONFIG_EXYNOS5260 +#define INTEN_RISE3 (1 << 12) +#define INTEN_FALL3 (1 << 28) +#define INTCLEAR_RISE3 (1 << 12) +#define INTCLEAR_FALL3 (1 << 28) +#endif + +#if defined(INTCLEAR_RISE3) && defined(INTCLEAR_FALL3) #define INTCLEARALL (INTCLEAR_RISE0 | INTCLEAR_RISE1 | \ - INTCLEAR_RISE2 | INTCLEAR_FALL0 | \ - INTCLEAR_FALL1 | INTCLEAR_FALL2) + INTCLEAR_RISE2 | INTCLEAR_RISE3 | \ + INTCLEAR_FALL0 | INTCLEAR_FALL1 | \ + INTCLEAR_FALL2 | INTCLEAR_FALL3) +#else +#define INTCLEARALL (INTCLEAR_RISE0 | INTCLEAR_RISE1 | \ + INTCLEAR_RISE2 | INTCLEAR_FALL0 | \ + INTCLEAR_FALL1 | INTCLEAR_FALL2) +#endif /* Tmeperature threshold values for various thermal events */ struct temperature_params { -- 1.7.10.4

3 3

[U-Boot] [PATCH] T4240: Address T4240/T4160 Rev2.0 DDR clock change
by Roy Zang 05 Dec '13

05 Dec '13

MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> Reviewed-by: Yusong Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 1a58a19..46ae80c 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) + if (SVR_MAJ(get_svr()) >= 2) + mem_pll_rat *= 2; +#endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; else -- 1.7.9.5

2 1

[U-Boot] [PATCH][v3] powerpc: spiflash:Add corenet devices support in eSPI SPL
by Priyanka Jain 05 Dec '13

05 Dec '13

Existing eSPI SPL framework assumes booting from spi-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Changes for v3: Send as independent patch (not as part of patch set) Changes for v2: Updated description based on Sun York's inputs drivers/mtd/spi/fsl_espi_spl.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 6263d8c..e5ac79b 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -31,6 +31,10 @@ void spi_boot(void) hang(); } +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; +#else /* * Load U-Boot image from SPI flash into RAM */ @@ -50,6 +54,7 @@ void spi_boot(void) code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); /* Skip spl code */ code_len = code_len - CONFIG_SPL_MAX_SIZE; +#endif /* copy code to DDR */ spi_flash_read(flash, offset, code_len, (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); -- 1.7.4.1

2 1

[U-Boot] [PATCH] powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
by Po Liu 05 Dec '13

05 Dec '13

Currently, there is only one EEPROM on c29xpcie board which isAT24C1024. We program the SPD data at beginning of the AT24C1024.But the AT24C1024 has a 16-bit sub-address mode. This patch is tomake it work when getting SPD in a 16-bit sub-address EEPROM. Signed-off-by: Po Liu <Po.Liu(a)freescale.com> --- board/freescale/c29xpcie/ddr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index 3337d6c..28f1bd2 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -84,3 +84,15 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; } } + +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} -- 1.8.0

3 5

[U-Boot] [PATCH] powerpc/p1010rdb:modify the mtest start_address
by Zhao Qiang 05 Dec '13

05 Dec '13

In new board P1010RDB-PB, the interrupt vector table is at the start of memory. So if the start_address needs to be set a proper value. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- include/configs/P1010RDB.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c1cfbd4..e0fb4c1 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -173,7 +173,7 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ -- 1.8.4

2 1

[U-Boot] [PATCH] powerpc/corenet: CPC1 speculation disable
by shh.xie＠gmail.com 05 Dec '13

05 Dec '13

From: Dave Liu <daveliu(a)freescale.com> In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable CPC1 speculation and keep it till relocation. Otherwise, speculation transactions will go to DDR controller, it will cause problem. Signed-off-by: Dave Liu <daveliu(a)freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/start.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6a81fa7..db84d10 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -886,7 +886,11 @@ delete_ccsr_l2_tlb: erratum_set_dcsr 0xb0008 0x00900000 erratum_set_dcsr 0xb0e40 0xe00a0000 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY +#ifdef CONFIG_RAMBOOT_PBL + erratum_set_ccsr 0x10f00 0x495e5000 +#else erratum_set_ccsr 0x10f00 0x415e5000 +#endif erratum_set_ccsr 0x11f00 0x415e5000 /* Make temp mapping uncacheable again, if it was initially */ -- 1.8.0

2 1

[U-Boot] [PATCH V2] arm: omap3: Enable clocks for peripherals only if they are used
by Michael Trimarchi 04 Dec '13

04 Dec '13

This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> Cc: Igor Grinberg <grinberg(a)compulab.co.il> Cc: Tom Rini <trini(a)ti.com> --- Changes in V2: add a better comment for describe the problems that could be raised on some boards arch/arm/cpu/armv7/omap3/clock.c | 2 -- arch/arm/include/asm/arch-omap3/clock.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 14fc7e8..1bc27bd 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -730,8 +730,6 @@ void per_clocks_enable(void) sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); } - sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); - sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON); sdelay(1000); } diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index be669c1..1912cc9 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -27,8 +27,6 @@ #define ICK_DSS_ON 0x00000001 #define FCK_CAM_ON 0x00000001 #define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff /* Used to index into DPLL parameter tables */ typedef struct { -- 1.8.1.2

3 2

[U-Boot] [PATCH] am3517_evm: activate Ethernet PHY
by yegorslists＠googlemail.com 04 Dec '13

04 Dec '13

From: Yegor Yefremov <yegorslists(a)googlemail.com> Pin 30 is connected to PHY's RESET# signal, so it must be put to high. Otherwize PHY won't be found via MDIO interface. Signed-off-by: Yegor Yefremov <yegorslists(a)googlemail.com> --- board/logicpd/am3517evm/am3517evm.c | 34 ++++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/am3517evm.h | 2 +- 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 1569905..80f7de0 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -22,6 +22,7 @@ #include <asm/arch/musb.h> #include <asm/mach-types.h> #include <asm/errno.h> +#include <asm/gpio.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <linux/usb/musb.h> @@ -31,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define AM3517_IP_SW_RESET 0x48002598 +#define CPGMACSS_SW_RST (1 << 1) + /* * Routine: board_init * Description: Early hardware init. @@ -98,6 +102,9 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { + volatile unsigned int ctr; + u32 reset; + #ifdef CONFIG_SYS_I2C_OMAP34XX i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif @@ -106,6 +113,33 @@ int misc_init_r(void) am3517_evm_musb_init(); +#if defined(CONFIG_DRIVER_TI_EMAC) + /* activate PHY reset */ + gpio_direction_output(30, 0); + gpio_set_value(30, 0); + + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* deactivate PHY reset */ + gpio_set_value(30, 1); + + /* allow the PHY to stabilize and settle down */ + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* ensure that the module is out of reset */ + reset = readl(AM3517_IP_SW_RESET); + reset &= (~CPGMACSS_SW_RST); + writel(reset,AM3517_IP_SW_RESET); +#endif + return 0; } diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 704af84..d407d66 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ /*SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ /* - GPIO30 */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ /* - PEN_IRQ */\ -- 1.7.7

2 1

[U-Boot] [[PATCH]pandaboard: 0/1] Modification of Elpida DDR2 RAM for Pandaboard-ES Rev B3
by Hardik 04 Dec '13

04 Dec '13

From: Hardik Patel <hardik.patel(a)volansystech.com> This patch adds Elpida DDR2 RAM support for Pandaboard-ES Rev-B3 board.Enable automatic sdram detection in pandaboard defconfig, so that Elpida DDR2 RAM gets detected on Pandaboard-ES Rev-B3 board. We verified that u-boot works on Panadaboard-ES Rev-B2 board with this patch. Hardik Patel (1): Modification of Elpida DDR2 RAM for Pandaboard-ES Rev B3 include/configs/omap4_common.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 1.7.9.5

8 23

[U-Boot] [PATCH] davinci: fix Master Priority Registers location
by Viktar Palstsiuk 04 Dec '13

04 Dec '13

MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at 0x01C14114 Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk(a)promwad.com> --- arch/arm/include/asm/arch-davinci/hardware.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 7aaf4bf..27b1844 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -478,8 +478,9 @@ struct davinci_syscfg_regs { dv_reg rsvd[13]; dv_reg kick0; dv_reg kick1; - dv_reg rsvd1[53]; + dv_reg rsvd1[52]; dv_reg mstpri[3]; + dv_reg rsvd2; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; -- 1.8.4.3

2 1