November 2013 - U-Boot

[U-Boot] [PATCH v2] net: Add fixed phy driver
by Christian Gmeiner 10 Dec '13

10 Dec '13

This patch is needed if the MAC is directly connected to a ethernet switch. In my case the FEC MAC is connected to a Micrel KSZ8895. All I need to to is configure my fixed phy/link like: #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE MII100 #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0x5 #define CONFIG_PHYLIB #define CONFIG_PHY_FIXED #define CONFIG_PHY_FIXED_SPEED SPEED_100 #define CONFIG_PHY_FIXED_DUPLEX DUPLEX_FULL Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/fixed.c | 34 ++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 +++ 3 files changed, 38 insertions(+) create mode 100644 drivers/net/phy/fixed.c diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index fe762e9..17e486f 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -19,6 +19,7 @@ COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o +COBJS-$(CONFIG_PHY_FIXED) += fixed.o COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o COBJS-$(CONFIG_PHY_LXT) += lxt.o COBJS-$(CONFIG_PHY_MARVELL) += marvell.o diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c new file mode 100644 index 0000000..70ff7bb --- /dev/null +++ b/drivers/net/phy/fixed.c @@ -0,0 +1,34 @@ +/* + * Fixed PHY driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2013 Bachmann electronic GmbH + * author Gmeiner Christian + */ +#include <config.h> +#include <common.h> +#include <phy.h> + +int fixed_config(struct phy_device *phydev) +{ + phydev->link = 1; + phydev->duplex = CONFIG_PHY_FIXED_SPEED; + phydev->speed = CONFIG_PHY_FIXED_DUPLEX; + + return 0; +} + +static struct phy_driver fixed_driver = { + .uid = 0xffffffff, + .mask = 0x00000000, + .name = "Fixed PHY", + .features = 0, + .config = &fixed_config, +}; + +int phy_fixed_init(void) +{ + phy_register(&fixed_driver); + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 62925bb..f2bccaf 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -479,6 +479,9 @@ int phy_init(void) #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif +#ifdef CONFIG_PHY_FIXED + phy_fixed_init(); +#endif return 0; } -- 1.7.10.4

3 3

[U-Boot] [PATCH] powerpc/mpc85xx: Add support for single source clocking
by Priyanka Jain 09 Dec '13

09 Dec '13

Single-source clocking is new feature introduced in T1040. In this mode, a differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-sourec clocking whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 20 ++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 3 +++ 3 files changed, 24 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 1a58a19..cd49695 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -77,7 +77,27 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_systembus = sysclk; #ifdef CONFIG_DDR_CLK_FREQ +#ifdef CONFIG_SINGLE_SOURCE_CLK + /* + * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS + * are driven by separate DDR Refclock or single source + * differential clock. + */ + uint single_src; + single_src = (in_be32(&gur->rcwsr[5]) >> + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; + /* + * For single source clocking, both ddrclock and syclock + * are driven by differential sysclock. + */ + if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; + else + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#endif #else sys_info->freq_ddrbus = sysclk; #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 99e16bd..370bd21 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 672e8c6..68c3c82 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 -- 1.7.4.1

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[U-Boot] [PATCH v5] at91: add support for CDU9G25 board
by Jiri Prchal 09 Dec '13

09 Dec '13

This patch adds support for our companies board CDU9G25 with Atmel AT91SAM9G25, 128MB DDR2, 256MB NAND. Signed-off-by: Jiri Prchal <jiri.prchal(a)aksignal.cz> --- v.2 Fixed static IP and MAC addr cofiguration by random MAC and DHCP. Added entry to MAINTAINERS. Fixed line lenght, trailing spaces and other cosmetics. v.3 Removed static eth_gadget addresses. MAC address set from serial number of F-RAM. v.4 Changed debug to printf if used random MAC addr, print that addr. Keep MAC addr set in enviroment. v.5 Changes to Bo Shen comments. Signed-off-by: Jiri Prchal <jiri.prchal(a)aksignal.cz> --- arch/arm/include/asm/mach-types.h | 1 + board/AKsignal/cdu9g25/Makefile | 34 ++++++ board/AKsignal/cdu9g25/cdu9g25.c | 202 +++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/cdu9g25.h | 210 +++++++++++++++++++++++++++++++++++++ 5 files changed, 448 insertions(+) create mode 100644 board/AKsignal/cdu9g25/Makefile create mode 100644 board/AKsignal/cdu9g25/cdu9g25.c create mode 100644 include/configs/cdu9g25.h diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041..9b274ba 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -986,6 +986,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_VIT_IBOX 3371 #define MACH_TYPE_DM6441_ESP 3372 #define MACH_TYPE_AT91SAM9X5EK 3373 +#define MACH_TYPE_CDU9G25 3373 #define MACH_TYPE_LIBRA 3374 #define MACH_TYPE_EASYCRRH 3375 #define MACH_TYPE_TRIPEL 3376 diff --git a/board/AKsignal/cdu9g25/Makefile b/board/AKsignal/cdu9g25/Makefile new file mode 100644 index 0000000..b644a83 --- /dev/null +++ b/board/AKsignal/cdu9g25/Makefile @@ -0,0 +1,34 @@ +# +# U-boot - Makefile +# +# (C) Copyright 2013 +# Jiri Prchal <jiri.prchal(a)aksignal.cz> +# AK signal <www.aksignal.cz> +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += cdu9g25.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/AKsignal/cdu9g25/cdu9g25.c b/board/AKsignal/cdu9g25/cdu9g25.c new file mode 100644 index 0000000..7321a02 --- /dev/null +++ b/board/AKsignal/cdu9g25/cdu9g25.c @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2013 + * Jiri Prchal <jiri.prchal(a)aksignal.cz> + * AK signal <www.aksignal.cz> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <atmel_hlcdc.h> +#include <atmel_mci.h> +#include <spi.h> +#include <net.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void cdu9g25_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs); + if (bus < 2 && cs < 4) + return 1; + + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs); + at91_set_pio_output(AT91_PIO_PORTA, 23, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs); + at91_set_pio_output(AT91_PIO_PORTA, 23, 1); +} + +void cdu9g25_spi0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + at91_set_pio_output(AT91_PIO_PORTA, 23, 1); +} + +void cdu9g25_init_enetaddr(void) +{ + struct spi_slave *slave; + uchar sernum[9]; + int ret; + + if (eth_getenv_enetaddr("ethaddr", sernum)) + return; + + slave = spi_setup_slave(0, 3, 1000000, SPI_MODE_0); + if (!slave) { + debug("Failed to set up FRAM slave\n"); + goto err_spi_setup_slave; + } + + ret = spi_claim_bus(slave); + if (ret) { + debug("Failed to claim SPI bus: %d\n", ret); + goto err_spi_claim_bus; + } + + *sernum = 0xc3; /* opcode to read serial number */ + ret = spi_xfer(slave, sizeof(sernum) * 8, sernum, sernum, + SPI_XFER_BEGIN | SPI_XFER_END); + if (ret) { + debug("Failed to read serial#: %d\n", ret); + goto err_spi_xfer; + } + + memmove(sernum + 1, sernum + 3, 6); + *sernum = 0x02; + +err_spi_xfer: + spi_release_bus(slave); +err_spi_claim_bus: + spi_free_slave(slave); +err_spi_setup_slave: + if (!is_valid_ether_addr(sernum)) { + eth_random_enetaddr(sernum); + printf("Using random MAC address %pM\n", sernum); + } + eth_setenv_enetaddr("ethaddr", sernum); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + cdu9g25_init_enetaddr(); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); + + return rc; +} + +static void cdu9g25_led_init(void) +{ + at91_set_gpio_output(CONFIG_LED_B, 1); + at91_set_gpio_value(CONFIG_LED_B, 0); +} + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_CDU9G25; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + cdu9g25_led_init(); + + cdu9g25_nand_hw_init(); + + cdu9g25_spi0_hw_init(); + + at91_macb_hw_init(); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif + diff --git a/boards.cfg b/boards.cfg index dbd8479..7a7d39e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -77,6 +77,7 @@ Active arm arm926ejs - armltd integrator Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla(a)marvell.com> Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav(a)einfochips.com> Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin(a)ossfans.org> +Active arm arm926ejs at91 AKsignal cdu9g25 cdu9g25 - Jiri Prchal <jiri.prchal(a)aksignal.cz> Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian(a)popies.net> Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian(a)popies.net> Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian(a)popies.net> diff --git a/include/configs/cdu9g25.h b/include/configs/cdu9g25.h new file mode 100644 index 0000000..a4189cc --- /dev/null +++ b/include/configs/cdu9g25.h @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2013 + * Jiri Prchal <jiri.prchal(a)aksignal.cz> + * AK signal <www.aksignal.cz> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#define CONFIG_AT91SAM9X5 +#include <asm/hardware.h> + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CONFIG_SYS_HZ 1000 + +/* Define actual evaluation board type from used processor type */ +#define CONFIG_CDU9G25 +#define CONFIG_AT91FAMILY +#define CONFIG_IDENT_STRING "_cdu9g25" + +/* Misc CPU related */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* LEDs */ +#define CONFIG_LED_R AT91_PIN_PB18 +#define CONFIG_LED_G AT91_PIN_PB16 +#define CONFIG_LED_Y AT91_PIN_PB14 +#define CONFIG_LED_B AT91_PIN_PB12 + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME 600 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_AT91SAM9_WATCHDOG + +/* SPI */ +#define CONFIG_ATMEL_SPI +#define CONFIG_CMD_SPI + +/* RAMTRON FRAM */ +#define CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */ +#define CONFIG_SPI_FLASH /* RAMTRON FRAM on SPI bus */ +#define CONFIG_SPI_FRAM_RAMTRON + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT + +/* + * SDRAM: 1 bank, 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_SYS_TEXT_BASE 0x27f00000 + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024\ + - GENERATED_GBL_DATA_SIZE) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 + +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_NAND_TRIMFFS +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:256k(bootstrap),"\ + "768k(uboot),256k(ubootenv),"\ + "4864k(kernel),"\ + "-(root)" + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RANDOM_MACADDR + +/* USB */ +#ifdef CONFIG_CMD_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#else +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif +#define CONFIG_USB_ATMEL +#define CONFIG_USB_STORAGE +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_TEXT_BASE + +/* CONFIG_SYS_USE_NANDFLASH */ +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128kB */ +#define CONFIG_ENV_RANGE 0x40000 /* 2 sectors for bad sector handling */ +#define CONFIG_BOOTCOMMAND "nand read 21000000 kernel; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 ubi.mtd=root "\ + "root=ubi0:root rootfstype=ubifs rw" +#define CONFIG_SERVERIP 10.0.1.1 +#define CONFIG_BOOTFILE "kernel_cdu9g25" +#define CONFIG_PREBOOT "mtdparts default" /* for partitions */ + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)\ + + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + CONFIG_ENV_SIZE) + +#endif -- 1.7.9.5

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[U-Boot] [PATCH] arm: at91: support for the Calao USB-A9263 board (based on AT91SAM9263)
by Mateusz Kulikowski 09 Dec '13

09 Dec '13

Add support for USB-A9263 board manufactured by Calao Systems (http://www.calao-systems.com/). Code is based on old U-Boot sources (2010.09) released by Calao and existing AT92SAM9263-EK code. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> --- board/calao/usb_a9263/Makefile | 35 ++++++++ board/calao/usb_a9263/partition.c | 25 ++++++ board/calao/usb_a9263/usb_a9263.c | 158 ++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/usb_a9263.h | 175 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 394 insertions(+) create mode 100644 board/calao/usb_a9263/Makefile create mode 100644 board/calao/usb_a9263/partition.c create mode 100644 board/calao/usb_a9263/usb_a9263.c create mode 100644 include/configs/usb_a9263.h diff --git a/board/calao/usb_a9263/Makefile b/board/calao/usb_a9263/Makefile new file mode 100644 index 0000000..211752c --- /dev/null +++ b/board/calao/usb_a9263/Makefile @@ -0,0 +1,35 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian(a)popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2013 +# Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += usb_a9263.o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/calao/usb_a9263/partition.c b/board/calao/usb_a9263/partition.c new file mode 100644 index 0000000..17cbbf0 --- /dev/null +++ b/board/calao/usb_a9263/partition.c @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2008-2009 + * Ulf Samuelsson <ulf(a)atmel.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00004000, 0xFFFFFFFF, FLAG_PROTECT_SET, 0, "U-Boot"}, +}; diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c new file mode 100644 index 0000000..54c7671 --- /dev/null +++ b/board/calao/usb_a9263/usb_a9263.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2007-2013 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hardware.h> +#if defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void usb_a9263_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void usb_a9263_macb_hw_init(void) +{ + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; + at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; + + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(1 << 25, &pio->pioc.pudr); + writel((1 << 25) | (1 << 26), &pio->pioe.pudr); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + /* Re-enable pull-up */ + writel(1 << 25, &pio->pioc.puer); + writel((1 << 25) | (1 << 26), &pio->pioe.puer); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* arch number of USB-A9263-Board */ + gd->bd->bi_arch_number = MACH_TYPE_USB_A9263; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + usb_a9263_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */ + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + usb_a9263_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + (void)bis; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/boards.cfg b/boards.cfg index 56af102..601482a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -119,6 +119,7 @@ Active arm arm926ejs at91 calao tny_a9260 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre(a)free-electrons.com> Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre(a)free-electrons.com> +Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info(a)egnite.de> Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h new file mode 100644 index 0000000..1d36795 --- /dev/null +++ b/include/configs/usb_a9263.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2007-2013 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> + * + * Settings for Calao USB-A9263 board + * + * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap + * installed on board will not be able to load it properly. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/hardware.h> + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CALAO_USB_A9263 1 /* Calao USB A 9263 Board */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO 1 + +/* serial console */ +#define CONFIG_ATMEL_USART 1 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 + +/* LCD */ +#undef CONFIG_LCD + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_NFS +/* + * U-Boot with enabled USB stack is too big to load properly on default + * at91bootstrap. + */ +#undef CONFIG_CMD_USB + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define AT91_SPI_CLK 8000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY 1 +#define CONFIG_ETHADDR 00:0D:00:0D:00:AB + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000) +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_BOOTCOMMAND "nboot 21000000 0" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"\ + "rw rootfstype=jffs2" + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif -- 1.8.4.1

4 19

[U-Boot] [RFC PATCH 0/3] at91: remove legacy gpio API
by Andreas Bießmann 09 Dec '13

09 Dec '13

This RFC is to remove the need for legacy at91 gpio API in favor of switching to generic gpio API. Please comment, especially on new gpio macros. Andreas Bießmann (3): at91: add new gpio pin macros at91sam9263ek: remove ATMEL_LEGACY at91: use generic gpio API for AT91_LED arch/arm/cpu/arm926ejs/at91/led.c | 43 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-at91/gpio.h | 34 ++++++++++++++++++++++---- board/atmel/at91sam9263ek/led.c | 12 +++------ include/configs/at91sam9263ek.h | 13 +++++----- 4 files changed, 82 insertions(+), 20 deletions(-) -- 1.7.10.4

6 20

[U-Boot] [PATCH] i2c: s3c24xx: add hsi2c controller support
by Naveen Krishna Chatradhi 09 Dec '13

09 Dec '13

Add support for hsi2c controller available on exynos5420. Note: driver currently supports only fast speed mode 100kbps Signed-off-by: Naveen Krishna Chatradhi <ch.naveen(a)samsung.com> Signed-off-by: R. Chandrasekar <rc.sekar(a)samsung.com> --- drivers/i2c/s3c24x0_i2c.c | 389 ++++++++++++++++++++++++++++++++++++++++++--- drivers/i2c/s3c24x0_i2c.h | 33 ++++ 2 files changed, 397 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 769a2ba..3117ab7 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -32,6 +32,7 @@ #include <asm/arch/clk.h> #include <asm/arch/cpu.h> #include <asm/arch/pinmux.h> +#include <asm/arch/clock.h> #else #include <asm/arch/s3c24x0_cpu.h> #endif @@ -50,6 +51,60 @@ #define I2C_NOK_LA 3 /* Lost arbitration */ #define I2C_NOK_TOUT 4 /* time out */ +/* HSI2C specific register description */ + +/* I2C_CTL Register bits */ +#define HSI2C_FUNC_MODE_I2C (1u << 0) +#define HSI2C_MASTER (1u << 3) +#define HSI2C_RXCHON (1u << 6) /* Write/Send */ +#define HSI2C_TXCHON (1u << 7) /* Read/Receive */ +#define HSI2C_SW_RST (1u << 31) + +/* I2C_FIFO_CTL Register bits */ +#define HSI2C_RXFIFO_EN (1u << 0) +#define HSI2C_TXFIFO_EN (1u << 1) +#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) +#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) + +/* I2C_TRAILING_CTL Register bits */ +#define HSI2C_TRAILING_COUNT (0xff) + +/* I2C_INT_EN Register bits */ +#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) +#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) +#define HSI2C_INT_TRAILING_EN (1u << 6) +#define HSI2C_INT_I2C_EN (1u << 9) + +/* I2C_CONF Register bits */ +#define HSI2C_AUTO_MODE (1u << 31) +#define HSI2C_10BIT_ADDR_MODE (1u << 30) +#define HSI2C_HS_MODE (1u << 29) + +/* I2C_AUTO_CONF Register bits */ +#define HSI2C_READ_WRITE (1u << 16) +#define HSI2C_STOP_AFTER_TRANS (1u << 17) +#define HSI2C_MASTER_RUN (1u << 31) + +/* I2C_TIMEOUT Register bits */ +#define HSI2C_TIMEOUT_EN (1u << 31) + +/* I2C_TRANS_STATUS register bits */ +#define HSI2C_MASTER_BUSY (1u << 17) +#define HSI2C_SLAVE_BUSY (1u << 16) +#define HSI2C_NO_DEV (1u << 3) +#define HSI2C_NO_DEV_ACK (1u << 2) +#define HSI2C_TRANS_ABORT (1u << 1) +#define HSI2C_TRANS_DONE (1u << 0) +#define HSI2C_TIMEOUT_AUTO (0u << 0) + +#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) + +/* Controller operating frequency, timing values for operation + * are calculated against this frequency + */ +#define HSI2C_FS_TX_CLOCK 1000000 + +/* S3C I2C Controller bits */ #define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ @@ -61,6 +116,7 @@ #define I2C_TIMEOUT 1 /* 1 second */ +#define HSI2C_TIMEOUT 100 /* * For SPL boot some boards need i2c before SDRAM is initialised so force @@ -120,9 +176,23 @@ static int WaitForXfer(struct s3c24x0_i2c *i2c) return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; } -static int IsACK(struct s3c24x0_i2c *i2c) +static int hsi2c_wait_for_irq(struct exynos5_hsi2c *i2c) { - return !(readl(&i2c->iicstat) & I2CSTAT_NACK); + int i = HSI2C_TIMEOUT * 10; + int ret = I2C_NOK_TOUT; + + while (i > 0) { + /* wait for a while and retry */ + udelay(50); + if (readl(&i2c->usi_int_stat) & + (HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN)) { + ret = I2C_OK; + break; + } + i--; + } + + return ret; } static void ReadWriteByte(struct s3c24x0_i2c *i2c) @@ -130,6 +200,22 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c) writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } +static void hsi2c_clear_irqpd(struct exynos5_hsi2c *i2c) +{ + writel(readl(&i2c->usi_int_stat), &i2c->usi_int_stat); +} + +static int hsi2c_isack(struct exynos5_hsi2c *i2c) +{ + return readl(&i2c->usi_trans_status) & + (HSI2C_NO_DEV | HSI2C_NO_DEV_ACK); +} + +static int IsACK(struct s3c24x0_i2c *i2c) +{ + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); +} + static struct s3c24x0_i2c *get_base_i2c(void) { #ifdef CONFIG_EXYNOS4 @@ -147,6 +233,18 @@ static struct s3c24x0_i2c *get_base_i2c(void) #endif } +static struct exynos5_hsi2c *get_base_hsi2c(void) +{ + struct exynos5_hsi2c *i2c = NULL; + int bus = g_current_bus; + + if (proid_is_exynos5420()) + i2c = (struct exynos5_hsi2c *)(EXYNOS5420_I2C_BASE + + ((bus) * EXYNOS5_I2C_SPACING)); + + return i2c; +} + static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) { ulong freq, pres = 16, div; @@ -174,6 +272,74 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } +static void hsi2c_ch_init(struct exynos5_hsi2c *i2c, int speed) +{ + u32 i2c_timeout; + ulong clkin = get_i2c_clk(); + u32 i2c_timing_s1; + u32 i2c_timing_s2; + u32 i2c_timing_s3; + u32 i2c_timing_sla; + unsigned int op_clk = HSI2C_FS_TX_CLOCK; + unsigned int n_clkdiv; + unsigned int t_start_su, t_start_hd; + unsigned int t_stop_su; + unsigned int t_data_su, t_data_hd; + unsigned int t_scl_l, t_scl_h; + unsigned int t_sr_release; + unsigned int t_ftl_cycle; + unsigned int i = 0, utemp0 = 0, utemp1 = 0, utemp2 = 0; + + /* FPCLK / FI2C = + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE + * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + * uTemp1 = (TSCLK_L + TSCLK_H + 2) + * uTemp2 = TSCLK_L + TSCLK_H + */ + t_ftl_cycle = (readl(&i2c->usi_conf) >> 16) & 0x7; + utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; + + /* CLK_DIV max is 256 */ + for (i = 0; i < 256; i++) { + utemp1 = utemp0 / (i + 1); + /* SCLK_L/H max is 256 / 2 */ + if (utemp1 < 128) { + utemp2 = utemp1 - 2; + break; + } + } + + n_clkdiv = i; + t_scl_l = utemp2 / 2; + t_scl_h = utemp2 / 2; + t_start_su = t_scl_l; + t_start_hd = t_scl_l; + t_stop_su = t_scl_l; + t_data_su = t_scl_l / 2; + t_data_hd = t_scl_l / 2; + t_sr_release = utemp2; + + i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; + i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; + i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; + i2c_timing_sla = t_data_hd << 0; + + writel(HSI2C_TRAILING_COUNT, &i2c->usi_trailing_ctl); + + /* Clear to enable Timeout */ + i2c_timeout = readl(&i2c->usi_timeout); + i2c_timeout &= ~HSI2C_TIMEOUT_EN; + writel(i2c_timeout, &i2c->usi_timeout); + + writel(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* Currently operating in Fast speed mode. */ + writel(i2c_timing_s1, &i2c->usi_timing_fs1); + writel(i2c_timing_s2, &i2c->usi_timing_fs2); + writel(i2c_timing_s3, &i2c->usi_timing_fs3); + writel(i2c_timing_sla, &i2c->usi_timing_sla); +} + /* * MULTI BUS I2C support */ @@ -181,16 +347,18 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) #ifdef CONFIG_I2C_MULTI_BUS int i2c_set_bus_num(unsigned int bus) { - struct s3c24x0_i2c *i2c; - if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { debug("Bad bus: %d\n", bus); return -1; } g_current_bus = bus; - i2c = get_base_i2c(); - i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (proid_is_exynos5420() && (bus > 3)) { + hsi2c_ch_init(get_base_hsi2c(), + CONFIG_SYS_I2C_SPEED); + } else + i2c_ch_init(get_base_i2c(), CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE); return 0; } @@ -269,24 +437,182 @@ void i2c_init(int speed, int slaveadd) } /* + * Send a STOP event and wait for it to have completed + * + * @param mode If it is a master transmitter or receiver + * @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise + */ +static int hsi2c_send_stop(struct exynos5_hsi2c *i2c, int result) +{ + int timeout; + int ret = I2C_NOK_TOUT; + + /* Wait for the STOP to send and the bus to go idle */ + for (timeout = HSI2C_TIMEOUT; timeout > 0; timeout -= 5) { + if (!(readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY)) { + ret = I2C_OK; + goto out; + } + udelay(5); + } + out: + /* Setting the STOP event to fire */ + writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); + writel(0x0, &i2c->usi_int_en); + + return (result == I2C_OK) ? ret : result; +} + +static int hsi2c_write(unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len) +{ + struct exynos5_hsi2c *i2c = get_base_hsi2c(); + int i = 0, result = I2C_OK; + u32 i2c_auto_conf; + u32 stat; + + /* Check I2C bus idle */ + i = HSI2C_TIMEOUT * 20; + while ((readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) + && (i > 0)) { + udelay(50); + i--; + } + + stat = readl(&i2c->usi_trans_status); + + if (stat & HSI2C_MASTER_BUSY) { + debug("%s: bus busy\n", __func__); + return I2C_NOK_TOUT; + } + /* Disable TXFIFO and RXFIFO */ + writel(0, &i2c->usi_fifo_ctl); + + /* chip address */ + writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); + + /* Enable interrupts */ + writel((HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN), + &i2c->usi_int_en); + + /* usi_ctl enable i2c func, master write configure */ + writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* i2c_conf configure */ + writel(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* auto_conf for write length and stop configure */ + i2c_auto_conf = ((len + alen) | HSI2C_STOP_AFTER_TRANS); + i2c_auto_conf &= ~HSI2C_READ_WRITE; + writel(i2c_auto_conf, &i2c->usi_auto_conf); + + /* Master run, start xfer */ + writel(readl(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, + &i2c->usi_auto_conf); + + result = hsi2c_wait_for_irq(i2c); + if ((result == I2C_OK) && hsi2c_isack(i2c)) { + result = I2C_NACK; + goto err; + } + + for (i = 0; i < alen && (result == I2C_OK); i++) { + writel(addr[i], &i2c->usi_txdata); + result = hsi2c_wait_for_irq(i2c); + } + + for (i = 0; i < len && (result == I2C_OK); i++) { + writel(data[i], &i2c->usi_txdata); + result = hsi2c_wait_for_irq(i2c); + } + + err: + hsi2c_clear_irqpd(i2c); + return hsi2c_send_stop(i2c, result); +} + +static int hsi2c_read(unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len, + int check) +{ + struct exynos5_hsi2c *i2c = get_base_hsi2c(); + int i, result; + u32 i2c_auto_conf; + + if (!check) { + result = hsi2c_write(chip, addr, alen, data, 0); + if (result != I2C_OK) { + debug("write failed Result = %d\n", result); + return result; + } + } + + /* start read */ + /* Disable TXFIFO and RXFIFO */ + writel(0, &i2c->usi_fifo_ctl); + + /* chip address */ + writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); + + /* Enable interrupts */ + writel(HSI2C_INT_I2C_EN, &i2c->usi_int_en); + + /* i2c_conf configure */ + writel(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* auto_conf, length and stop configure */ + i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE); + writel(i2c_auto_conf, &i2c->usi_auto_conf); + + /* usi_ctl enable i2c func, master WRITE configure */ + writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* Master run, start xfer */ + writel(readl(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, + &i2c->usi_auto_conf); + + result = hsi2c_wait_for_irq(i2c); + if ((result == I2C_OK) && hsi2c_isack(i2c)) { + result = I2C_NACK; + goto err; + } + + for (i = 0; i < len && (result == I2C_OK); i++) { + result = hsi2c_wait_for_irq(i2c); + data[i] = readl(&i2c->usi_rxdata); + } + err: + /* Stop and quit */ + hsi2c_clear_irqpd(i2c); + return hsi2c_send_stop(i2c, result); +} + +/* * cmd_type is 0 for write, 1 for read. * * addr_len can take any value from 0-255, it is only limited * by the char, we could make it larger if needed. If it is * 0 we skip the address write cycle. */ -static int i2c_transfer(struct s3c24x0_i2c *i2c, - unsigned char cmd_type, +static int i2c_transfer(unsigned char cmd_type, unsigned char chip, unsigned char addr[], unsigned char addr_len, unsigned char data[], unsigned short data_len) { + struct s3c24x0_i2c *i2c = get_base_i2c(); int i, result; if (data == 0 || data_len == 0) { - /*Don't support data transfer of no length or to address 0 */ debug("i2c_transfer: bad call\n"); return I2C_NOK; } @@ -428,10 +754,8 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, int i2c_probe(uchar chip) { - struct s3c24x0_i2c *i2c; uchar buf[1]; - i2c = get_base_i2c(); buf[0] = 0; /* @@ -439,12 +763,15 @@ int i2c_probe(uchar chip) * address was <ACK>ed (i.e. there was a chip at that address which * drove the data line low). */ - return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; + if (proid_is_exynos5420() && (g_current_bus > 3)) + return (hsi2c_read(chip, 0, 1, buf, 1, 1) != I2C_OK); + else + return i2c_transfer( + I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; } int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct s3c24x0_i2c *i2c; uchar xaddr[4]; int ret; @@ -476,9 +803,13 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif - i2c = get_base_i2c(); - ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen, - buffer, len); + if (proid_is_exynos5420() && (g_current_bus > 3)) + ret = hsi2c_read(chip, &xaddr[4 - alen], + alen, buffer, len, 0); + else + ret = i2c_transfer(I2C_READ, chip << 1, + &xaddr[4 - alen], alen, buffer, len); + if (ret != 0) { debug("I2c read: failed %d\n", ret); return 1; @@ -488,7 +819,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct s3c24x0_i2c *i2c; uchar xaddr[4]; if (alen > 4) { @@ -518,31 +848,36 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif - i2c = get_base_i2c(); - return (i2c_transfer - (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, - len) != 0); + if (proid_is_exynos5420() && (g_current_bus > 3)) + return (hsi2c_write(chip, &xaddr[4 - alen], + alen, buffer, len) != 0); + else + return (i2c_transfer(I2C_WRITE, chip << 1, + &xaddr[4 - alen], alen, buffer, len) != 0); } #ifdef CONFIG_OF_CONTROL void board_i2c_init(const void *blob) { + struct s3c24x0_i2c_bus *bus; int node_list[CONFIG_MAX_I2C_NUM]; int count, i; count = fdtdec_find_aliases_for_id(blob, "i2c", COMPAT_SAMSUNG_S3C2440_I2C, node_list, CONFIG_MAX_I2C_NUM); - for (i = 0; i < count; i++) { - struct s3c24x0_i2c_bus *bus; int node = node_list[i]; if (node <= 0) continue; bus = &i2c_bus[i]; + bus->regs = (struct s3c24x0_i2c *) - fdtdec_get_addr(blob, node, "reg"); + fdtdec_get_addr(blob, node, "reg"); + bus->hsregs = (struct exynos5_hsi2c *) + fdtdec_get_addr(blob, node, "reg"); + bus->id = pinmux_decode_periph_id(blob, node); bus->node = node; bus->bus_num = i2c_busses++; @@ -589,7 +924,11 @@ int i2c_reset_port_fdt(const void *blob, int node) return -1; } - i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (proid_is_exynos5420() && (bus > 3)) + hsi2c_ch_init(i2c->hsregs, CONFIG_SYS_I2C_SPEED); + else + i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE); return 0; } diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index a56d749..81ed19c 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -31,10 +31,43 @@ struct s3c24x0_i2c { u32 iiclc; }; +struct exynos5_hsi2c { + u32 usi_ctl; + u32 usi_fifo_ctl; + u32 usi_trailing_ctl; + u32 usi_clk_ctl; + u32 usi_clk_slot; + u32 spi_ctl; + u32 uart_ctl; + u32 res1; + u32 usi_int_en; + u32 usi_int_stat; + u32 usi_modem_stat; + u32 usi_error_stat; + u32 usi_fifo_stat; + u32 usi_txdata; + u32 usi_rxdata; + u32 res2; + u32 usi_conf; + u32 usi_auto_conf; + u32 usi_timeout; + u32 usi_manual_cmd; + u32 usi_trans_status; + u32 usi_timing_hs1; + u32 usi_timing_hs2; + u32 usi_timing_hs3; + u32 usi_timing_fs1; + u32 usi_timing_fs2; + u32 usi_timing_fs3; + u32 usi_timing_sla; + u32 i2c_addr; +}; + struct s3c24x0_i2c_bus { int node; /* device tree node */ int bus_num; /* i2c bus number */ struct s3c24x0_i2c *regs; + struct exynos5_hsi2c *hsregs; int id; }; #endif /* _S3C24X0_I2C_H */ -- 1.7.9.5

9 56

[U-Boot] [PATCH] arm: omap3: i2c: don't zero cnt in i2c_write
by Nikita Kiryanov 09 Dec '13

09 Dec '13

The zeroing of I2Ci.I2C_CNT register at the end of i2c_write causes random I2C failures in OMAP3 based devices. This is probably related to the following advisory in OMAP3 errata: I2C Module Does Not Allow 0-Byte Data Requests Details: When configured as the master, the I2C module does not allow 0-byte data transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause undefined behavior. Workaround(s): No workaround. Do not use 0-byte data requests. Make the write conditional so that only non-OMAP3 devices will perform it. Cc: Heiko Schocher <hs(a)denx.de> Signed-off-by: Nikita Kiryanov <nikita(a)compulab.co.il> --- drivers/i2c/omap24xx_i2c.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 3d38c03..2862a8f 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -473,7 +473,10 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, wr_exit: flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); + /* This write is known to cause undefined behavior on OMAP3 */ +#ifndef CONFIG_OMAP34XX writew(0, &i2c_base->cnt); +#endif return i2c_error; } -- 1.8.1.2

8 12

[U-Boot] [PATCH 0/6] adapt s3c24x0 driver to new i2c framework
by Piotr Wilczek 09 Dec '13

09 Dec '13

This patch series adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Boards VCMA9, arndale and exynos5250 are compile tested only. Boards Trats and Trats2 were hardware tested. All boards compile clean. Piotr Wilczek (6): driver:i2c:s3c24x0: adapt driver to new i2c board:arndale: switch to new i2c framework board:VCMA9 switch to new i2c framework board:smdk5250: switch to new i2c framework board:trats: switch to new i2c framework board:trats2: switch Trats2 to new i2c framework board/samsung/smdk5250/exynos5-dt.c | 2 - board/samsung/trats/trats.c | 21 +++-- board/samsung/trats2/trats2.c | 35 ++++++-- drivers/i2c/Makefile | 2 +- drivers/i2c/s3c24x0_i2c.c | 157 ++++++++++++++++++++++------------- include/configs/VCMA9.h | 8 +- include/configs/arndale.h | 9 +- include/configs/exynos5250-dt.h | 8 +- include/configs/trats.h | 25 ++---- include/configs/trats2.h | 29 +++---- 10 files changed, 174 insertions(+), 122 deletions(-) -- 1.7.9.5

3 16

[U-Boot] [PATCH] mmc: add Faraday FTSDC021 SDHCI controller support
by Kuo-Jung Su 08 Dec '13

08 Dec '13

From: Kuo-Jung Su <dantesu(a)faraday-tech.com> Faraday FTSDC021 is a controller which is compliant with SDHCI v3.0, SDIO v2.0 and MMC v4.3. However this driver is only verified with SD memory cards. Signed-off-by: Kuo-Jung Su <dantesu(a)faraday-tech.com> CC: Andy Fleming <afleming(a)gmail.com> --- drivers/mmc/Makefile | 1 + drivers/mmc/ftsdc021_sdhci.c | 33 +++++++++++++++++++++++++++++++++ include/faraday/ftsdc021.h | 13 +++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 drivers/mmc/ftsdc021_sdhci.c create mode 100644 include/faraday/ftsdc021.h diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a7ae38d..1ed26ca 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o +obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o obj-$(CONFIG_GENERIC_MMC) += mmc.o obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o diff --git a/drivers/mmc/ftsdc021_sdhci.c b/drivers/mmc/ftsdc021_sdhci.c new file mode 100644 index 0000000..1f6cdba --- /dev/null +++ b/drivers/mmc/ftsdc021_sdhci.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2013 Faraday Technology + * Kuo-Jung Su <dantesu(a)faraday-tech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <sdhci.h> + +#ifndef CONFIG_FTSDC021_CLOCK +#define CONFIG_FTSDC021_CLOCK clk_get_rate("MMC") +#endif + +int ftsdc021_sdhci_init(u32 regbase) +{ + struct sdhci_host *host = NULL; + uint32_t freq = CONFIG_FTSDC021_CLOCK; + + host = calloc(1, sizeof(struct sdhci_host)); + if (!host) { + puts("sdh_host malloc fail!\n"); + return 1; + } + + host->name = "FTSDC021"; + host->ioaddr = (void __iomem *)regbase; + host->quirks = 0; + add_sdhci(host, freq, 0); + + return 0; +} diff --git a/include/faraday/ftsdc021.h b/include/faraday/ftsdc021.h new file mode 100644 index 0000000..de8e250 --- /dev/null +++ b/include/faraday/ftsdc021.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 Faraday Technology + * Dante Su <dantesu(a)faraday-tech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FTSDC021_H +#define __FTSDC021_H + +int ftsdc021_sdhci_init(u32 regbase); + +#endif /* __FTSDC021_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH][v3] powerpc: mmc: Add corenet devices support in esdhc spl
by Priyanka Jain 08 Dec '13

08 Dec '13

Existing eSDHC SPL framework assumes booting from sd-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Changes for v3: Send as independent patch (not as part of patch set) Changes for v2: Updated description based on Sun York's inputs drivers/mmc/fsl_esdhc_spl.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 65c52a2..8fc263f 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -42,6 +42,10 @@ void __noreturn mmc_boot(void) hang(); } +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_MMC_U_BOOT_OFFS; + code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; +#else blklen = mmc->read_bl_len; tmp_buf = malloc(blklen); if (!tmp_buf) { @@ -91,6 +95,7 @@ void __noreturn mmc_boot(void) /* * Load U-Boot image from mmc into RAM */ +#endif blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; err = mmc->block_dev.block_read(0, blk_start, blk_cnt, -- 1.7.4.1

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