August 2012 - U-Boot

[U-Boot] [PATCH 2/4] mx53_smd: add spi nor support
by Terry Lv 14 Aug '12

14 Aug '12

Add spi nor support to mx53 smd, including iomux, configs, etc. To test spi nor on mx53 smd: MX53SMD U-Boot > sf probe 0:21249 JEDEC ID: 0x202016 m25p32 (4096 Kbytes) SF: Detected m25p32 with page size 0 Bytes, total 4 MiB Here, 21249 is integer of hex 0x5301. 0x01 is cs and 0x53 is active gpio number. Signed-off-by: Terry Lv <r65388(a)freescale.com> --- board/freescale/mx53smd/mx53smd.c | 63 +++++++++++++++++++++++++++++++++++++ include/configs/mx53smd.h | 17 ++++++++++ 2 files changed, 80 insertions(+), 0 deletions(-) diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 87fa7fa..abb1e9b 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -127,6 +127,65 @@ static void setup_iomux_fec(void) PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); } +#ifdef CONFIG_MXC_SPI +static void setup_iomux_spi(u8 bus, u8 ss) +{ + switch (bus) { + case 0: + /* SCLK */ + mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D16, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH); + mxc_iomux_set_input(MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, + 0x3); + + /* MISO */ + mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D17, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH); + mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT, + 0x3); + + /* MOSI */ + mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D18, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH); + mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + 0x3); + + if (0 == ss) { + mxc_request_iomux(MX53_PIN_EIM_EB2, + IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + 0x3); + + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH); + } else if (1 == ss){ + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, + 0x2); + + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH); + } + break; + case 1: + case 2: + default: + break; + } +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {MMC_SDHC1_BASE_ADDR, 1}, @@ -203,6 +262,10 @@ int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); +#if defined(CONFIG_MXC_SPI) && defined(CONFIG_SPI_FLASH) \ + && defined(CONFIG_SPI_FLASH_BUS) && defined(CONFIG_SPI_FLASH_CS) + setup_iomux_spi(CONFIG_SPI_FLASH_BUS, CONFIG_SPI_FLASH_CS); +#endif return 0; } diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 48b32dd..2597562 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -65,6 +65,23 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* SPI Configs*/ +#define CONFIG_CMD_SPI +#define CONFIG_MXC_SPI +#define CONFIG_SPI_VER_2_3 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR +#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR + +/* SPI Flash Configs */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_M25P80 1 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SPI_FLASH_BUS 0 +#define CONFIG_SPI_FLASH_CS 1 + /* Eth Configs */ #define CONFIG_HAS_ETH1 #define CONFIG_MII -- 1.7.0.4

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[U-Boot] [PATCH 1/6] powerpc/corenet_ds: Update README.srio-boot-corenet
by Liu Gang 14 Aug '12

14 Aug '12

Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by: Liu Gang <Gang.Liu(a)freescale.com> --- doc/README.srio-boot-corenet | 70 ++++++++++++++++++++---------------------- 1 files changed, 33 insertions(+), 37 deletions(-) diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet index 56b094c..6a13e9c 100644 --- a/doc/README.srio-boot-corenet +++ b/doc/README.srio-boot-corenet @@ -18,7 +18,7 @@ Environment of the SRIO boot: U-Boot images, UCodes will be stored in this flash. d) Slave has its own EEPROM for RCW and PBI. e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores if needed. + location to SRIO, and holdoff all the cores. ---------- ----------- ----------- | | | | | | @@ -30,63 +30,55 @@ Environment of the SRIO boot: The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 0 will be connected directly and will be used for the boot from SRIO. + ports 1 will be connected directly and will be used for the boot from SRIO. - 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. - 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 - 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 - 00000020: f400 0000 0100 0000 0000 0000 0000 0000 - 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 - 00000040: 0000 0000 0000 0000 0813 8040 698b 93fe - - 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 00000020: f440 0000 0100 0000 0000 0000 0000 0000 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 00000040: 0000 0000 0000 0000 0813 8040 063c 778f - 3. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 0 configuration. + 2. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 1 configuration. b) Program slave's U-Boot image, UCode, and ENV parameters into master's NorFlash. - c) Start up master and it will boot up normally from its NorFlash. + c) Set environment variable "bootmaster" to "SRIO1" and save environment + for master. + setenv bootmaster SRIO1 + saveenv + d) Restart up master and it will boot up normally from its NorFlash. Then, it will finish necessary configurations for slave's boot from - SRIO port 0. - d) Master will set inbound SRIO windows covered slave's U-Boot image stored + SRIO port 1. + e) Master will set inbound SRIO windows covered slave's U-Boot image stored in master's NorFlash. - e) Master will set an inbound SRIO window covered slave's UCode stored in - master's NorFlash. - f) Master will set an inbound SRIO window covered slave's ENV stored in - master's NorFlash. - g) If need to release slave's core, master will set outbound SRIO windows - in order to configure slave's registers for the core's releasing. - h) If all cores of slave in holdoff, slave should be powered on before all - the above master's steps, and wait to be released by master. If not all - cores in holdoff, that means core 0 will start up normally, slave should - be powered on after all the above master's steps. In the startup phase - of the slave from SRIO, it will finish some necessary configurations. + f) Master will set an inbound SRIO window covered slave's UCode and ENV + stored in master's NorFlash. + g) Master will set outbound SRIO windows in order to configure slave's + registers for the core's releasing. + h) Since all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master. In the + startup phase of the slave from SRIO, it will finish some necessary + configurations. i) Slave will set a specific TLB entry for the boot process. - j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot. + j) Slave will set a LAW entry with the TargetID SRIO port 1 for the boot. k) Slave will set a specific TLB entry in order to fetch UCode and ENV from master. - l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV. + l) Slave will set a LAW entry with the TargetID SRIO port 1 for UCode and ENV. How to use this feature: - To use this feature, you need to focus three points. + To use this feature, you need to focus those points. 1. Slave's RCW with SRIO boot configurations, and all cores in holdoff - configurations if needed. + configurations. Please refer to the examples given above. 2. U-Boot image's compilation. - For master, U-Boot image should be generated specifically by - - make xxxx_SRIOBOOT_MASTER_config. + For master, U-Boot image should be generated normally. For example, master U-Boot image used on P4080DS should be compiled with - make P4080DS_SRIOBOOT_MASTER_config. + make P4080DS_config. For slave, U-Boot image should be generated specifically by @@ -97,7 +89,11 @@ How to use this feature: make P4080DS_SRIOBOOT_SLAVE_config. 3. Necessary modifications based on a specific environment. - For a specific environment, the SRIO port for boot, the addresses of the - slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other - configurations can be modified in the file: + For a specific environment, the addresses of the slave's U-Boot image, + UCode, ENV stored in master's NorFlash, and any other configurations + can be modified in the file: include/configs/corenet_ds.h. + + 4. Set and save the environment variable "bootmaster" with "SRIO1" or "SRIO2" + for master, and then restart it in order to perform the role as a master + for boot from SRIO. -- 1.7.1

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Re: [U-Boot] Help : Keyboard Enabling at U-boot
by Simon Glass 14 Aug '12

14 Aug '12

Hi, [Please do send to the U-Boot mailing list also] On Fri, Aug 10, 2012 at 2:55 AM, LIVIN SUNNY <livin20(a)gmail.com> wrote: > Hi sir, > > I have an issue regarding u-boot. I'm using Beagle-board Rev B as well > as omap3_evm. i would like to enable keyboard at the u-boot level,i.e the > keyboard is connected to the target and entering the text.But the problem is > that at the U-boot, keyboard is not responding( no lights ) for both the > devices.When i checked the USB info ,the current for keyboard was > 70mA(actual 100mA for keyboard). But after the boot level the keyboard light > blinks and works well and fine. > What will be the reason for lowering the current at the u-boot and > increasing after the initialization of the USB at the kernel level?? Is > there any change i have to make in the U-boot code for beagle board as well > as for the omap3_evm?? I am not sure. It is possible that there is some sort of VBUS control on your board that you need to enable in U-Boot. I haven't really much experience with Beagle board, so perhaps someone on the list will be able to help. If not, I suggest you send to the list again with Beagleboard in the subject. Regards, Simon > > > please help me ........... > > Waiting for your reply. > > > -- > With thanks & regards, > > Livin Sunny > > +91-8123966435 > >

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[U-Boot] [PATCH] mpc85xx: use LCRR_DBYP define instead of raw constant
by Paul Gortmaker 14 Aug '12

14 Aug '12

Using the raw value of 0x80000000 directly in the code can lead to "count the zeros" bugs like that fixed in commit 718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC") Change all existing raw values to use the symbolic value of LCRR_DBYP instead. Cc: Kumar Gala <galak(a)kernel.crashing.org> Cc: Scott Wood <scottwood(a)freescale.com> Signed-off-by: Paul Gortmaker <paul.gortmaker(a)windriver.com> diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index c75585e..a275d3a 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -87,10 +87,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -105,7 +105,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 532d32a..13ca84b 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -269,13 +269,13 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr |= 0x80000000; /* DLL Bypass */ + lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 3361614..4cfd61c 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -267,13 +267,13 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr |= 0x80000000; /* DLL Bypass */ + lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1a165bf..285edbc 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -292,10 +292,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -310,7 +310,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ udelay(200); /* -- 1.7.12.rc1.1.ga9c166e

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[U-Boot] [PATCH v3 4/6] nand_spl: update udelay for Freescale boards
by Matthew McClintock 14 Aug '12

14 Aug '12

Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time. Looked at reusing the u-boot udelay functions but it pulls in a lot of code and would require quite a bit of work to keep us within the very small space constrains we currently have Signed-off-by: Matthew McClintock <msm(a)freescale.com> --- v2: Change global bus_clk to use gd->bus_clk v3: Update commit message a bit Fixed code formatting issues Use proper define for bus divider nand_spl/board/freescale/common.c | 40 +++++++++++++++++++++ nand_spl/board/freescale/p1010rdb/Makefile | 6 +++- nand_spl/board/freescale/p1010rdb/nand_boot.c | 11 +++--- nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 6 +++- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 12 +++---- 5 files changed, 60 insertions(+), 15 deletions(-) create mode 100644 nand_spl/board/freescale/common.c diff --git a/nand_spl/board/freescale/common.c b/nand_spl/board/freescale/common.c new file mode 100644 index 0000000..0e099bc --- /dev/null +++ b/nand_spl/board/freescale/common.c @@ -0,0 +1,40 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Author: Matthew McClintock <msm(a)freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif + +void udelay(unsigned long usec) +{ + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); + + while ((mfspr(SPRN_TBRL) - s) < ticks); +} diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 8d240ea..cdbd492 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o ticks.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index f5294d0..a075509 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -27,8 +27,9 @@ #include <asm/immap_85xx.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_law.h> +#include <asm/global_data.h> -#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); } +DECLARE_GLOBAL_DATA_PTR; unsigned long ddr_freq_mhz; @@ -82,8 +83,7 @@ void sdram_init(void) __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); } - /* mimic 500us delay, with busy isync() loop */ - udelay(100); + udelay(500); /* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); @@ -94,20 +94,19 @@ void sdram_init(void) void board_init_f(ulong bootflag) { u32 plat_ratio, ddr_ratio; - unsigned long bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile index 475cc49..46cf709 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -119,6 +120,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c index b9796ea..fcff382 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c @@ -25,11 +25,9 @@ #include <nand.h> #include <asm/fsl_law.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/global_data.h> -#define udelay(x) {int i, j; \ - for (i = 0; i < x; i++) \ - for (j = 0; j < 10000; j++) \ - ; } +DECLARE_GLOBAL_DATA_PTR; /* * Fixed sdram init -- doesn't use serial presence detect. @@ -76,7 +74,7 @@ void sdram_init(void) void board_init_f(ulong bootflag) { - u32 plat_ratio, bus_clk; + u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); @@ -85,10 +83,10 @@ void board_init_f(ulong bootflag) /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); -- 1.7.9.7

1 0

[U-Boot] Please pull u-boot-ti/master
by Tom Rini 14 Aug '12

14 Aug '12

Hello, The following changes since commit 8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08: DaVinci DA8xx: fix set_cpu_clk_info() (2012-08-05 22:02:40 +0200) are available in the git repository at: git://git.denx.de/u-boot-ti next for you to fetch changes up to a47233a30055660ad64d865f1fde19503ed02696: am335x_evm: enable SMSC PHY driver (2012-08-07 10:07:22 -0700) ---------------------------------------------------------------- Enric Balletbò i Serra (1): OMAP3: fix DRAM size for IGEP-based boards. Ilya Yanok (1): am335x_evm: enable SMSC PHY driver board/isee/igep0020/igep0020.c | 6 +++--- board/isee/igep0030/igep0030.c | 6 +++--- include/configs/am335x_evm.h | 1 + 3 files changed, 7 insertions(+), 6 deletions(-) -- Tom

2 1

[U-Boot] Please pull u-boot-atmel/master
by Andreas Bießmann 14 Aug '12

14 Aug '12

The following changes since commit 8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08: DaVinci DA8xx: fix set_cpu_clk_info() (2012-08-05 22:02:40 +0200) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 17cda15fa6fb3ab2433bed951dad5c4ab30d8cbc: at91: Add support for taskit AT91SAM9G20 boards. (2012-08-07 23:47:29 +0200) ---------------------------------------------------------------- Andreas Bießmann (3): doc/git-mailrc: update at91 and avr32 MAINTAINERS: fix entry of Ilko Iliev MAINTAINERS: fix Andreas Bießmann AVR32 entry Bo Shen (1): arm : Atmel : add at91sam9x5ek board support Markus Hubig (2): Enable the EMAC clock in at91_macb_hw_init(). at91: Add support for taskit AT91SAM9G20 boards. MAINTAINERS | 23 +- arch/arm/cpu/arm926ejs/at91/Makefile | 1 + arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 4 + arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 232 ++++++++++++++++ arch/arm/cpu/arm926ejs/at91/clock.c | 12 +- arch/arm/include/asm/arch-at91/at91sam9_matrix.h | 2 + arch/arm/include/asm/arch-at91/at91sam9x5.h | 170 ++++++++++++ arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h | 91 ++++++ arch/arm/include/asm/arch-at91/hardware.h | 2 + board/atmel/at91sam9x5ek/Makefile | 52 ++++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 293 ++++++++++++++++++++ board/atmel/at91sam9x5ek/config.mk | 1 + board/taskit/stamp9g20/Makefile | 53 ++++ board/taskit/stamp9g20/led.c | 138 +++++++++ board/taskit/stamp9g20/stamp9g20.c | 191 +++++++++++++ boards.cfg | 3 + doc/git-mailrc | 5 +- drivers/net/macb.c | 4 +- include/configs/at91sam9x5ek.h | 183 ++++++++++++ include/configs/stamp9g20.h | 266 ++++++++++++++++++ 20 files changed, 1713 insertions(+), 13 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5.h create mode 100644 arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h create mode 100644 board/atmel/at91sam9x5ek/Makefile create mode 100644 board/atmel/at91sam9x5ek/at91sam9x5ek.c create mode 100644 board/atmel/at91sam9x5ek/config.mk create mode 100644 board/taskit/stamp9g20/Makefile create mode 100644 board/taskit/stamp9g20/led.c create mode 100644 board/taskit/stamp9g20/stamp9g20.c create mode 100644 include/configs/at91sam9x5ek.h create mode 100644 include/configs/stamp9g20.h

2 2

[U-Boot] [GIT PULL] Pull request: u-boot-imx
by Stefano Babic 14 Aug '12

14 Aug '12

Hi Albert, please pull from u-boot-imx, thanks. The following changes since commit 8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08: DaVinci DA8xx: fix set_cpu_clk_info() (2012-08-05 22:02:40 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to c031cea4c7f5af2aba58e8883eb5cca871213d1b: MX28: Add SchulerControl SC_SPS_1 platform (2012-08-07 17:49:55 +0200) ---------------------------------------------------------------- Fabio Estevam (3): mx28evk: Turn on caches mx51evk: do not overwrite the console vision2: do not overwrite the console Marek Vasut (9): MX28: SPI: Refactor spi_xfer a bit MX28: SPI: Pull out the PIO transfer function MX28: SPI: Add DMA transfer support MX28: Fix up the MMC driver DMA mode MX28: Split out the PIO and DMA transfer functions MX28: Transfer small blocks via PIO in MXS MMC MX28: Fix MXS MMC DMA issues MX28: Move the u-boot.bd info CPUDIR/SOCDIR MX28: Add SchulerControl SC_SPS_1 platform Otavio Salvador (9): imx: Use a clear identification of an unidentified CPU type MX28: extend print_cpuinfo() to use chip information MX28: use a clear name for DDR2 initialization mxs: reorganize source directory for easy sharing of code in i.MXS SoCs mxs: prefix register acessor macros with 'mxs' prefix mxs: prefix register structs with 'mxs' prefix mxs: Reowork SPL to use 'mxs' prefix for methods mxs: Clarify why we poweroff in case of brownout in 5v conflict mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCs Stathis Voukelatos (1): i.MX28: bug fixes in PMU configuration code Stefano Babic (1): MX5: mx53loco: do not overwrite the console Veli-Pekka Peltola (1): Add support for Bluegiga APX4 Development Kit MAINTAINERS | 5 + Makefile | 2 +- arch/arm/cpu/arm926ejs/{mx28 => mxs}/Makefile | 2 +- arch/arm/cpu/arm926ejs/{mx28 => mxs}/clock.c | 40 +-- arch/arm/cpu/arm926ejs/{mx28 => mxs}/iomux.c | 6 +- arch/arm/cpu/arm926ejs/{mx28/mx28.c => mxs/mxs.c} | 72 +++-- .../arm926ejs/{mx28/mx28_init.h => mxs/mxs_init.h} | 14 +- arch/arm/cpu/arm926ejs/{mx28 => mxs}/spl_boot.c | 20 +- .../cpu/arm926ejs/{mx28 => mxs}/spl_lradc_init.c | 10 +- .../arm/cpu/arm926ejs/{mx28 => mxs}/spl_mem_init.c | 64 ++--- .../cpu/arm926ejs/{mx28 => mxs}/spl_power_init.c | 274 ++++++++++---------- arch/arm/cpu/arm926ejs/{mx28 => mxs}/start.S | 0 arch/arm/cpu/arm926ejs/{mx28 => mxs}/timer.c | 8 +- .../arm/cpu/arm926ejs/{mx28 => mxs}/u-boot-spl.lds | 2 +- .../arm/cpu/arm926ejs/mxs}/u-boot.bd | 0 arch/arm/cpu/armv7/imx-common/cpu.c | 4 +- .../include/asm/{arch-mx28 => arch-mxs}/clock.h | 0 arch/arm/include/asm/{arch-mx28 => arch-mxs}/dma.h | 0 .../arm/include/asm/{arch-mx28 => arch-mxs}/gpio.h | 0 .../include/asm/{arch-mx28 => arch-mxs}/imx-regs.h | 0 .../asm/{arch-mx28 => arch-mxs}/iomux-mx28.h | 0 .../include/asm/{arch-mx28 => arch-mxs}/iomux.h | 0 .../asm/{arch-mx28 => arch-mxs}/regs-apbh.h | 256 +++++++++--------- .../asm/{arch-mx28 => arch-mxs}/regs-base.h | 0 .../include/asm/{arch-mx28 => arch-mxs}/regs-bch.h | 44 ++-- .../asm/{arch-mx28 => arch-mxs}/regs-clkctrl.h | 60 ++--- .../asm/{arch-mx28 => arch-mxs}/regs-common.h | 34 +-- .../asm/{arch-mx28 => arch-mxs}/regs-digctl.h | 56 ++-- .../asm/{arch-mx28 => arch-mxs}/regs-gpmi.h | 28 +- .../include/asm/{arch-mx28 => arch-mxs}/regs-i2c.h | 30 +-- .../asm/{arch-mx28 => arch-mxs}/regs-lcdif.h | 66 ++--- .../asm/{arch-mx28 => arch-mxs}/regs-lradc.h | 50 ++-- .../asm/{arch-mx28 => arch-mxs}/regs-ocotp.h | 88 +++---- .../asm/{arch-mx28 => arch-mxs}/regs-pinctrl.h | 170 ++++++------ .../asm/{arch-mx28 => arch-mxs}/regs-power.h | 30 +-- .../include/asm/{arch-mx28 => arch-mxs}/regs-rtc.h | 30 +-- .../include/asm/{arch-mx28 => arch-mxs}/regs-ssp.h | 42 +-- .../asm/{arch-mx28 => arch-mxs}/regs-timrot.h | 40 +-- .../include/asm/{arch-mx28 => arch-mxs}/regs-usb.h | 2 +- .../asm/{arch-mx28 => arch-mxs}/regs-usbphy.h | 22 +- .../asm/{arch-mx28 => arch-mxs}/sys_proto.h | 10 +- board/bluegiga/apx4devkit/Makefile | 47 ++++ board/bluegiga/apx4devkit/apx4devkit.c | 150 +++++++++++ board/bluegiga/apx4devkit/spl_boot.c | 164 ++++++++++++ board/denx/m28evk/m28evk.c | 4 +- board/denx/m28evk/spl_boot.c | 2 +- board/freescale/mx28evk/iomux.c | 2 +- board/freescale/mx28evk/mx28evk.c | 4 +- board/freescale/mx28evk/u-boot.bd | 14 - board/freescale/mx51evk/mx51evk.c | 10 +- board/freescale/mx53loco/mx53loco.c | 12 +- board/schulercontrol/sc_sps_1/Makefile | 47 ++++ board/schulercontrol/sc_sps_1/sc_sps_1.c | 113 ++++++++ board/schulercontrol/sc_sps_1/spl_boot.c | 165 ++++++++++++ board/ttcontrol/vision2/vision2.c | 11 +- boards.cfg | 6 +- doc/README.m28 | 4 +- doc/README.mx28evk | 4 +- drivers/dma/apbh_dma.c | 32 +-- drivers/gpio/mxs_gpio.c | 16 +- drivers/i2c/mxs_i2c.c | 12 +- drivers/mmc/mxsmmc.c | 202 ++++++++------- drivers/mtd/nand/mxs_nand.c | 12 +- drivers/rtc/mxsrtc.c | 6 +- drivers/spi/mxs_spi.c | 200 +++++++++++--- drivers/usb/host/ehci-mxs.c | 24 +- include/configs/apx4devkit.h | 238 +++++++++++++++++ include/configs/m28evk.h | 4 +- include/configs/mx28evk.h | 6 +- include/configs/mx51evk.h | 2 + include/configs/mx53loco.h | 2 + include/configs/sc_sps_1.h | 208 +++++++++++++++ include/configs/vision2.h | 2 + 73 files changed, 2324 insertions(+), 982 deletions(-) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/Makefile (97%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/clock.c (89%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/iomux.c (94%) rename arch/arm/cpu/arm926ejs/{mx28/mx28.c => mxs/mxs.c} (79%) rename arch/arm/cpu/arm926ejs/{mx28/mx28_init.h => mxs/mxs_init.h} (81%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/spl_boot.c (90%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/spl_lradc_init.c (91%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/spl_mem_init.c (83%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/spl_power_init.c (81%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/start.S (100%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/timer.c (95%) rename arch/arm/cpu/arm926ejs/{mx28 => mxs}/u-boot-spl.lds (97%) rename {board/denx/m28evk => arch/arm/cpu/arm926ejs/mxs}/u-boot.bd (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/clock.h (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/dma.h (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/gpio.h (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/imx-regs.h (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/iomux-mx28.h (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/iomux.h (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-apbh.h (77%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-base.h (100%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-bch.h (92%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-clkctrl.h (88%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-common.h (78%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-digctl.h (77%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-gpmi.h (95%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-i2c.h (94%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-lcdif.h (84%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-lradc.h (96%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-ocotp.h (71%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-pinctrl.h (93%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-power.h (97%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-rtc.h (91%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-ssp.h (95%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-timrot.h (90%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-usb.h (99%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/regs-usbphy.h (94%) rename arch/arm/include/asm/{arch-mx28 => arch-mxs}/sys_proto.h (89%) create mode 100644 board/bluegiga/apx4devkit/Makefile create mode 100644 board/bluegiga/apx4devkit/apx4devkit.c create mode 100644 board/bluegiga/apx4devkit/spl_boot.c delete mode 100644 board/freescale/mx28evk/u-boot.bd create mode 100644 board/schulercontrol/sc_sps_1/Makefile create mode 100644 board/schulercontrol/sc_sps_1/sc_sps_1.c create mode 100644 board/schulercontrol/sc_sps_1/spl_boot.c create mode 100644 include/configs/apx4devkit.h create mode 100644 include/configs/sc_sps_1.h Best regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

2 2

[U-Boot] [PATCH 1/6] powerpc/85xx: add support for FM2 DTSEC5
by Timur Tabi 13 Aug '12

13 Aug '12

Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 6 ++++++ arch/powerpc/include/asm/fsl_serdes.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 1 + drivers/net/fm/init.c | 3 +++ include/fm_eth.h | 1 + 5 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 4b52dad..8aac1de 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -68,6 +68,7 @@ static const char *serdes_prtcl_str[] = { [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5", [XAUI_FM1] = "XAUI_FM1", [XAUI_FM2] = "XAUI_FM2", [AURORA] = "DEBUG", @@ -658,6 +659,7 @@ void fsl_serdes_init(void) case SGMII_FM2_DTSEC2: case SGMII_FM2_DTSEC3: case SGMII_FM2_DTSEC4: + case SGMII_FM2_DTSEC5: case XAUI_FM1: case XAUI_FM2: case SRIO1: @@ -717,6 +719,10 @@ void fsl_serdes_init(void) serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | FSL_CORENET_DEVDISR2_DTSEC2_4; break; + case SGMII_FM2_DTSEC5: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_5; + break; case XAUI_FM1: serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | FSL_CORENET_DEVDISR2_10GEC1; diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 0f31af1..22525f1 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -41,6 +41,7 @@ enum srds_prtcl { SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + SGMII_FM2_DTSEC5, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3, diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 53d563e..42dd89c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1729,6 +1729,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 +#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 #define FSL_CORENET_NUM_DEVDISR 2 u8 res7[8]; u32 powmgtcsr; /* Power management status & control */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 953c359..9834cd9 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = { #if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(2, 4), #endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5) + FM_DTSEC_INFO_INITIALIZER(2, 5), +#endif #if (CONFIG_SYS_NUM_FM1_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(1, 1), #endif diff --git a/include/fm_eth.h b/include/fm_eth.h index c7c6882..05121ea 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -35,6 +35,7 @@ enum fm_port { FM2_DTSEC2, FM2_DTSEC3, FM2_DTSEC4, + FM2_DTSEC5, FM2_10GEC1, NUM_FM_PORTS, }; -- 1.7.3.4

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[U-Boot] [PATCH v2 4/6] nand_spl: update udelay for Freescale boards
by Matthew McClintock 13 Aug '12

13 Aug '12

Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time. Looked at reusing the u-boot udelay functions but it pulls in a lot of code as well as depends on the gd struct and would require a lot of rework Signed-off-by: Matthew McClintock <msm(a)freescale.com> --- v2: Change global bus_clk to use gd->bus_clk nand_spl/board/freescale/common.c | 35 +++++++++++++++++++++ nand_spl/board/freescale/p1010rdb/Makefile | 6 +++- nand_spl/board/freescale/p1010rdb/nand_boot.c | 11 +++---- nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 6 +++- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 12 +++---- 5 files changed, 55 insertions(+), 15 deletions(-) create mode 100644 nand_spl/board/freescale/common.c diff --git a/nand_spl/board/freescale/common.c b/nand_spl/board/freescale/common.c new file mode 100644 index 0000000..983fd2e --- /dev/null +++ b/nand_spl/board/freescale/common.c @@ -0,0 +1,35 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Author: Matthew McClintock <msm(a)freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +void udelay(unsigned long usec) { + u32 ticks_per_usec = gd->bus_clk / (8 * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); + + while ((mfspr(SPRN_TBRL)-s) < ticks); +} diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 8d240ea..cdbd492 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o ticks.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index f5294d0..a075509 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -27,8 +27,9 @@ #include <asm/immap_85xx.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_law.h> +#include <asm/global_data.h> -#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); } +DECLARE_GLOBAL_DATA_PTR; unsigned long ddr_freq_mhz; @@ -82,8 +83,7 @@ void sdram_init(void) __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); } - /* mimic 500us delay, with busy isync() loop */ - udelay(100); + udelay(500); /* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); @@ -94,20 +94,19 @@ void sdram_init(void) void board_init_f(ulong bootflag) { u32 plat_ratio, ddr_ratio; - unsigned long bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile index 475cc49..46cf709 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -119,6 +120,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c index b9796ea..fcff382 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c @@ -25,11 +25,9 @@ #include <nand.h> #include <asm/fsl_law.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/global_data.h> -#define udelay(x) {int i, j; \ - for (i = 0; i < x; i++) \ - for (j = 0; j < 10000; j++) \ - ; } +DECLARE_GLOBAL_DATA_PTR; /* * Fixed sdram init -- doesn't use serial presence detect. @@ -76,7 +74,7 @@ void sdram_init(void) void board_init_f(ulong bootflag) { - u32 plat_ratio, bus_clk; + u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); @@ -85,10 +83,10 @@ void board_init_f(ulong bootflag) /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); -- 1.7.9.7

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