August 2012 - U-Boot

[U-Boot] [PATCH v3 8/8] ehci: Optimize qTD allocations
by Benoît Thébaudeau 12 Aug '12

12 Aug '12

Relax the qTD transfer alignment constraints in order to need less qTDs for buffers that are aligned to 512 bytes but not to pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Ilya Yanok <ilya.yanok(a)cogentembedded.com> Cc: Stefan Herbrechtsmeier <stefan(a)herbrechtsmeier.net> --- Changes for v2: N/A. Changes for v3: - New patch. .../drivers/usb/host/ehci-hcd.c | 68 +++++++++++--------- 1 file changed, 38 insertions(+), 30 deletions(-) diff --git u-boot-usb-8d5fb14.orig/drivers/usb/host/ehci-hcd.c u-boot-usb-8d5fb14/drivers/usb/host/ehci-hcd.c index 84c7d08..37517cb 100644 --- u-boot-usb-8d5fb14.orig/drivers/usb/host/ehci-hcd.c +++ u-boot-usb-8d5fb14/drivers/usb/host/ehci-hcd.c @@ -215,7 +215,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, volatile struct qTD *vtd; unsigned long ts; uint32_t *tdp; - uint32_t endpt, token, usbsts; + uint32_t endpt, maxpacket, token, usbsts; uint32_t c, toggle; uint32_t cmd; int timeout; @@ -230,6 +230,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, le16_to_cpu(req->value), le16_to_cpu(req->value), le16_to_cpu(req->index)); +#define PKT_ALIGN 512 /* * The USB transfer is split into qTD transfers. Eeach qTD transfer is * described by a transfer descriptor (the qTD). The qTDs form a linked @@ -251,43 +252,41 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, if (length > 0 || req == NULL) { /* * Determine the qTD transfer size that will be used for the - * data payload (not considering the final qTD transfer, which - * may be shorter). + * data payload (not considering the first qTD transfer, which + * may be longer or shorter, and the final one, which may be + * shorter). * * In order to keep each packet within a qTD transfer, the qTD - * transfer size is aligned to EHCI_PAGE_SIZE, which is a - * multiple of wMaxPacketSize (except in some cases for - * interrupt transfers, see comment in submit_int_msg()). + * transfer size is aligned to PKT_ALIGN, which is a multiple of + * wMaxPacketSize (except in some cases for interrupt transfers, + * see comment in submit_int_msg()). * - * By default, i.e. if the input buffer is page-aligned, + * By default, i.e. if the input buffer is aligned to PKT_ALIGN, * QT_BUFFER_CNT full pages will be used. */ int xfr_sz = QT_BUFFER_CNT; /* - * However, if the input buffer is not page-aligned, the qTD - * transfer size will be one page shorter, and the first qTD + * However, if the input buffer is not aligned to PKT_ALIGN, the + * qTD transfer size will be one page shorter, and the first qTD * data buffer of each transfer will be page-unaligned. */ - if ((uint32_t)buffer & (EHCI_PAGE_SIZE - 1)) + if ((uint32_t)buffer & (PKT_ALIGN - 1)) xfr_sz--; /* Convert the qTD transfer size to bytes. */ xfr_sz *= EHCI_PAGE_SIZE; /* - * Determine the number of qTDs that will be required for the - * data payload. This value has to be rounded up since the final - * qTD transfer may be shorter than the regular qTD transfer - * size that has just been computed. + * Approximate by excess the number of qTDs that will be + * required for the data payload. The exact formula is way more + * complicated and saves at most 2 qTDs, i.e. a total of 128 + * bytes. */ - qtd_count += DIV_ROUND_UP(length, xfr_sz); - /* ZLPs also need a qTD. */ - if (!qtd_count) - qtd_count++; + qtd_count += 2 + length / xfr_sz; } /* - * Threshold value based on the worst-case total size of the qTDs to allocate - * for a mass-storage transfer of 65535 blocks of 512 bytes. + * Threshold value based on the worst-case total size of the allocated qTDs for + * a mass-storage transfer of 65535 blocks of 512 bytes. */ -#if CONFIG_SYS_MALLOC_LEN <= 128 * 1024 +#if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI #endif qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); @@ -314,9 +313,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && usb_pipeendpoint(pipe) == 0); + maxpacket = usb_maxpacket(dev, pipe); endpt = (8 << QH_ENDPT1_RL) | (c << QH_ENDPT1_C) | - (usb_maxpacket(dev, pipe) << QH_ENDPT1_MAXPKTLEN) | + (maxpacket << QH_ENDPT1_MAXPKTLEN) | (0 << QH_ENDPT1_H) | (QH_ENDPT1_DTC_DT_FROM_QTD << QH_ENDPT1_DTC) | (usb_pipespeed(pipe) << QH_ENDPT1_EPS) | @@ -362,6 +362,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, } if (length > 0 || req == NULL) { + uint32_t qtd_toggle = toggle; uint8_t *buf_ptr = buffer; int left_length = length; @@ -379,9 +380,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1); /* * In order to keep each packet within a qTD transfer, - * align the qTD transfer size to EHCI_PAGE_SIZE. + * align the qTD transfer size to PKT_ALIGN. */ - xfr_bytes &= ~(EHCI_PAGE_SIZE - 1); + xfr_bytes &= ~(PKT_ALIGN - 1); /* * This transfer may be shorter than the available qTD * transfer size that has just been computed. @@ -401,7 +402,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, cpu_to_hc32(QT_NEXT_TERMINATE); qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); - token = (toggle << QT_TOKEN_DT) | + token = (qtd_toggle << QT_TOKEN_DT) | (xfr_bytes << QT_TOKEN_TOTALBYTES) | ((req == NULL) << QT_TOKEN_IOC) | (0 << QT_TOKEN_CPAGE) | @@ -418,6 +419,13 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, /* Update previous qTD! */ *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); tdp = &qtd[qtd_counter++].qt_next; + /* + * Data toggle has to be adjusted since the qTD transfer + * size is not always an even multiple of + * wMaxPacketSize. + */ + if ((xfr_bytes / maxpacket) & 1) + qtd_toggle ^= 1; buf_ptr += xfr_bytes; left_length -= xfr_bytes; } while (left_length > 0); @@ -944,11 +952,11 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, * because bInterval is ignored. * * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 - * if several qTDs are required, while the USB specification does not - * constrain this for interrupt transfers. That means that - * ehci_submit_async() would support interrupt transfers requiring - * several transactions only as long as the transfer size does not - * require more than a single qTD. + * <= PKT_ALIGN if several qTDs are required, while the USB + * specification does not constrain this for interrupt transfers. That + * means that ehci_submit_async() would support interrupt transfers + * requiring several transactions only as long as the transfer size does + * not require more than a single qTD. */ if (length > usb_maxpacket(dev, pipe)) { printf("%s: Interrupt transfers requiring several transactions "

2 4

[U-Boot] [PATCH v3 1/8] ehci: cosmetic: Define used constants
by Benoît Thébaudeau 12 Aug '12

12 Aug '12

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Ilya Yanok <ilya.yanok(a)cogentembedded.com> Cc: Stefan Herbrechtsmeier <stefan(a)herbrechtsmeier.net> --- Changes for v2: N/A. Changes for v3: - New patch. .../drivers/usb/host/ehci-hcd.c | 135 +++++++++++--------- .../drivers/usb/host/ehci.h | 75 ++++++++++- 2 files changed, 150 insertions(+), 60 deletions(-) diff --git u-boot-usb-8d5fb14.orig/drivers/usb/host/ehci-hcd.c u-boot-usb-8d5fb14/drivers/usb/host/ehci-hcd.c index 5b3b906..1977c28 100644 --- u-boot-usb-8d5fb14.orig/drivers/usb/host/ehci-hcd.c +++ u-boot-usb-8d5fb14/drivers/usb/host/ehci-hcd.c @@ -163,7 +163,7 @@ static int ehci_reset(void) #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH cmd = ehci_readl(&hcor->or_txfilltuning); - cmd &= ~TXFIFO_THRESH(0x3f); + cmd &= ~TXFIFO_THRESH_MASK; cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); ehci_writel(&hcor->or_txfilltuning, cmd); #endif @@ -186,7 +186,7 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) while (idx < QT_BUFFER_CNT) { td->qt_buffer[idx] = cpu_to_hc32(addr); td->qt_buffer_hi[idx] = 0; - next = (addr + 4096) & ~4095; + next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); delta = next - addr; if (delta >= sz) break; @@ -208,7 +208,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) { ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); - ALLOC_ALIGN_BUFFER(struct qTD, qtd, 3, USB_DMA_MINALIGN); +#define QTD_COUNT 3 + ALLOC_ALIGN_BUFFER(struct qTD, qtd, QTD_COUNT, USB_DMA_MINALIGN); int qtd_counter = 0; volatile struct qTD *vtd; @@ -230,7 +231,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, le16_to_cpu(req->index)); memset(qh, 0, sizeof(struct QH)); - memset(qtd, 0, 3 * sizeof(*qtd)); + memset(qtd, 0, QTD_COUNT * sizeof(*qtd)); toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); @@ -246,19 +247,20 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, */ qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && - usb_pipeendpoint(pipe) == 0) ? 1 : 0; - endpt = (8 << 28) | - (c << 27) | - (usb_maxpacket(dev, pipe) << 16) | - (0 << 15) | - (1 << 14) | - (usb_pipespeed(pipe) << 12) | - (usb_pipeendpoint(pipe) << 8) | - (0 << 7) | (usb_pipedevice(pipe) << 0); + usb_pipeendpoint(pipe) == 0); + endpt = (8 << QH_ENDPT1_RL) | + (c << QH_ENDPT1_C) | + (usb_maxpacket(dev, pipe) << QH_ENDPT1_MAXPKTLEN) | + (0 << QH_ENDPT1_H) | + (QH_ENDPT1_DTC_DT_FROM_QTD << QH_ENDPT1_DTC) | + (usb_pipespeed(pipe) << QH_ENDPT1_EPS) | + (usb_pipeendpoint(pipe) << QH_ENDPT1_ENDPT) | + (0 << QH_ENDPT1_I) | (usb_pipedevice(pipe) << QH_ENDPT1_DEVADDR); qh->qh_endpt1 = cpu_to_hc32(endpt); - endpt = (1 << 30) | - (dev->portnr << 23) | - (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); + endpt = (1 << QH_ENDPT2_MULT) | + (dev->portnr << QH_ENDPT2_PORTNUM) | + (dev->parent->devnum << QH_ENDPT2_HUBADDR) | + (0 << QH_ENDPT2_UFRAMECMASK) | (0 << QH_ENDPT2_UFRAMESMASK); qh->qh_endpt2 = cpu_to_hc32(endpt); qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); @@ -276,9 +278,12 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, */ qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); - token = (0 << 31) | - (sizeof(*req) << 16) | - (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); + token = (0 << QT_TOKEN_DT) | + (sizeof(*req) << QT_TOKEN_TOTALBYTES) | + (0 << QT_TOKEN_IOC) | (0 << QT_TOKEN_CPAGE) | + (3 << QT_TOKEN_CERR) | + (QT_TOKEN_PID_SETUP << QT_TOKEN_PID) | + (QT_TOKEN_STATUS_ACTIVE << QT_TOKEN_STATUS); qtd[qtd_counter].qt_token = cpu_to_hc32(token); if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req)) != 0) { printf("unable construct SETUP td\n"); @@ -302,12 +307,14 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, */ qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); - token = (toggle << 31) | - (length << 16) | - ((req == NULL ? 1 : 0) << 15) | - (0 << 12) | - (3 << 10) | - ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); + token = (toggle << QT_TOKEN_DT) | + (length << QT_TOKEN_TOTALBYTES) | + ((req == NULL) << QT_TOKEN_IOC) | + (0 << QT_TOKEN_CPAGE) | + (3 << QT_TOKEN_CERR) | + ((usb_pipein(pipe) ? QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) << + QT_TOKEN_PID) | + (QT_TOKEN_STATUS_ACTIVE << QT_TOKEN_STATUS); qtd[qtd_counter].qt_token = cpu_to_hc32(token); if (ehci_td_buffer(&qtd[qtd_counter], buffer, length) != 0) { printf("unable construct DATA td\n"); @@ -328,12 +335,14 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, */ qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); - token = (toggle << 31) | - (0 << 16) | - (1 << 15) | - (0 << 12) | - (3 << 10) | - ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); + token = (toggle << QT_TOKEN_DT) | + (0 << QT_TOKEN_TOTALBYTES) | + (1 << QT_TOKEN_IOC) | + (0 << QT_TOKEN_CPAGE) | + (3 << QT_TOKEN_CERR) | + ((usb_pipein(pipe) ? QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) << + QT_TOKEN_PID) | + (QT_TOKEN_STATUS_ACTIVE << QT_TOKEN_STATUS); qtd[qtd_counter].qt_token = cpu_to_hc32(token); /* Update previous qTD! */ *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); @@ -346,7 +355,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, flush_dcache_range((uint32_t)qh_list, ALIGN_END_ADDR(struct QH, qh_list, 1)); flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); - flush_dcache_range((uint32_t)qtd, ALIGN_END_ADDR(struct qTD, qtd, 3)); + flush_dcache_range((uint32_t)qtd, + ALIGN_END_ADDR(struct qTD, qtd, QTD_COUNT)); /* Set async. queue head pointer. */ ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list); @@ -359,10 +369,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, cmd |= CMD_ASE; ehci_writel(&hcor->or_usbcmd, cmd); - ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS, + ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS, 100 * 1000); if (ret < 0) { - printf("EHCI fail timeout STD_ASS set\n"); + printf("EHCI fail timeout STS_ASS set\n"); goto fail; } @@ -377,10 +387,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, invalidate_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); invalidate_dcache_range((uint32_t)qtd, - ALIGN_END_ADDR(struct qTD, qtd, 3)); + ALIGN_END_ADDR(struct qTD, qtd, QTD_COUNT)); token = hc32_to_cpu(vtd->qt_token); - if (!(token & 0x80)) + if (!(token & (QT_TOKEN_STATUS_ACTIVE << QT_TOKEN_STATUS))) break; WATCHDOG_RESET(); } while (get_timer(ts) < timeout); @@ -398,50 +408,53 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN)); /* Check that the TD processing happened */ - if (token & 0x80) { + if (token & (QT_TOKEN_STATUS_ACTIVE << QT_TOKEN_STATUS)) printf("EHCI timed out on TD - token=%#x\n", token); - } /* Disable async schedule. */ cmd = ehci_readl(&hcor->or_usbcmd); cmd &= ~CMD_ASE; ehci_writel(&hcor->or_usbcmd, cmd); - ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0, + ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0, 100 * 1000); if (ret < 0) { - printf("EHCI fail timeout STD_ASS reset\n"); + printf("EHCI fail timeout STS_ASS reset\n"); goto fail; } token = hc32_to_cpu(qh->qh_overlay.qt_token); - if (!(token & 0x80)) { + if (!(token & (QT_TOKEN_STATUS_ACTIVE << QT_TOKEN_STATUS))) { debug("TOKEN=%#x\n", token); - switch (token & 0xfc) { + switch ((token >> QT_TOKEN_STATUS) & (QT_TOKEN_STATUS_ACTIVE | + QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_DATBUFERR | + QT_TOKEN_STATUS_BABBLEDET | QT_TOKEN_STATUS_XACTERR | + QT_TOKEN_STATUS_MISSEDUFRAME)) { case 0: - toggle = token >> 31; + toggle = token >> QT_TOKEN_DT; usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle); dev->status = 0; break; - case 0x40: + case QT_TOKEN_STATUS_HALTED: dev->status = USB_ST_STALLED; break; - case 0xa0: - case 0x20: + case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: + case QT_TOKEN_STATUS_DATBUFERR: dev->status = USB_ST_BUF_ERR; break; - case 0x50: - case 0x10: + case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: + case QT_TOKEN_STATUS_BABBLEDET: dev->status = USB_ST_BABBLE_DET; break; default: dev->status = USB_ST_CRC_ERR; - if ((token & 0x40) == 0x40) + if (token & (QT_TOKEN_STATUS_HALTED << QT_TOKEN_STATUS)) dev->status |= USB_ST_STALLED; break; } - dev->act_len = length - ((token >> 16) & 0x7fff); + dev->act_len = length - ((token & QT_TOKEN_TOTALBYTES_MASK) >> + QT_TOKEN_TOTALBYTES); } else { dev->act_len = 0; debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", @@ -499,12 +512,14 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, case USB_DT_DEVICE: debug("USB_DT_DEVICE request\n"); srcptr = &descriptor.device; - srclen = 0x12; + srclen = descriptor.device.bLength; break; case USB_DT_CONFIG: debug("USB_DT_CONFIG config\n"); srcptr = &descriptor.config; - srclen = 0x19; + srclen = descriptor.config.bLength + + descriptor.interface.bLength + + descriptor.endpoint.bLength; break; case USB_DT_STRING: debug("USB_DT_STRING config\n"); @@ -539,7 +554,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, case USB_DT_HUB: debug("USB_DT_HUB config\n"); srcptr = &descriptor.hub; - srclen = 0x8; + srclen = descriptor.hub.bLength; break; default: debug("unknown value %x\n", le16_to_cpu(req->value)); @@ -577,13 +592,13 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; if (ehci_is_TDI()) { - switch ((reg >> 26) & 3) { - case 0: + switch ((reg & PORTSC_PSPD_MASK) >> PORTSC_PSPD_OFFS) { + case PORTSC_PSPD_FS: break; - case 1: + case PORTSC_PSPD_LS: tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; break; - case 2: + case PORTSC_PSPD_HS: default: tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; break; @@ -744,11 +759,13 @@ int usb_lowlevel_init(void) /* Set head of reclaim list */ memset(qh_list, 0, sizeof(*qh_list)); qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); - qh_list->qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); + qh_list->qh_endpt1 = cpu_to_hc32((1 << QH_ENDPT1_H) | + (USB_SPEED_HIGH << QH_ENDPT1_EPS)); qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); - qh_list->qh_overlay.qt_token = cpu_to_hc32(0x40); + qh_list->qh_overlay.qt_token = cpu_to_hc32(QT_TOKEN_STATUS_HALTED << + QT_TOKEN_STATUS); reg = ehci_readl(&hccr->cr_hcsparams); descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); diff --git u-boot-usb-8d5fb14.orig/drivers/usb/host/ehci.h u-boot-usb-8d5fb14/drivers/usb/host/ehci.h index 7992983..c6f1794 100644 --- u-boot-usb-8d5fb14.orig/drivers/usb/host/ehci.h +++ u-boot-usb-8d5fb14/drivers/usb/host/ehci.h @@ -68,7 +68,7 @@ struct ehci_hcor { #define CMD_RESET (1 << 1) /* reset HC not bus */ #define CMD_RUN (1 << 0) /* start/stop HC */ uint32_t or_usbsts; -#define STD_ASS (1 << 15) +#define STS_ASS (1 << 15) #define STS_HALT (1 << 12) uint32_t or_usbintr; #define INTR_UE (1 << 0) /* USB interrupt enable */ @@ -83,11 +83,44 @@ struct ehci_hcor { uint32_t _reserved_0_; uint32_t or_burstsize; uint32_t or_txfilltuning; +#define TXFIFO_THRESH_MASK (0x3f << 16) #define TXFIFO_THRESH(p) ((p & 0x3f) << 16) uint32_t _reserved_1_[6]; uint32_t or_configflag; #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; +#define PORTSC_PTS_OFFS 30 +#define PORTSC_PTS_MASK (0x3 << PORTSC_PTS_OFFS) +#define PORTSC_STS (1 << 29) +#define PORTSC_PTW (1 << 28) +#define PORTSC_PSPD_OFFS 26 +#define PORTSC_PSPD_MASK (0x3 << PORTSC_PSPD_OFFS) +#define PORTSC_PSPD_FS 0x0 +#define PORTSC_PSPD_LS 0x1 +#define PORTSC_PSPD_HS 0x2 +#define PORTSC_PFSC (1 << 24) +#define PORTSC_PHCD (1 << 23) +#define PORTSC_WKOC (1 << 22) +#define PORTSC_WKDS (1 << 21) +#define PORTSC_WKCN (1 << 20) +#define PORTSC_PTC_OFFS 16 +#define PORTSC_PTC_MASK (0xf << PORTSC_PTC_OFFS) +#define PORTSC_PIC_OFFS 14 +#define PORTSC_PIC_MASK (0x3 << PORTSC_PIC_OFFS) +#define PORTSC_PO (1 << 13) +#define PORTSC_PP (1 << 12) +#define PORTSC_LS_OFFS 10 +#define PORTSC_LS_MASK (0x3 << PORTSC_LS_OFFS) +#define PORTSC_HSP (1 << 9) +#define PORTSC_PR (1 << 8) +#define PORTSC_SUSP (1 << 7) +#define PORTSC_FPR (1 << 6) +#define PORTSC_OCC (1 << 5) +#define PORTSC_OCA (1 << 4) +#define PORTSC_PEC (1 << 3) +#define PORTSC_PE (1 << 2) +#define PORTSC_OSC (1 << 1) +#define PORTSC_CCS (1 << 0) uint32_t or_systune; } __attribute__ ((packed, aligned(4))); @@ -175,6 +208,25 @@ struct qTD { #define QT_NEXT_TERMINATE 1 uint32_t qt_altnext; /* see EHCI 3.5.2 */ uint32_t qt_token; /* see EHCI 3.5.3 */ +#define QT_TOKEN_DT 31 /* Data Toggle */ +#define QT_TOKEN_TOTALBYTES 16 /* Total Bytes to Transfer */ +#define QT_TOKEN_TOTALBYTES_MASK (0x7fff << QT_TOKEN_TOTALBYTES) +#define QT_TOKEN_IOC 15 /* Interrupt On Complete */ +#define QT_TOKEN_CPAGE 12 /* Current Page */ +#define QT_TOKEN_CERR 10 /* Error Counter */ +#define QT_TOKEN_PID 8 /* PID Code */ +#define QT_TOKEN_PID_OUT 0x0 +#define QT_TOKEN_PID_IN 0x1 +#define QT_TOKEN_PID_SETUP 0x2 +#define QT_TOKEN_STATUS 0 /* Status */ +#define QT_TOKEN_STATUS_ACTIVE 0x80 +#define QT_TOKEN_STATUS_HALTED 0x40 +#define QT_TOKEN_STATUS_DATBUFERR 0x20 +#define QT_TOKEN_STATUS_BABBLEDET 0x10 +#define QT_TOKEN_STATUS_XACTERR 0x08 +#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04 +#define QT_TOKEN_STATUS_SPLITXSTATE 0x02 +#define QT_TOKEN_STATUS_PERR 0x01 #define QT_BUFFER_CNT 5 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */ uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */ @@ -182,6 +234,8 @@ struct qTD { uint32_t unused[3]; }; +#define EHCI_PAGE_SIZE 4096 + /* Queue Head (QH). */ struct QH { uint32_t qh_link; @@ -191,7 +245,26 @@ struct QH { #define QH_LINK_TYPE_SITD 4 #define QH_LINK_TYPE_FSTN 6 uint32_t qh_endpt1; +#define QH_ENDPT1_RL 28 /* NAK Count Reload */ +#define QH_ENDPT1_C 27 /* Control Endpoint Flag */ +#define QH_ENDPT1_MAXPKTLEN 16 /* Maximum Packet Length */ +#define QH_ENDPT1_H 15 /* Head of Reclamation List Flag */ +#define QH_ENDPT1_DTC 14 /* Data Toggle Control */ +#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0 +#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1 +#define QH_ENDPT1_EPS 12 /* Endpoint Speed */ +#define QH_ENDPT1_EPS_FS 0x0 +#define QH_ENDPT1_EPS_LS 0x1 +#define QH_ENDPT1_EPS_HS 0x2 +#define QH_ENDPT1_ENDPT 8 /* Endpoint Number */ +#define QH_ENDPT1_I 7 /* Inactivate on Next Transaction */ +#define QH_ENDPT1_DEVADDR 0 /* Device Address */ uint32_t qh_endpt2; +#define QH_ENDPT2_MULT 30 /* High-Bandwidth Pipe Multiplier */ +#define QH_ENDPT2_PORTNUM 23 /* Port Number */ +#define QH_ENDPT2_HUBADDR 16 /* Hub Address */ +#define QH_ENDPT2_UFRAMECMASK 8 /* Split Completion Mask */ +#define QH_ENDPT2_UFRAMESMASK 0 /* Interrupt Schedule Mask */ uint32_t qh_curtd; struct qTD qh_overlay; /*

3 24

[U-Boot] [PATCH V3 1/3] imx-common/cmd_resetmode.c: add imx resetmode command
by Troy Kisky 11 Aug '12

11 Aug '12

This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> Note: MX53 support untested. --- arch/arm/cpu/armv7/imx-common/Makefile | 1 + arch/arm/cpu/armv7/imx-common/cmd_resetmode.c | 152 +++++++++++++++++++++++++ arch/arm/cpu/armv7/mx5/soc.c | 31 +++++ arch/arm/cpu/armv7/mx6/soc.c | 36 ++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 18 +++ arch/arm/include/asm/arch-mx6/imx-regs.h | 21 ++++ arch/arm/include/asm/imx-common/resetmode.h | 36 ++++++ 7 files changed, 295 insertions(+) create mode 100644 arch/arm/cpu/armv7/imx-common/cmd_resetmode.c create mode 100644 arch/arm/include/asm/imx-common/resetmode.h V3 is same as V2, only a rebase. diff --git a/arch/arm/cpu/armv7/imx-common/Makefile b/arch/arm/cpu/armv7/imx-common/Makefile index bf36be5..24f490e 100644 --- a/arch/arm/cpu/armv7/imx-common/Makefile +++ b/arch/arm/cpu/armv7/imx-common/Makefile @@ -29,6 +29,7 @@ LIB = $(obj)libimx-common.o COBJS-y = iomux-v3.o timer.o cpu.o speed.o COBJS-$(CONFIG_I2C_MXC) += i2c.o +COBJS-$(CONFIG_CMD_RESETMODE) += cmd_resetmode.o COBJS := $(sort $(COBJS-y)) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/imx-common/cmd_resetmode.c b/arch/arm/cpu/armv7/imx-common/cmd_resetmode.c new file mode 100644 index 0000000..d1c50e1 --- /dev/null +++ b/arch/arm/cpu/armv7/imx-common/cmd_resetmode.c @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2012 Boundary Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/imx-common/resetmode.h> +#include <malloc.h> + +const struct reset_mode *modes[2]; + +const struct reset_mode *search_modes(char *arg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(modes); i++) { + const struct reset_mode *p = modes[i]; + if (p) { + while (p->name) { + if (!strcmp(p->name, arg)) + return p; + p++; + } + } + } + return NULL; +} + +int create_usage(char *dest) +{ + int i; + int size = 0; + + for (i = 0; i < ARRAY_SIZE(modes); i++) { + const struct reset_mode *p = modes[i]; + if (p) { + while (p->name) { + int len = strlen(p->name); + if (dest) { + memcpy(dest, p->name, len); + dest += len; + *dest++ = '|'; + } + size += len + 1; + p++; + } + } + } + if (dest) + dest[-1] = 0; + return size; +} + +int do_resetmode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const struct reset_mode *p; + + if (argc < 2) + return CMD_RET_USAGE; + p = search_modes(argv[1]); + if (!p) + return CMD_RET_USAGE; + reset_mode_apply(p->cfg_val); + return 0; +} + +U_BOOT_CMD( + resetmode, 2, 0, do_resetmode, + NULL, + ""); + +void add_board_resetmodes(const struct reset_mode *p) +{ + int size; + char *dest; + + if (__u_boot_cmd_resetmode.usage) { + free(__u_boot_cmd_resetmode.usage); + __u_boot_cmd_resetmode.usage = NULL; + } + + modes[0] = p; + modes[1] = soc_reset_modes; + size = create_usage(NULL); + dest = malloc(size); + if (dest) { + create_usage(dest); + __u_boot_cmd_resetmode.usage = dest; + } +} + +int do_resetmode_cmd(char *arg) +{ + const struct reset_mode *p; + + p = search_modes(arg); + if (!p) { + printf("%s not found\n", arg); + return CMD_RET_FAILURE; + } + reset_mode_apply(p->cfg_val); + do_reset(NULL, 0, 0, NULL); + return 0; +} + +int do_bootmmc0(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return do_resetmode_cmd("mmc0"); +} + +int do_bootmmc1(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return do_resetmode_cmd("mmc1"); +} + +int do_download_mode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return do_resetmode_cmd("usb"); +} + +U_BOOT_CMD( + bootmmc0, 1, 0, do_bootmmc0, + "boot to mmc 0", + ""); + +U_BOOT_CMD( + bootmmc1, 1, 0, do_bootmmc1, + "boot to mmc 1", + ""); + +U_BOOT_CMD( + download_mode, 1, 0, do_download_mode, + "start rom loader", + ""); diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 3f5a4f7..9cd363b 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -30,6 +30,7 @@ #include <asm/errno.h> #include <asm/io.h> +#include <asm/imx-common/resetmode.h> #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) #error "CPU_TYPE not defined" @@ -115,3 +116,33 @@ void set_chipselect_size(int const cs_size) writel(reg, &iomuxc_regs->gpr1); } + +#ifdef CONFIG_MX53 +void reset_mode_apply(unsigned cfg_val) +{ + writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr); +} +/* + * cfg_val will be used for + * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] + * + * If bit 28 of LPGR is set upon watchdog reset, + * bits[25:0] of LPGR will move to SBMR. + */ +const struct reset_mode soc_reset_modes[] = { + {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, + /* usb or serial download */ + {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)}, + {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)}, + {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)}, + {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)}, + {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)}, + {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)}, + /* 4 bit bus width */ + {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, + {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, + {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)}, + {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)}, + {NULL, 0}, +}; +#endif diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 84b458c..7a7fb35 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -29,6 +29,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/imx-common/resetmode.h> u32 get_cpu_rev(void) { @@ -141,3 +142,38 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif + +void reset_mode_apply(unsigned cfg_val) +{ + unsigned reg; + struct src_regs *psrc = (struct src_regs *)SRC_BASE_ADDR; + writel(cfg_val, &psrc->gpr9); + reg = readl(&psrc->gpr10); + if (cfg_val) + reg |= 1 << 28; + else + reg &= ~(1 << 28); + writel(reg, &psrc->gpr10); +} +/* + * cfg_val will be used for + * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] + * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] + * to SBMR1, which will determine the boot device. + */ +const struct reset_mode soc_reset_modes[] = { + {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, + /* reserved value should start rom usb */ + {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, + {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, + {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, + {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, + {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, + {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, + /* 4 bit bus width */ + {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 7f66b61..c53465f 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -459,6 +459,24 @@ struct src { u32 simr; }; +struct srtc_regs { + u32 lpscmr; /* 0x00 */ + u32 lpsclr; /* 0x04 */ + u32 lpsar; /* 0x08 */ + u32 lpsmcr; /* 0x0c */ + u32 lpcr; /* 0x10 */ + u32 lpsr; /* 0x14 */ + u32 lppdr; /* 0x18 */ + u32 lpgr; /* 0x1c */ + u32 hpcmr; /* 0x20 */ + u32 hpclr; /* 0x24 */ + u32 hpamr; /* 0x28 */ + u32 hpalr; /* 0x2c */ + u32 hpcr; /* 0x30 */ + u32 hpisr; /* 0x34 */ + u32 hpienr; /* 0x38 */ +}; + /* CSPI registers */ struct cspi_regs { u32 rxdata; diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d77603..dacb9ea 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -448,5 +448,26 @@ struct iomuxc_base_regs { u32 daisy[104]; /* 0x7b0..94c */ }; +struct src_regs { + u32 scr; /* 0x00 */ + u32 sbmr1; /* 0x04 */ + u32 srsr; /* 0x08 */ + u32 reserved1; /* 0x0c */ + u32 reserved2; /* 0x10 */ + u32 sisr; /* 0x14 */ + u32 simr; /* 0x18 */ + u32 sbmr2; /* 0x1c */ + u32 gpr1; /* 0x20 */ + u32 gpr2; /* 0x24 */ + u32 gpr3; /* 0x28 */ + u32 gpr4; /* 0x2c */ + u32 gpr5; /* 0x30 */ + u32 gpr6; /* 0x34 */ + u32 gpr7; /* 0x38 */ + u32 gpr8; /* 0x3c */ + u32 gpr9; /* 0x40 */ + u32 gpr10; /* 0x44 */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/imx-common/resetmode.h b/arch/arm/include/asm/imx-common/resetmode.h new file mode 100644 index 0000000..76216d0 --- /dev/null +++ b/arch/arm/include/asm/imx-common/resetmode.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2012 Boundary Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_RESETMODE_H +#define _ASM_RESETMODE_H +#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \ + ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1) + +struct reset_mode { + const char *name; + unsigned cfg_val; +}; + +void add_board_resetmodes(const struct reset_mode *p); +void reset_mode_apply(unsigned cfg_val); +extern const struct reset_mode soc_reset_modes[]; +#endif -- 1.7.9.5

4 11

Re: [U-Boot] multiple definition of `reloc_dst'
by Sabri Altunbas 11 Aug '12

11 Aug '12

Ich habe in Makefile die Zeile "LDFLAGS += -z muldefs" aufgenommen

1 0

[U-Boot] [PATCH 1/5] pxa255: Add UDC registers definitions
by Łukasz Dałek 11 Aug '12

11 Aug '12

This patch starts series of patches adding support for USB support on PXA255 chips. Signed-off-by: Łukasz Dałek <luk0104(a)gmail.com> --- arch/arm/include/asm/arch-pxa/pxa-regs.h | 247 ++++++++++++++++++++++++++++++ 1 files changed, 247 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index b81b42c..114e9a2 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -2498,6 +2498,253 @@ typedef void (*ExcpHndlr) (void) ; #endif /* CONFIG_CPU_PXA27X */ +#if defined(CONFIG_CPU_PXA25X) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDCCR *((volatile u32 *)0x40600000) +#else +# define UDCCR 0x40600000 +#endif + +#define UDCCR_UDE (1 << 0) +#define UDCCR_UDA (1 << 1) +#define UDCCR_RSM (1 << 2) +#define UDCCR_RESIR (1 << 3) +#define UDCCR_SUSIR (1 << 4) +#define UDCCR_SRM (1 << 5) +#define UDCCR_RSTIR (1 << 6) +#define UDCCR_REM (1 << 7) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDCCFR *((volatile u32 *)0x40600008) +#else +# define UDCCFR 0x40600008 +#endif + +#define UDCCFR_AREN (1 << 7) +#define UDCCFR_ACM (1 << 2) +#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UICR0 *((volatile u32 *)0x40600050) +#else +# define UICR0 0x40600050 +#endif + +#define UICR0_MASK 0xf +#define UICR0_IM0 (1 << 0) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UICR1 *((volatile u32 *)0x40600054) +#else +# define UICR1 0x40600054 +#endif + +#define UICR1_MASK 0xf + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define USIR0 *((volatile u32 *)0x40600058) +#else +# define USIR0 0x40600058 +#endif + +#define USIR0_MASK 0xf +#define USIR0_IR0 (1 << 0) +#define USIR0_IR1 (1 << 1) +#define USIR0_IR2 (1 << 2) +#define USIR0_IR3 (1 << 3) +#define USIR0_IR4 (1 << 4) +#define USIR0_IR5 (1 << 5) +#define USIR0_IR6 (1 << 6) +#define USIR0_IR7 (1 << 7) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define USIR1 *((volatile u32 *)0x4060005c) +#else +# define USIR1 0x4060005c +#endif + +#define USIR1_MASK 0xf +#define USIR1_IR8 (1 << 0) +#define USIR1_IR9 (1 << 1) +#define USIR1_IR10 (1 << 2) +#define USIR1_IR11 (1 << 3) +#define USIR1_IR12 (1 << 4) +#define USIR1_IR13 (1 << 5) +#define USIR1_IR14 (1 << 6) +#define USIR1_IR15 (1 << 7) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDCCS0 *((volatile u32 *)0x40600010) +# define UDCCS1 *((volatile u32 *)0x40600014) +# define UDCCS2 *((volatile u32 *)0x40600018) +# define UDCCS3 *((volatile u32 *)0x4060001c) +# define UDCCS4 *((volatile u32 *)0x40600020) +# define UDCCS5 *((volatile u32 *)0x40600024) +# define UDCCS6 *((volatile u32 *)0x40600028) +# define UDCCS7 *((volatile u32 *)0x4060002c) +# define UDCCS8 *((volatile u32 *)0x40600030) +# define UDCCS9 *((volatile u32 *)0x40600034) +# define UDCCS10 *((volatile u32 *)0x40600038) +# define UDCCS11 *((volatile u32 *)0x4060003c) +# define UDCCS12 *((volatile u32 *)0x40600040) +# define UDCCS13 *((volatile u32 *)0x40600044) +# define UDCCS14 *((volatile u32 *)0x40600048) +# define UDCCS15 *((volatile u32 *)0x4060004c) +#else +# define UDCCS(x) (0x40600010 + 4 * (x)) +# define UDCCS0 UDCCS(0) +#endif + +/* Control endpoint 0 */ +#define UDCCS_CTRL_OPR (1 << 0) +#define UDCCS_CTRL_IPR (1 << 1) +#define UDCCS_CTRL_FTF (1 << 2) +#define UDCCS_CTRL_DRWF (1 << 3) +#define UDCCS_CTRL_SST (1 << 4) +#define UDCCS_CTRL_FST (1 << 5) +#define UDCCS_CTRL_RNE (1 << 6) +#define UDCCS_CTRL_SA (1 << 7) + +/* Linux compat */ +#define UDCCS0_SA UDCCS_CTRL_SA +#define UDCCS0_RNE UDCCS_CTRL_RNE +#define UDCCS0_FST UDCCS_CTRL_FST +#define UDCCS0_SST UDCCS_CTRL_SST +#define UDCCS0_DRWF UDCCS_CTRL_DRWF +#define UDCCS0_FTF UDCCS_CTRL_FTF +#define UDCCS0_IPR UDCCS_CTRL_IPR +#define UDCCS0_OPR UDCCS_CTRL_OPR + +/* Bulk IN endpoint 1/6/11 */ +#define UDCCS_BULK_IN_TSP (1 << 7) +#define UDCCS_BULK_IN_FST (1 << 5) +#define UDCCS_BULK_IN_SST (1 << 4) +#define UDCCS_BULK_IN_TUR (1 << 3) +#define UDCCS_BULK_IN_FTF (1 << 2) +#define UDCCS_BULK_IN_TPC (1 << 1) +#define UDCCS_BULK_IN_TFS (1 << 0) + +/* Linux compat */ +#define UDCCS_BI_TFS UDCCS_BULK_IN_TFS +#define UDCCS_BI_TPC UDCCS_BULK_IN_TPC +#define UDCCS_BI_FTF UDCCS_BULK_IN_FTF +#define UDCCS_BI_TUR UDCCS_BULK_IN_TUR +#define UDCCS_BI_SST UDCCS_BULK_IN_SST +#define UDCCS_BI_FST UDCCS_BULK_IN_FST +#define UDCCS_BI_TSP UDCCS_BULK_IN_TSP + +/* Bulk OUT endpoint 2/7/12 */ +#define UDCCS_BULK_OUT_RSP (1 << 7) +#define UDCCS_BULK_OUT_RNE (1 << 6) +#define UDCCS_BULK_OUT_FST (1 << 5) +#define UDCCS_BULK_OUT_SST (1 << 4) +#define UDCCS_BULK_OUT_DME (1 << 3) +#define UDCCS_BULK_OUT_RPC (1 << 1) +#define UDCCS_BULK_OUT_RFS (1 << 0) + +/* Linux compat */ +#define UDCCS_BO_RSP UDCCS_BULK_OUT_RSP +#define UDCCS_BO_RNE UDCCS_BULK_OUT_RNE +#define UDCCS_BO_FST UDCCS_BULK_OUT_FST +#define UDCCS_BO_SST UDCCS_BULK_OUT_SST +#define UDCCS_BO_DME UDCCS_BULK_OUT_DME +#define UDCCS_BO_RPC UDCCS_BULK_OUT_RPC +#define UDCCS_BO_RFS UDCCS_BULK_OUT_RFS + +/* Isochronous IN endpoint 3/8/13 */ +#define UDCCS_ISO_IN_TSP (1 << 7) +#define UDCCS_ISO_IN_TUR (1 << 3) +#define UDCCS_ISO_IN_FTF (1 << 2) +#define UDCCS_ISO_IN_TPC (1 << 1) +#define UDCCS_ISO_IN_TFS (1 << 0) + +/* Isochronous OUT endpoint 4/9/14 */ +#define UDCCS_ISO_OUT_RSP (1 << 7) +#define UDCCS_ISO_OUT_RNE (1 << 6) +#define UDCCS_ISO_OUT_DME (1 << 3) +#define UDCCS_ISO_OUT_ROF (1 << 2) +#define UDCCS_ISO_OUT_RPC (1 << 1) +#define UDCCS_ISO_OUT_RFS (1 << 0) + +/* Linux compat */ +#define UDCCS_IO_RSP UDCCS_ISO_OUT_RSP +#define UDCCS_IO_RNE UDCCS_ISO_OUT_RNE +#define UDCCS_IO_DME UDCCS_ISO_OUT_DME +#define UDCCS_IO_ROF UDCCS_ISO_OUT_ROF +#define UDCCS_IO_RPC UDCCS_ISO_OUT_RPC +#define UDCCS_IO_RFS UDCCS_ISO_OUT_RFS + +/* Interrupt IN endpoint 5/10/15 */ +#define UDCCS_INT_TSP (1 << 7) +#define UDCCS_INT_FST (1 << 5) +#define UDCCS_INT_SST (1 << 4) +#define UDCCS_INT_TUR (1 << 3) +#define UDCCS_INT_FTF (1 << 2) +#define UDCCS_INT_TPC (1 << 1) +#define UDCCS_INT_TFS (1 << 0) + +/* Byte count registers */ +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UBCR2 *((volatile u32 *)0x40600068) +# define UBCR4 *((volatile u32 *)0x4060006c) +# define UBCR7 *((volatile u32 *)0x40600070) +# define UBCR9 *((volatile u32 *)0x40600074) +# define UBCR12 *((volatile u32 *)0x40600078) +# define UBCR14 *((volatile u32 *)0x4060007c) +#else +# define UBCR2 0x40600068 +# define UBCR4 0x4060006c +# define UBCR7 0x40600070 +# define UBCR9 0x40600074 +# define UBCR12 0x40600078 +# define UBCR14 0x4060007c +#endif + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDDR0 *((volatile u32 *)0x40600080) +# define UDDR1 *((volatile u32 *)0x40600100) +# define UDDR2 *((volatile u32 *)0x40600180) +# define UDDR3 *((volatile u32 *)0x40600200) +# define UDDR4 *((volatile u32 *)0x40600400) +# define UDDR5 *((volatile u32 *)0x406000A0) +# define UDDR6 *((volatile u32 *)0x40600600) +# define UDDR7 *((volatile u32 *)0x40600680) +# define UDDR8 *((volatile u32 *)0x40600700) +# define UDDR9 *((volatile u32 *)0x40600900) +# define UDDR10 *((volatile u32 *)0x406000C0) +# define UDDR11 *((volatile u32 *)0x40600B00) +# define UDDR12 *((volatile u32 *)0x40600B80) +# define UDDR13 *((volatile u32 *)0x40600C00) +# define UDDR14 *((volatile u32 *)0x40600E00) +# define UDDR15 *((volatile u32 *)0x406000E0) +#else +# define UDDR0 0x40600080 +# define UDDR1 0x40600100 +# define UDDR2 0x40600180 +# define UDDR3 0x40600200 +# define UDDR4 0x40600400 +# define UDDR5 0x406000A0 +# define UDDR6 0x40600600 +# define UDDR7 0x40600680 +# define UDDR8 0x40600700 +# define UDDR9 0x40600900 +# define UDDR10 0x406000C0 +# define UDDR11 0x40600B00 +# define UDDR12 0x40600B80 +# define UDDR13 0x40600C00 +# define UDDR14 0x40600E00 +# define UDDR15 0x406000E0 +#endif + +/* Linux compat */ +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UFNRH *((volatile u32 *)0x40600060) +# define UFNRL *((volatile u32 *)0x40600064) +#endif + +#endif /* CONFIG_CPU_PXA25X */ + /* LCD registers */ #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ #define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ -- 1.7.3.4

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[U-Boot] [PATCH] armv7: Move save_boot_params_default() to start.S
by Benoît Thébaudeau 11 Aug '12

11 Aug '12

save_boot_params() is called by start.S, so move its default implementation to this file too. This is also useful for boards willing to use nand_spl since cpu.c is not built in this case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- .../arch/arm/cpu/armv7/cpu.c | 7 ------- .../arch/arm/cpu/armv7/start.S | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/cpu.c u-boot-4d3c95f/arch/arm/cpu/armv7/cpu.c index c6fa8ef..b0677f4 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/cpu.c +++ u-boot-4d3c95f/arch/arm/cpu/armv7/cpu.c @@ -37,13 +37,6 @@ #include <asm/cache.h> #include <asm/armv7.h> -void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) -{ -} - -void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) - __attribute__((weak, alias("save_boot_params_default"))); - int cleanup_before_linux(void) { /* diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/start.S u-boot-4d3c95f/arch/arm/cpu/armv7/start.S index aee27fd..6df9c91 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/start.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/start.S @@ -119,6 +119,13 @@ FIQ_STACK_START: IRQ_STACK_START_IN: .word 0x0badc0de +.globl save_boot_params_default +save_boot_params_default: + mov pc, lr + +.weak save_boot_params +save_boot_params = save_boot_params_default + /* * the actual reset code */

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[U-Boot] Using u-boot to update the kernel and root-file system on NAND chip on imx28evk from USB memory stick
by Bill 11 Aug '12

11 Aug '12

All, I'm needing the ability to upgrade the kernel and root-filesystem on the NAND chip on the imx28evk from new files that reside on a USB memory stick. That is I want to partition the NAND (mtd) into 3 sections that contain u-boot, kernel, rootfs. Then whenever the system is booted, u-boot will probe the USB memory stick (using fatls and looking for a kernel file and rootfs file) If the files exist on the USB memory stick, uboot will automatically (first it will verify a CRC/Checksum) erase the kernel and rootfs sections on the NAND chip, and then copy the new kernel and rootfs from the USB stick to their respective sections in the flash chip (I think using fatload)?. It will never write a new u-boot. I've also seen where u-boot can define the NAND flash partitions using the mtdparts command and pass these along to the kernel via command line args? Can u-boot write/erase to a nand partition (i.e. /dev/mtd0) instead of using absolute memory addresses? Thanks, Bill

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[U-Boot] [PATCH v4] tx25: Use generic gpio_* calls
by Vikram Narayanan 11 Aug '12

11 Aug '12

Instead of manipulating gpio registers directly, use the calls from the gpio library. Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Acked-by: Stefano Babic <sbabic(a)denx.de> Cc: John Rigby <jcrigby(a)gmail.com> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes from v3: Use gpio_set_value instead of gpio_direction_output (Ahh. Missed it again!!. Very bad) Changes from v2: Swap the place of the change log and commit message. Changes from v1: Used appropriate gpio_* lib calls. board/karo/tx25/tx25.c | 25 +++++++++---------------- 1 files changed, 9 insertions(+), 16 deletions(-) diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 2a29943..07fd98d 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -34,14 +34,13 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FEC_MXC +#define GPIO_FEC_RESET_B MXC_GPIO_PORT_TO_NUM(4, 7) +#define GPIO_FEC_ENABLE_B MXC_GPIO_PORT_TO_NUM(4, 9) void tx25_fec_init(void) { struct iomuxc_mux_ctl *muxctl; struct iomuxc_pad_ctl *padctl; - u32 val; u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); - struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; - struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; debug("tx25_fec_init\n"); @@ -66,18 +65,15 @@ void tx25_fec_init(void) writel(0x0, &padctl->pad_d11); /* drop PHY power and assert reset (low) */ - val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9)); - writel(val, &gpio4->gpio_dr); - val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9); - writel(val, &gpio4->gpio_dir); + gpio_direction_output(GPIO_FEC_RESET_B, 0); + gpio_direction_output(GPIO_FEC_ENABLE_B, 0); mdelay(5); debug("resetting phy\n"); /* turn on PHY power leaving reset asserted */ - val = readl(&gpio4->gpio_dr) | 1 << 9; - writel(val, &gpio4->gpio_dr); + gpio_set_value(GPIO_FEC_ENABLE_B, 1); mdelay(10); @@ -107,19 +103,16 @@ void tx25_fec_init(void) /* * set each to 1 and make each an output */ - val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->gpio_dr); - val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->gpio_dir); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 10), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 11), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 12), 1); mdelay(22); /* this value came from RedBoot */ /* * deassert PHY reset */ - val = readl(&gpio4->gpio_dr) | 1 << 7; - writel(val, &gpio4->gpio_dr); - writel(val, &gpio4->gpio_dr); + gpio_set_value(GPIO_FEC_RESET_B, 1); mdelay(5); -- 1.7.4.1

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[U-Boot] [PATCH] dts/Makefile: Turn off system-/gcc-specific predefined macros
by Horst Kronstorfer 10 Aug '12

10 Aug '12

Add '-undef' to DTS_CPPFLAGS to avoid unwanted expansion of dts content that matches system-specific or gcc-specific predefined macros. Example: A number of PowerPC related *.dts files in the kernel define a property named 'linux,network-index' which (w/o '-undef') is expanded to '1,network-index' by the preprocessor because of '#define linux 1.' With '-undef' in place only the standard predefined macros are visible: $ gcc -dM -E -undef - </dev/null #define __STDC_HOSTED__ 1 #define __STDC__ 1 Signed-off-by: Horst Kronstorfer <hkronsto(a)frequentis.com> --- dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/Makefile b/dts/Makefile index 402dfe1..3c6bc18 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -36,7 +36,7 @@ $(error Your architecture does not have device tree support enabled. \ Please define CONFIG_ARCH_DEVICE_TREE)) # We preprocess the device tree file provide a useful define -DTS_CPPFLAGS := -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" +DTS_CPPFLAGS := -undef -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" all: $(obj).depend $(LIB) -- 1.7.11.2

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[U-Boot] [PATCH] Add support for DS1388.
by Kenth Eriksson 10 Aug '12

10 Aug '12

Support for DS1388 is added by extending the DS1337 driver. DS1388 is similar to DS1337. The time registers are offset by 1 (due to support for hundreds of seconds), and there is no century bit. The configuration and trickle charge registers are also different. Tested on hardware with Freescale P2010 and DS1388. Signed-off-by: Kenth Eriksson <kenth.eriksson(a)transmode.com> --- drivers/rtc/Makefile | 1 + drivers/rtc/ds1337.c | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index faf4fcd..9cfdbf9 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_RTC_DS1307) += ds1307.o COBJS-$(CONFIG_RTC_DS1338) += ds1307.o COBJS-$(CONFIG_RTC_DS1337) += ds1337.o COBJS-$(CONFIG_RTC_DS1374) += ds1374.o +COBJS-$(CONFIG_RTC_DS1388) += ds1337.o COBJS-$(CONFIG_RTC_DS1556) += ds1556.o COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 5bb9f94..4c98732 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -37,6 +37,7 @@ /* * RTC register addresses */ +#if defined CONFIG_RTC_DS1337 #define RTC_SEC_REG_ADDR 0x0 #define RTC_MIN_REG_ADDR 0x1 #define RTC_HR_REG_ADDR 0x2 @@ -47,6 +48,18 @@ #define RTC_CTL_REG_ADDR 0x0e #define RTC_STAT_REG_ADDR 0x0f #define RTC_TC_REG_ADDR 0x10 +#elif defined CONFIG_RTC_DS1388 +#define RTC_SEC_REG_ADDR 0x1 +#define RTC_MIN_REG_ADDR 0x2 +#define RTC_HR_REG_ADDR 0x3 +#define RTC_DAY_REG_ADDR 0x4 +#define RTC_DATE_REG_ADDR 0x5 +#define RTC_MON_REG_ADDR 0x6 +#define RTC_YR_REG_ADDR 0x7 +#define RTC_CTL_REG_ADDR 0x0c +#define RTC_STAT_REG_ADDR 0x0b +#define RTC_TC_REG_ADDR 0x0a +#endif /* * RTC control register bits @@ -87,6 +100,11 @@ int rtc_get (struct rtc_time *tmp) mon_cent = rtc_read (RTC_MON_REG_ADDR); year = rtc_read (RTC_YR_REG_ADDR); + /* No century bit, assume year 2000 */ +#ifdef CONFIG_RTC_DS1388 + mon_cent |= 0x80; +#endif + debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", year, mon_cent, mday, wday, hour, min, sec, control, status); @@ -151,6 +169,7 @@ int rtc_set (struct rtc_time *tmp) * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn * off the OSC output. */ + #ifdef CONFIG_SYS_RTC_DS1337_NOOSC #define RTC_DS1337_RESET_VAL \ (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) @@ -159,10 +178,17 @@ int rtc_set (struct rtc_time *tmp) #endif void rtc_reset (void) { +#ifdef CONFIG_SYS_RTC_DS1337 rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); +#elif defined CONFIG_SYS_RTC_DS1388 + rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */ +#endif #ifdef CONFIG_SYS_DS1339_TCR_VAL rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL); #endif +#ifdef CONFIG_SYS_DS1388_TCR_VAL + rtc_write(RTC_TC_REG_ADDR, CONFIG_SYS_DS1388_TCR_VAL); +#endif } -- 1.7.3.4

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