August 2011 - U-Boot

[U-Boot] [PATCH 1/1] mmc: omap: config VMMC, MMC1_PBIAS
by Balaji T K 25 Aug '11

25 Aug '11

Config VMMC voltage to 3V for MMC/SD card slot and PBIAS settings needed for OMAP4 Fixes MMC/SD detection on boot from eMMC. Signed-off-by: Balaji T K <balajitk(a)ti.com> Signed-off-by: Aneesh V <aneesh(a)ti.com> --- arch/arm/include/asm/arch-omap4/omap4.h | 1 + drivers/mmc/omap_hsmmc.c | 28 +++++++++++++++++++++++++--- drivers/power/twl6030.c | 7 +++++++ include/configs/omap4_sdp4430.h | 2 ++ include/twl6030.h | 3 +++ 5 files changed, 38 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 9aad0e6..13fc8c9 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -55,6 +55,7 @@ #define LPDDR2_IO_REGS_BASE 0x4A100638 #define CONTROL_EFUSE_2 0x4A100704 +#define CONTROL_PBIASLITE 0x4A100600 /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 6627905..95bb661 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -28,6 +28,7 @@ #include <part.h> #include <i2c.h> #include <twl4030.h> +#include <twl6030.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> @@ -38,7 +39,24 @@ static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size); static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz); static struct mmc hsmmc_dev[2]; -unsigned char mmc_board_init(hsmmc_t *mmc_base) + +#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) +static void omap4_vmmc_pbias_config(struct mmc *mmc) +{ + u32 value = 0; + + value = readl(CONTROL_PBIASLITE); + value &= ~((1 << 22) | (1 << 26)); + writel(value, CONTROL_PBIASLITE); + /* set VMMC to 3V */ + twl6030_power_mmc_init(); + value = readl(CONTROL_PBIASLITE); + value |= (1 << 21) | (1 << 22) | (1 << 26); + writel(value, CONTROL_PBIASLITE); +} +#endif + +unsigned char mmc_board_init(struct mmc *mmc) { #if defined(CONFIG_TWL4030_POWER) twl4030_power_mmc_init(); @@ -67,7 +85,11 @@ unsigned char mmc_board_init(hsmmc_t *mmc_base) &prcm_base->iclken1_core); #endif -/* TODO add appropriate OMAP4 init - none currently necessary */ +#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) + /* PBIAS config needed for MMC1 only */ + if (mmc->block_dev.dev == 0) + omap4_vmmc_pbias_config(mmc); +#endif return 0; } @@ -108,7 +130,7 @@ static int mmc_init_setup(struct mmc *mmc) unsigned int dsor; ulong start; - mmc_board_init(mmc_base); + mmc_board_init(mmc); writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, &mmc_base->sysconfig); diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index fef57b4..c5a0038 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -182,6 +182,13 @@ void twl6030_init_battery_charging(void) return; } +void twl6030_power_mmc_init() +{ + /* set voltage to 3.0 and turnon for APP */ + twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x15, VMMC_CFG_VOLTATE); + twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VMMC_CFG_STATE); +} + void twl6030_usb_device_settings() { u8 data = 0; diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 5b3110c..50797ab 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -98,8 +98,10 @@ #define CONFIG_I2C_MULTI_BUS 1 /* TWL6030 */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_TWL6030_POWER 1 #define CONFIG_CMD_BAT 1 +#endif /* MMC */ #define CONFIG_GENERIC_MMC 1 diff --git a/include/twl6030.h b/include/twl6030.h index 6ed68a0..a9fcadb 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -33,6 +33,8 @@ #define TWL6030_CHIP_PWM 0x49 /* Slave Address 0x48 */ +#define VMMC_CFG_STATE 0x9A +#define VMMC_CFG_VOLTATE 0x9B #define VUSB_CFG_STATE 0xA2 #define MISC1 0xE4 @@ -130,3 +132,4 @@ void twl6030_start_usb_charging(void); void twl6030_stop_usb_charging(void); int twl6030_get_battery_voltage(void); int twl6030_get_battery_current(void); +void twl6030_power_mmc_init(void); -- 1.7.0.4

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[U-Boot] bitte lesen und antworten Sie mir dringend <Miss Nicole>..Reply to me urgently < Miss Nicole >
by Nicole Nicole 25 Aug '11

25 Aug '11

Liebste, wie war dein Tag, ich hoffe, alles gut bei dir? Ich entschied mich für Sie, weil meine derzeitige Situation wenden, ich bin in einer privaten Hilfsorganisation Aufenthalt unter St Johns Church hier in Ouagadougou in Burkina-Faso und ich bete, dass Gott das Herz berühren, zu verstehen und gib mir deine helfende Hand Ich bin Miss, Nicole Moses Akumi, und ich bin ein Mädchen von 24 Jahre alt, ein Medizinstudent, mein Vater seligen Angedenkens nach Name verstorbenen Herrn Moses Akumi, die ein Manager mit CNPC Ölgesellschaft wurde an der Khartoum-Raffinerie in Sudan, wurde an der Seite mit meiner geliebten Mutter und unsere Familie Haus von den Rebellen während der letzten Krise in meinem Land verbrannt getötet Ich bin jetzt schreibe Ihnen aus Ouagadougou Burkina-Faso, wo ich durch Straße entkommen, und jetzt um Asyl in einem privaten Hilfsorganisation unter St Johns Church hier in Ouagadougou in Burkina-Faso, können Sie mehr von meiner Geschichte über folgende Seite im Netz zu finden BBC News http://news.bbc.co.uk/2/hi/africa/6469857.stm so bin ich jetzt auf der Suche nach einem ehrlichen und zuverlässigen Person, die Hilfe für mich auf jeden der westlichen Welt zu verlagern nach einem besseren Leben und zu meinem Studium fortsetzen will, habe ich gewählt, um Ihnen nach Durchlaufen Ihr Profil Kontakt und ich glaube, Sie sind eine zuverlässige Person, die nicht im Stich lässt mich oder mein Vertrauen verraten Ich weiß, Sie fragen sich vielleicht, warum ich so bald erzählen Sie über all das, auch ohne zu sehen oder zu wissen Sie ganz genau, wirklich etwas in mir sagt mir, dass du ein guter Mensch sind und ich denke, ich bin nicht falsch kurz will ich gerne etwas mehr über mich dir offenbaren und sehen, wenn Sie dazu beitragen können, um Ihr Land zu verlagern, um so mit meinem Studium fortsetzen und ein neues Leben, und bitte dies ist ein wenig abzusondern und flehe ich Sie zu halten es sich selbst allein, bis alles richtig angeordnet und ausgeführt wird, dann werde ich kommen, um Sie in Ihrem Land beitreten Ich habe die Summe von 5,2 Millionen Dollar als Erbe von meinem verstorbenen Vater, die Ich mag, um in Ihrem Land mit Ihrer Hilfe zu investieren wird, ist der Grund, warum ich brauche deine Hilfe auf Anweisung meines verstorbenen Vaters an die Bank gab in den Fonds-Release mir im Alter von 24 durch einen Ausländer, der mir helfen kann, den Fonds klug investieren, und es hat mein Vater den Wunsch für mich, einen Ausländer zu heiraten, so wird die Bank nicht freigeben der Fonds für mich ohne die Hilfe eines Ausländers wie mein Vater wies die Bank Dieser Fonds ist in meinem verstorbenen Vater das Bankkonto mit einer der Banken hier in Burkina-Faso hinterlegt und ich werde Ihnen alle Details / Kontakt, weil ich das Geld auf Ihr Konto überwiesen werden, bevor ich zu Ihnen kommen kommen wollen in Ihrem Land, ich will dich mit 15% des gesamten Fonds zu kompensieren, und Sie können mir auch helfen, um meinen eigenen Teil in jedem guten Geschäft zu investieren, möchte ich mein Studium beenden, weil ich Arzt werden, so dass ich positiv beitragen können wollen die Menschheit, i Ihre dringende Antwort auf Ihre Fähigkeit, das für mich verarbeiten, so dass i wird Ihnen sagen, den nächsten Schritt brauchen, weil ich zu diesem Flüchtlingslager so schnell wie möglich verlassen wollen, ist das Leben hier, um mir eine Hölle gibt, keine Liebe, keine Zuneigung und keine Annehmlichkeiten, was noch wichtiger ist, ich meine Studien Liebe und hier nichts los ist und die Menschen hier sind nicht freundlich, ich bin wirklich Leid an diesem Ort, es ist zu schmerzhaft, aber ich hoffe, mit Ihrer Hilfe, um die Übertragung der Fonds in Ihrem Konto , werde ich ein besseres Leben zu leben so freundlich mir Ihre Bereitschaft, mir zu helfen und ich verspreche, immer nett sein und dir treu, ich will gerne mit 15% des gesamten Fonds für die Hilfe zu kompensieren, und Sie können mir auch helfen, den Fonds zu investieren, während Ich setze meine Studien, weil ich Arzt werden wollen, ist es mein Wunsch, einen positiven Beitrag für die Menschheit Ich schicke Ihnen mein Foto und ich hoffe, Ihnen und Ihrer Telefonnummer, damit wir per Telefon sprechen kann und ich werde auch gerne deine Stimme zu hören Vielen Dank und Gott segne Sie Mit freundlichen Grüßen, Von Nicole ........................ dearest, how was your day, i hope everything is well with you? i decided to contact you because of my present situation, i am staying in a private charity organization under St Johns Church here in Ouagadougou Burkina-Faso and i pray that God will touch your heart to understand and give me your helping hand i am miss, Nicole Moses Akumi, and i am a girl of 24 years old, a medical student, my father of blessed memory by name late Mr. Moses Akumi who was the a manager with CNPC oil company at the Khartoum refinery in Sudan, was killed along side with my beloved mother and our family house burnt down by the rebels during the last crisis in my country i am now writing you from Ouagadougou Burkina-Faso where i escaped through road, and now seeking asylum in a private charity organization under St Johns Church here in Ouagadougou Burkina-Faso, you can find more of my story through the following site on the net bbc news http://news.bbc.co.uk/2/hi/africa/6469857.stm so i am now in search of an honest and reliable person who will help to relocate me in any of the western world for a better life and to continue my studies, i have chosen to contact you after going through your profile and i believe you are a reliable person who will not let me down or betray my trust i know you may wonder why i am so soon telling you about all this, even without seeing or knowing you fully well, really something in me tells me that you are a good person and i guess i am not wrong briefly i will like to disclose little more about myself to you and see if you can help to relocate to your country so as to continue with my studies and have a new life, and please this is a little secrete and i plead with you to keep it to yourself alone until everything is properly arranged and executed, then i will come over to join you in your country i have the sum of $5.2 Million as an inheritance from my late father which i will like to invest in your country with your help, the reason why i need your help is based on the instruction my late father gave to the bank to release the fund to me at the age of 24 through a foreigner who can help me to invest the fund wisely, and it has been my father's desire for me to marry a foreigner, so the bank will not release the fund to me without the help of a foreigner as my father instructed the bank this fund is deposited in my late father's bank account with one of the banks here in Burkina-Faso and i am going to give you all the details / contact because i want the money to be transferred to your account before i come over to join you in your country, I will compensate you with 15% of the total fund and you can also help me to invest my own part into any good business, I want to finish my studies because I want to be a doctor so that I can contribute positively to humanity, i need your urgent answer of your ability to handle this for me so that i will tell you the next step because i want to leave this refugee camp as soon as possible, life here is to me a hell, no love, no affection and no amenities, more importantly, i love my studies and here nothing is happening and people here are not friendly, i am really suffering in this place, it is too painful, but i hope with your help to transferring the fund in your account, i will have a better life to live so kindly let me know your readiness to help me and i promise to always be nice and faithful to you, I will glad to compensate you with 15% of the total fund for helping me, and you can also help me to invest the fund while I continue my studies because I want to be a doctor, it is my desire to contribute positively to humanity i will send you my photo and i hope to have yours and your phone number so that we can talk through phone and i will also like to hear your voice thank you and God bless you sincerely yours, Nicole

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[U-Boot] phylib + mii + <phy>_parse_status
by Michal Simek 25 Aug '11

25 Aug '11

Hi, I have done some experiments with phylib and Xilinx ethernet drivers and I found that mii code show different values for speed and duplex. I think that the main problem is that there are called miiphy_speed and miiphy_duplex functions instead of phy parsing functions. I think that it will be the best to extend struct phy_driver for int (*parse_status)(struct phy_device *phydev); and then reread phydev->speed or phydev->duplex instead of using generic code which does wrong things. Then will be good to synchronize FULL/HALF and DUPLEX_FULL/DUPLEX_HALF. miiphy.h #define HALF 22 #define FULL 44 include/linux/ethtool.h #define DUPLEX_HALF 0x00 #define DUPLEX_FULL 0x01 And of course speeds: miiphy.h #define _1000BASET 1000 #define _100BASET 100 #define _10BASET 10 include/linux/ethtool.h #define SPEED_10 10 #define SPEED_100 100 #define SPEED_1000 1000 #define SPEED_2500 2500 #define SPEED_10000 10000 Have someone looked at it? Any comments? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian

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[U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
by Ajay Bhargav 25 Aug '11

25 Aug '11

This patch adds support for Fast Ethernet Controller driver for Armada100 series. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- Changes for v2: - removed random MAC generation - driver init function changed to register as per new naming convention - code cleanup (Thanks to Wolfgang, Marek & Mike for tips) arch/arm/include/asm/arch-armada100/armada100.h | 1 + drivers/net/Makefile | 1 + drivers/net/armada100_fec.c | 761 +++++++++++++++++++++++ drivers/net/armada100_fec.h | 232 +++++++ include/netdev.h | 1 + 5 files changed, 996 insertions(+), 0 deletions(-) create mode 100644 drivers/net/armada100_fec.c create mode 100644 drivers/net/armada100_fec.h diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index d5d125a..3d567eb 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -59,6 +59,7 @@ #define ARMD1_MPMU_BASE 0xD4050000 #define ARMD1_APMU_BASE 0xD4282800 #define ARMD1_CPU_BASE 0xD4282C00 +#define ARMD1_FEC_BASE 0xC0800000 /* * Main Power Management (MPMU) Registers diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 819b197..34b4322 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libnet.o COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o +COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c new file mode 100644 index 0000000..e36dca6 --- /dev/null +++ b/drivers/net/armada100_fec.c @@ -0,0 +1,761 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Contributor: Mahavir Jain <mjain(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/types.h> +#include <asm/byteorder.h> +#include <linux/err.h> +#include <linux/mii.h> +#include <asm/io.h> +#include <asm/arch/armada100.h> +#include "armada100_fec.h" + +#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */ + +#ifdef DEBUG +static int eth_dump_regs(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + unsigned int i = 0; + + printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr)); + printf("offset: smi, value: 0x%x\n", readl(&regs->smi)); + for (i = 0x400; i <= 0x4e4; i += 4) + printf("offset: 0x%x, value: 0x%x\n", + i, readl(ARMD1_FEC_BASE + i)); + return 0; +} +#endif + +static int armdfec_phy_timeout(u32 reg, u32 flag, int cond) +{ + u32 timeout = PHY_WAIT_ITERATIONS; + while (--timeout) { + if (cond && (readl(reg) & flag)) + break; + else if (!cond && !(readl(reg) & flag)) + break; + udelay(PHY_WAIT_MICRO_SECONDS); + } + return !timeout; +} + +static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, + u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + u32 val, reg_data; + + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { + reg_data = readl(&regs->phyadr); + *value = (u16) (reg_data & 0x1f); + return 0; + } + + /* check parameters */ + if (phy_addr > PHY_MASK) { + printf("Err..(%s) Invalid phy address: 0x%X\n", + __func__, phy_addr); + return -EINVAL; + } + if (phy_reg > PHY_MASK) { + printf("Err..(%s) Invalid register offset: 0x%X\n", + __func__, phy_reg); + return -EINVAL; + } + + /* wait for the SMI register to become available */ + if (armdfec_phy_timeout((u32)&regs->smi, SMI_BUSY, FALSE)) { + printf("Error (%s) PHY busy timeout\n", __func__); + return -1; + } + + writel(phy_addr << 16 | phy_reg << 21 | SMI_OP_R, &regs->smi); + + /* now wait for the data to be valid */ + if (armdfec_phy_timeout((u32)&regs->smi, SMI_R_VALID, TRUE)) { + val = readl(&regs->smi); + printf("Err (%s) PHY Read timeout, val=0x%x\n", __func__, val); + return -1; + } + val = readl(&regs->smi); + *value = val & 0xffff; + + return 0; +} + +static int smi_reg_write(const char *devname, + u8 phy_addr, u8 phy_reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { + clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f); + return 0; + } + + /* check parameters */ + if (phy_addr > PHY_MASK) { + printf("Err..(%s) Invalid phy address\n", __func__); + return -EINVAL; + } + if (phy_reg > PHY_MASK) { + printf("Err..(%s) Invalid register offset\n", __func__); + return -EINVAL; + } + + /* wait for the SMI register to become available */ + if (armdfec_phy_timeout((u32)&regs->smi, SMI_BUSY, FALSE)) { + printf("Error (%s) PHY busy timeout\n", __func__); + return -1; + } + + writel(phy_addr << 16 | phy_reg << 21 | SMI_OP_W | (value & 0xffff), + &regs->smi); + return 0; +} + +/* + * Abort any transmit and receive operations and put DMA + * in idle state. AT and AR bits are cleared upon entering + * in IDLE state. So poll those bits to verify operation. + */ +static void abortdma(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + int delay; + int maxretries = 40; + + do { + writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd); + udelay(100); + + delay = 10; + while ((readl(&regs->sdma_cmd) & + (SDMA_CMD_AR | SDMA_CMD_AT)) + && delay-- > 0) { + udelay(10); + } + } while (maxretries-- > 0 && delay <= 0); + + if (maxretries <= 0) + printf("%s : DMA Stuck\n", __func__); +} + +static inline u32 nibble_swapping_32_bit(u32 x) +{ + return (((x) & 0xf0f0f0f0) >> 4) | (((x) & 0x0f0f0f0f) << 4); +} + +static inline u32 nibble_swapping_16_bit(u32 x) +{ + return (((x) & 0x0000f0f0) >> 4) | (((x) & 0x00000f0f) << 4); +} + +static inline u32 flip_4_bits(u32 x) +{ + return (((x) & 0x01) << 3) | (((x) & 0x002) << 1) + | (((x) & 0x04) >> 1) | (((x) & 0x008) >> 3); +} + +/* + * This function will calculate the hash function of the address. + * depends on the hash mode and hash size. + * Inputs + * mach - the 2 most significant bytes of the MAC address. + * macl - the 4 least significant bytes of the MAC address. + * Outputs + * return the calculated entry. + */ +static u32 hash_function(u32 mach, u32 macl) +{ + u32 hashresult; + u32 addrh; + u32 addrl; + u32 addr0; + u32 addr1; + u32 addr2; + u32 addr3; + u32 addrhswapped; + u32 addrlswapped; + + addrh = nibble_swapping_16_bit(mach); + addrl = nibble_swapping_32_bit(macl); + + addrhswapped = flip_4_bits(addrh & 0xf) + + ((flip_4_bits((addrh >> 4) & 0xf)) << 4) + + ((flip_4_bits((addrh >> 8) & 0xf)) << 8) + + ((flip_4_bits((addrh >> 12) & 0xf)) << 12); + + addrlswapped = flip_4_bits(addrl & 0xf) + + ((flip_4_bits((addrl >> 4) & 0xf)) << 4) + + ((flip_4_bits((addrl >> 8) & 0xf)) << 8) + + ((flip_4_bits((addrl >> 12) & 0xf)) << 12) + + ((flip_4_bits((addrl >> 16) & 0xf)) << 16) + + ((flip_4_bits((addrl >> 20) & 0xf)) << 20) + + ((flip_4_bits((addrl >> 24) & 0xf)) << 24) + + ((flip_4_bits((addrl >> 28) & 0xf)) << 28); + + addrh = addrhswapped; + addrl = addrlswapped; + + addr0 = (addrl >> 2) & 0x03f; + addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2); + addr2 = (addrl >> 15) & 0x1ff; + addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8); + + hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); + hashresult = hashresult & 0x07ff; + return hashresult; +} + +/* + * This function will add an entry to the address table. + * depends on the hash mode and hash size that was initialized. + * Inputs + * mach - the 2 most significant bytes of the MAC address. + * macl - the 4 least significant bytes of the MAC address. + * skip - if 1, skip this address. + * rd - the RD field in the address table. + * Outputs + * address table entry is added. + * 0 if success. + * -ENOSPC if table full + */ +static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach, + u32 macl, u32 rd, u32 skip, int del) +{ + struct addr_table_entry_t *entry, *start; + u32 newhi; + u32 newlo; + u32 i; + u8 *last; + + newlo = (((mach >> 4) & 0xf) << 15) + | (((mach >> 0) & 0xf) << 11) + | (((mach >> 12) & 0xf) << 7) + | (((mach >> 8) & 0xf) << 3) + | (((macl >> 20) & 0x1) << 31) + | (((macl >> 16) & 0xf) << 27) + | (((macl >> 28) & 0xf) << 23) + | (((macl >> 24) & 0xf) << 19) + | (skip << HTESKIP) | (rd << HTERDBIT) + | HTEVALID; + + newhi = (((macl >> 4) & 0xf) << 15) + | (((macl >> 0) & 0xf) << 11) + | (((macl >> 12) & 0xf) << 7) + | (((macl >> 8) & 0xf) << 3) + | (((macl >> 21) & 0x7) << 0); + + /* + * Pick the appropriate table, start scanning for free/reusable + * entries at the index obtained by hashing the specified MAC address + */ + start = (struct addr_table_entry_t *) (darmdfec->htpr); + entry = start + hash_function(mach, macl); + for (i = 0; i < HOP_NUMBER; i++) { + if (!(entry->lo & HTEVALID)) { + break; + } else { + /* if same address put in same position */ + if (((entry->lo & 0xfffffff8) == + (newlo & 0xfffffff8)) + && (entry->hi == newhi)) { + break; + } + } + if (entry == start + 0x7ff) + entry = start; + else + entry++; + } + + if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) && + (entry->hi != newhi) && del) + return 0; + + if (i == HOP_NUMBER) { + if (!del) { + printf("%s: table section is full\n", __FILE__); + return -ENOSPC; + } else { + return 0; + } + } + + /* + * Update the selected entry + */ + if (del) { + entry->hi = 0; + entry->lo = 0; + } else { + entry->hi = newhi; + entry->lo = newlo; + } + + last = (u8 *) entry; + last = last + sizeof(*entry); + + return 0; +} + +/* + * Create an addressTable entry from MAC address info + * found in the specifed net_device struct + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + */ +static void update_hash_table_mac_address(struct armdfec_device *darmdfec, + u8 *oaddr, u8 *addr) +{ + u32 mach; + u32 macl; + + /* Delete old entry */ + if (oaddr) { + mach = (oaddr[0] << 8) | oaddr[1]; + macl = (oaddr[2] << 24) | (oaddr[3] << 16) | + (oaddr[4] << 8) | oaddr[5]; + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE); + } + + /* Add new entry */ + mach = (addr[0] << 8) | addr[1]; + macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD); +} + +/* Address Table Initialization */ +static void init_hashtable(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE); + writel((u32) darmdfec->htpr, &regs->htpr); +} + +static int setportconfigext(struct eth_device *dev, int mtu) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + int mtusize; + + /* 64 should work but does not -- dhcp packets NEVER get transmitted. */ + if ((mtu > MAX_PKT_SIZE) || (mtu < 64)) + return -EINVAL; + + /* add source/dest mac addr (12) + pid (2) + crc (4) */ + mtu += ETH_EXTRA_HEADER; + if (mtu <= 1518) + mtusize = PCXR_MFL_1518; + else if (mtu <= 1536) + mtusize = PCXR_MFL_1536; + else if (mtu <= 2048) + mtusize = PCXR_MFL_2048; + else + mtusize = PCXR_MFL_64K; + + /* Extended Port Configuration */ + writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */ + PCXR_DSCP_EN | /* Enable DSCP in IP */ + mtusize | PCXR_FLP | /* do not force link pass */ + PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */ + &regs->pconf_ext); + + /* subtract source/dest mac addr (12) + pid (2) + crc (4) */ + mtu -= ETH_EXTRA_HEADER; + return 0; +} + +/* + * This detects PHY chip from address 0-31 by reading PHY status + * registers. PHY chip can be connected at any of this address. + */ +static int ethernet_phy_detect(struct eth_device *dev) +{ + u32 val; + u16 tmp, mii_status; + u8 addr; + + for (addr = 0; addr < 32; addr++) { + if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0) + /* try next phy */ + continue; + + /* invalid MII status. More validation required here... */ + if (mii_status == 0 || mii_status == 0xffff) + /* try next phy */ + continue; + + if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0) + /* try next phy */ + continue; + + val = tmp << 16; + if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0) + /* try next phy */ + continue; + + val |= tmp; + + if ((val & 0xfffffff0) != 0) + return addr; + } + return -1; +} + +static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec) +{ + struct rx_desc *p_rx_desc; + int i; + + /* initialize the Rx descriptors ring */ + p_rx_desc = darmdfec->p_rxdesc; + for (i = 0; i < RINGSZ; i++) { + p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; + p_rx_desc->buf_size = PKTSIZE_ALIGN; + p_rx_desc->byte_cnt = 0; + p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN; + if (i == (RINGSZ - 1)) + p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc; + else { + p_rx_desc->nxtdesc_p = (struct rx_desc *) + ((u32) p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE); + p_rx_desc = p_rx_desc->nxtdesc_p; + } + } + darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc; +} + +static int armdfec_init(struct eth_device *dev, bd_t *bd) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + + armdfec_init_rx_desc_ring(darmdfec); + + /* Disable interrupts */ + writel(0, &regs->im); + writel(0, &regs->ic); + /* Write to ICR to clear interrupts. */ + writel(0, &regs->iwc); + + /* + * Abort any transmit and receive operations and put DMA + * in idle state. + */ + abortdma(dev); + + /* Initialize address hash table */ + init_hashtable(dev); + + /* SDMA configuration */ + writel(SDCR_BSZ8 | /* Burst size = 32 bytes */ + SDCR_RIFB | /* Rx interrupt on frame */ + SDCR_BLMT | /* Little endian transmit */ + SDCR_BLMR | /* Little endian receive */ + SDCR_RC_MAX_RETRANS, /* Max retransmit count */ + &regs->sdma_conf); + /* Port Configuration */ + writel(PCR_HS, &regs->pconf); /* Hash size is 1/2kb */ + setportconfigext(dev, 1500); + + update_hash_table_mac_address(darmdfec, dev->enetaddr, dev->enetaddr); + + /* Update TX and RX queue descriptor register */ + writel((u32) darmdfec->p_txdesc, &regs->txcdp[TXQ]); + writel((u32) darmdfec->p_rxdesc, &regs->rxfdp[RXQ]); + writel((u32) darmdfec->p_rxdesc_curr, &regs->rxcdp[RXQ]); + + /* Enable Interrupts */ + writel(ALL_INTS, &regs->im); + + /* Enable Ethernet Port */ + setbits_le32(&regs->pconf, PCR_EN); + + /* Enable RX DMA engine */ + setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD); + +#ifdef DEBUG + eth_dump_regs(dev); +#endif + +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ + && defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) + /* Wait up to 5s for the link status */ + for (i = 0; i < 5; i++) { + u16 phy_adr; + + miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr); + /* Return if we get link up */ + if (miiphy_link(dev->name, phy_adr)) + return 0; + udelay(1000000); + } + + printf("No link on %s\n", dev->name); + return -1; +#endif + return 0; +} + +static void armdfec_halt(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + + /* Stop RX DMA */ + clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD); + + /* + * Abort any transmit and receive operations and put DMA + * in idle state. + */ + abortdma(dev); + + /* Disable interrupts */ + writel(0, &regs->im); + writel(0, &regs->ic); + writel(0, &regs->iwc); + + /* Disable Port */ + clrbits_le32(&regs->pconf, PCR_EN); +} + +static int armdfec_send(struct eth_device *dev, volatile void *dataptr, + int datasize) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + struct tx_desc *p_txdesc = darmdfec->p_txdesc; + void *p = (void *) dataptr; + int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS; + u32 cmd_sts; + + /* Copy buffer if it's misaligned */ + if ((u32) dataptr & 0x07) { + if (datasize > PKTSIZE_ALIGN) { + printf("Non-aligned data too large (%d)\n", datasize); + return -1; + } + memcpy(darmdfec->p_aligned_txbuf, p, datasize); + p = darmdfec->p_aligned_txbuf; + } + + p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; + p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; + p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; + p_txdesc->cmd_sts |= TX_EN_INT; + p_txdesc->buf_ptr = (u8 *)p; + p_txdesc->byte_cnt = datasize; + + /* Apply send command using high priority TX queue */ + writel((u32) p_txdesc, &regs->txcdp[TXQ]); + writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd); + + /* + * wait for packet xmit completion + */ + cmd_sts = readl(&p_txdesc->cmd_sts); + while (cmd_sts & BUF_OWNED_BY_DMA) { + /* return fail if error is detected */ + if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) == + (TX_ERROR | TX_LAST_DESC)) { + printf("Err..(%s) in xmit packet\n", __func__); + return -1; + } + cmd_sts = readl(&p_txdesc->cmd_sts); + if (!(retry--)) { + printf("%s: xmit packet timeout!\n", __func__); + return -1; + } + }; + + return 0; +} + +static int armdfec_recv(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; + u32 cmd_sts; + u32 timeout = 0; + + /* wait untill rx packet available or timeout */ + do { + if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) + timeout++; + else { + debug("%s time out...\n", __func__); + return -1; + } + } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA); + + if (p_rxdesc_curr->byte_cnt != 0) { + debug + ("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", + __func__, (u32) p_rxdesc_curr->byte_cnt, + (u32) p_rxdesc_curr->buf_ptr, + (u32) p_rxdesc_curr->cmd_sts); + } + + /* + * In case received a packet without first/last bits on + * OR the error summary bit is on, + * the packets needs to be dropeed. + */ + cmd_sts = readl(&p_rxdesc_curr->cmd_sts); + + if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) + != (RX_FIRST_DESC | RX_LAST_DESC)) { + + printf("Err..(%s) Dropping packet spread on" + " multiple descriptors\n", __func__); + } else if (cmd_sts & RX_ERROR) { + printf("Err..(%s) Dropping packet with errors\n", + __func__); + } else { + /* !!! call higher layer processing */ + debug("%s: Sending Received packet to" + " upper layer (NetReceive)\n", __func__); + + /* + * let the upper layer handle the packet, subtract offset + * as two dummy bytes are added in received buffer see + * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit. + */ + NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), + (int) (p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); + } + /* + * free these descriptors and point next in the ring + */ + p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; + p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; + p_rxdesc_curr->byte_cnt = 0; + + writel((u32) p_rxdesc_curr->nxtdesc_p, &darmdfec->p_rxdesc_curr); + + return 0; +} + +int armada100_fec_register() +{ + struct armdfec_device *darmdfec; + struct eth_device *dev; + int phy_adr; + + darmdfec = malloc(sizeof(struct armdfec_device)); + if (!darmdfec) + goto error; + + memset(darmdfec, 0, sizeof(struct armdfec_device)); + + darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE); + if (!darmdfec->htpr) + goto error; + + darmdfec->p_rxdesc = (struct rx_desc *) memalign(PKTALIGN, + ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1); + + if (!darmdfec->p_rxdesc) + goto error; + + darmdfec->p_rxbuf = (u8 *) memalign(PKTALIGN, + RINGSZ * PKTSIZE_ALIGN + 1); + if (!darmdfec->p_rxbuf) + goto error; + + darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); + if (!darmdfec->p_aligned_txbuf) + goto error; + + darmdfec->p_txdesc = (struct tx_desc *) + memalign(PKTALIGN, sizeof(struct tx_desc) + 1); + if (!darmdfec->p_txdesc) + goto error; + + dev = &darmdfec->dev; + /* Assign ARMADA100 Fast Ethernet Controller Base Address */ + darmdfec->regs = (void *) ARMD1_FEC_BASE; + + /* must be less than NAMESIZE (16) */ + strcpy(dev->name, "armd-fec0"); + + /* Read mac from env if available */ + eth_getenv_enetaddr("ethaddr", dev->enetaddr); + + dev->init = armdfec_init; + dev->halt = armdfec_halt; + dev->send = armdfec_send; + dev->recv = armdfec_recv; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, smi_reg_read, smi_reg_write); + +#if defined(CONFIG_PHY_BASE_ADR) + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, + (u16) CONFIG_PHY_BASE_ADR); +#else + /* Search phy address from range 0-31 */ + phy_adr = ethernet_phy_detect(dev); + if (phy_adr < 0) { + printf("Error: PHY not detected at address range 0-31\n"); + return -1; + } else { + debug("PHY detected at addr %d\n", phy_adr); + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, (u16)phy_adr); + } +#endif +#endif + return 0; + +error: + free(darmdfec->p_aligned_txbuf); + free(darmdfec->p_rxbuf); + free(darmdfec->p_rxdesc); + free(darmdfec->htpr); + free(darmdfec); + printf("Err.. %s Failed to allocate memory\n", __func__); + return -1; +} diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h new file mode 100644 index 0000000..e2df4fc --- /dev/null +++ b/drivers/net/armada100_fec.h @@ -0,0 +1,232 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Contributor: Mahavir Jain <mjain(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARMADA100_FEC_H__ +#define __ARMADA100_FEC_H__ + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define PORT_NUM 0x0 + +/* RX & TX descriptor command */ +#define BUF_OWNED_BY_DMA (1<<31) + +/* RX descriptor status */ +#define RX_EN_INT (1<<23) +#define RX_FIRST_DESC (1<<17) +#define RX_LAST_DESC (1<<16) +#define RX_ERROR (1<<15) + +/* TX descriptor command */ +#define TX_EN_INT (1<<23) +#define TX_GEN_CRC (1<<22) +#define TX_ZERO_PADDING (1<<18) +#define TX_FIRST_DESC (1<<17) +#define TX_LAST_DESC (1<<16) +#define TX_ERROR (1<<15) + +/* smi register */ +#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */ +#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */ +#define SMI_OP_W (0<<26) /* Write operation */ +#define SMI_OP_R (1<<26) /* Read operation */ + +#define HASH_ADD 0 +#define HASH_DELETE 1 +#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ +#define HOP_NUMBER 12 + +#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ +#define PHY_WAIT_MICRO_SECONDS 10 + +#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ +#define ETH_EXTRA_HEADER (6+6+2+4) + /* dest+src addr+protocol id+crc */ +#define MAX_PKT_SIZE 1536 + + +/* Bit definitions of the SDMA Config Reg */ +#define SDCR_BSZ_OFF 12 +#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF) +#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF) +#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF) +#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF) +#define SDCR_BLMR (1<<6) +#define SDCR_BLMT (1<<7) +#define SDCR_RIFB (1<<9) +#define SDCR_RC_OFF 2 +#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) + +/* SDMA_CMD */ +#define SDMA_CMD_AT (1<<31) +#define SDMA_CMD_TXDL (1<<24) +#define SDMA_CMD_TXDH (1<<23) +#define SDMA_CMD_AR (1<<15) +#define SDMA_CMD_ERD (1<<7) + + +/* Bit definitions of the Port Config Reg */ +#define PCR_HS (1<<12) +#define PCR_EN (1<<7) +#define PCR_PM (1<<0) + +/* Bit definitions of the Port Config Extend Reg */ +#define PCXR_2BSM (1<<28) +#define PCXR_DSCP_EN (1<<21) +#define PCXR_MFL_1518 (0<<14) +#define PCXR_MFL_1536 (1<<14) +#define PCXR_MFL_2048 (2<<14) +#define PCXR_MFL_64K (3<<14) +#define PCXR_FLP (1<<11) +#define PCXR_PRIO_TX_OFF 3 +#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF) + +/* + * * Bit definitions of the Interrupt Cause Reg + * * and Interrupt MASK Reg is the same + * */ +#define ICR_RXBUF (1<<0) +#define ICR_TXBUF_H (1<<2) +#define ICR_TXBUF_L (1<<3) +#define ICR_TXEND_H (1<<6) +#define ICR_TXEND_L (1<<7) +#define ICR_RXERR (1<<8) +#define ICR_TXERR_H (1<<10) +#define ICR_TXERR_L (1<<11) +#define ICR_TX_UDR (1<<13) +#define ICR_MII_CH (1<<28) + +#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ + ICR_TXERR_H | ICR_TXERR_L |\ + ICR_TXEND_H | ICR_TXEND_L |\ + ICR_RXBUF | ICR_RXERR | ICR_MII_CH) + +#define PHY_MASK 0x0000001f + +#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev) +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \ + (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN) + +#define RX_BUF_OFFSET 0x2 +#define RXQ 0x0 /* RX Queue 0 */ +#define TXQ 0x1 /* TX Queue 1 */ + +struct addr_table_entry_t { + u32 lo; + u32 hi; +}; + +/* Bit fields of a Hash Table Entry */ +enum hash_table_entry { + HTEVALID = 1, + HTESKIP = 2, + HTERD = 4, + HTERDBIT = 2 +}; + +struct tx_desc { + u32 cmd_sts; /* Command/status field */ + u16 reserved; + u16 byte_cnt; /* buffer byte count */ + u8 *buf_ptr; /* pointer to buffer for this descriptor */ + struct tx_desc *nextdesc_p; /* Pointer to next descriptor */ +}; + +struct rx_desc { + u32 cmd_sts; /* Descriptor command status */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u16 buf_size; /* Buffer size */ + u8 *buf_ptr; /* Descriptor buffer pointer */ + struct rx_desc *nxtdesc_p; /* Next descriptor pointer */ +}; + +/* + * Armada100 Fast Ethernet controller Registers + * Refer Datasheet Appendix A.22 + */ +struct armdfec_reg { + u32 phyadr; /* PHY Address */ + u32 pad1[3]; + u32 smi; /* SMI */ + u32 pad2[0xFB]; + u32 pconf; /* Port configuration */ + u32 pad3; + u32 pconf_ext; /* Port configuration extend */ + u32 pad4; + u32 pcmd; /* Port Command */ + u32 pad5; + u32 pstatus; /* Port Status */ + u32 pad6; + u32 spar; /* Serial Parameters */ + u32 pad7; + u32 htpr; /* Hash table pointer */ + u32 pad8; + u32 fcsal; /* Flow control source address low */ + u32 pad9; + u32 fcsah; /* Flow control source address high */ + u32 pad10; + u32 sdma_conf; /* SDMA configuration */ + u32 pad11; + u32 sdma_cmd; /* SDMA command */ + u32 pad12; + u32 ic; /* Interrupt cause */ + u32 iwc; /* Interrupt write to clear */ + u32 im; /* Interrupt mask */ + u32 pad13; + u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code + Point to Priority 0 Low */ + u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */ + u32 pad14[3]; + struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor + Pointer */ + u32 pad15[4]; + struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor + Pointer */ + u32 pad16[0x0C]; + struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor + Pointer */ +}; + +struct armdfec_device { + struct eth_device dev; + struct armdfec_reg *regs; + struct tx_desc *p_txdesc; + struct rx_desc *p_rxdesc; + struct rx_desc *p_rxdesc_curr; + u8 *p_rxbuf; + u8 *p_aligned_txbuf; + u8 *htpr; /* hash pointer */ +}; + +#endif /* __ARMADA100_FEC_H__ */ diff --git a/include/netdev.h b/include/netdev.h index 6f0a971..d12f179 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -94,6 +94,7 @@ int xilinx_emaclite_initialize (bd_t *bis, int base_addr); int sh_eth_initialize(bd_t *bis); int dm9000_initialize(bd_t *bis); int fecmxc_initialize(bd_t *bis); +int armada100_fec_register(void); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. -- 1.7.0.4

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[U-Boot] [PATCH] Error : Not finding asm/arch/gpio.h
by Faisal H 25 Aug '11

25 Aug '11

While building with omap3_beagle_config configuration, getting an error about not finding asm/arch/gpio.h (which does not exist). Found that header files are moved to arch/arm/include/asm/arch-. Fixed the includes to find the file.. Signed-off-by: Faisal Hassan<faah87(a)gmail.com> Cc: Wolfgang Denk<wd(a)denx.de> --- a/board/cm-bf537e/gpio_cfi_flash.c +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -8,7 +8,7 @@ #include<common.h> #include<asm/blackfin.h> -#include<asm/gpio.h> +#include<asm/mach-bf537/gpio.h> #include<asm/io.h> #include "gpio_cfi_flash.h" --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -11,7 +11,7 @@ #include<config.h> #include<malloc.h> #include<asm/blackfin.h> -#include<asm/gpio.h> +#include<asm/mach-bf548/gpio.h> #include<asm/portmux.h> #include<asm/mach-common/bits/dma.h> #include<i2c.h> --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -11,7 +11,7 @@ #include<command.h> #include<netdev.h> #include<asm/blackfin.h> -#include<asm/gpio.h> +#include<asm/mach-bf548/gpio.h> #include<asm/portmux.h> #include<asm/sdh.h> --- a/board/bf537-stamp/post.c +++ b/board/bf537-stamp/post.c @@ -12,7 +12,7 @@ #include<config.h> #include<command.h> #include<asm/blackfin.h> -#include<asm/gpio.h> +#include<asm/mach-bf537/gpio.h> /* Using sw10-PF5 as the hotkey */ int post_hotkeys_pressed(void) --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -27,7 +27,7 @@ #include<common.h> #include<netdev.h> -#include<asm/gpio.h> +#include<asm/mach-bf533/gpio.h> DECLARE_GLOBAL_DATA_PTR; --- a/board/bf527-sdp/bf527-sdp.c +++ b/board/bf527-sdp/bf527-sdp.c @@ -8,7 +8,7 @@ #include<common.h> #include<asm/blackfin.h> -#include<asm/gpio.h> +#include<asm/mach-bf527/gpio.h> #include<asm/mach-common/bits/pll.h> int checkboard(void) --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -12,7 +12,7 @@ #include<net.h> #include<netdev.h> #include<asm/blackfin.h> -#include<asm/gpio.h> +#include<mach-bf527/gpio.h> #include<asm/net.h> #include<asm/mach-common/bits/otp.h> --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -11,7 +11,7 @@ #include<config.h> #include<malloc.h> #include<asm/blackfin.h> -#include<asm/gpio.h> +#include<asm/mach-bf548/gpio.h> #include<asm/portmux.h> #include<asm/mach-common/bits/dma.h> #include<i2c.h> --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -38,7 +38,7 @@ #include<asm/arch/mmc_host_def.h> #include<asm/arch/mux.h> #include<asm/arch/sys_proto.h> -#include<asm/arch/gpio.h> +#include<asm/arch-omap3/gpio.h> #include<asm/mach-types.h> #ifdef CONFIG_USB_EHCI #include<usb.h> --- a/board/ti/beagle/led.c +++ b/board/ti/beagle/led.c @@ -22,7 +22,7 @@ #include<asm/arch/cpu.h> #include<asm/io.h> #include<asm/arch/sys_proto.h> -#include<asm/arch/gpio.h> +#include<asm/arch-omap3/gpio.h> static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};

4 3

Re: [U-Boot] [PATCH v2 2/3] Armada100: Enable Ethernet support for GplugD
by Ajay Bhargav 25 Aug '11

25 Aug '11

----- "Marek Vasut" <marek.vasut(a)gmail.com> wrote: > On Thursday, August 25, 2011 07:15:17 AM Ajay Bhargav wrote: > > ----- "Marek Vasut" <marek.vasut(a)gmail.com> wrote: > > [...] > > > > > > +/* Disable DCACHE */ > > > > +#define CONFIG_SYS_DCACHE_OFF > > > > > > ARMADA100 is still ARMv5? Then maybe you can try Hong Xu's patches > for > > > dcache on > > > armv5. You'll have to modify the ethernet driver to be aware of > the > > > dcache then > > > though. > > > > > > As dcache support is on the way, it might be worth it. > > > > Yes ARMADA100 is ARMv5. I had problems with dcache enabled, driver > get > > stuck. Can you please link me to Hong Xu's patches? Is there a > problem if > > i keep it disabled? > > http://lists.denx.de/pipermail/u-boot/2011-August/098405.html Look > around this. > You'd better search for V2 of the patches or V3 in U-Boot ML archive. > > There's no problem if you keep it disabled, but eventually, you'll > have to > enable it ;-) > > Cheers Hi Marek, I searched mail list after I emailed you.. There has been a lot of discussion going on Hong Xu's patches. I think it would be better if I work on enabling dcache once the patch is mainlined. Thanks, Ajay Bhargav

2 1

Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
by Ajay Bhargav 25 Aug '11

25 Aug '11

----- "Marek Vasut" <marek.vasut(a)gmail.com> wrote: > On Wednesday, August 24, 2011 03:07:18 PM Ajay Bhargav wrote: > > This patch adds support for Fast Ethernet Controller driver for > > Armada100 series. > > > > Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> > > --- > > [...] > [...] > > + > > +static int armdfec_phy_timeout(u32 reg, u32 flag, int cond) > > +{ > > + u32 timeout = PHY_WAIT_ITERATIONS; > > + while (--timeout) { > > + if (cond && (readl(reg) & flag)) > > + break; > > + else if (!cond && !(readl(reg) & flag)) > > You can read the register into some temporary variable so you don't > need the > readl() at two places. > readl will be called only once... do i really need a temp var? > > + break; > > + udelay(PHY_WAIT_MICRO_SECONDS); > > + } > > + return !timeout; > > +} > > + > > +static int smi_reg_read(const char *devname, u8 phy_addr, u8 > phy_reg, > > + u16 *value) > > +{ > > + struct eth_device *dev = eth_get_dev_by_name(devname); > > + struct armdfec_device *darmdfec = to_darmdfec(dev); > > + struct armdfec_reg *regs = darmdfec->regs; > > + u32 val, reg_data; > > + > > + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { > > + reg_data = readl(&regs->phyadr); > > + *value = (u16) (reg_data & 0x1f); > > + return 0; > > + } > > + > > + /* check parameters */ > > + if (phy_addr > PHY_MASK) { > > + printf("Err..(%s) Invalid phy address: 0x%X\n", > > + __func__, phy_addr); > > + return -EINVAL; > > + } > > + if (phy_reg > PHY_MASK) { > > + printf("Err..(%s) Invalid register offset: 0x%X\n", > > + __func__, phy_reg); > > + return -EINVAL; > > + } > > + > > + /* wait for the SMI register to become available */ > > + if (armdfec_phy_timeout((u32)&regs->smi, SMI_BUSY, FALSE)) { > > Adjust the function so you don't need the cast. > okay... > > + printf("Error (%s) PHY busy timeout\n", __func__); > > + return -1; > > + } > > + > > + writel(phy_addr << 16 | phy_reg << 21 | SMI_OP_R, &regs->smi); > > Parentheses missing maybe ? > :) okay.. > > + > > + /* now wait for the data to be valid */ > > + if (armdfec_phy_timeout((u32)&regs->smi, SMI_R_VALID, TRUE)) { > > + val = readl(&regs->smi); > > + printf("Err (%s) PHY Read timeout, val=0x%x\n", __func__, val); > > + return -1; > > + } > > + val = readl(&regs->smi); > > + *value = val & 0xffff; > > + > > + return 0; > > +} > > + > > +static int smi_reg_write(const char *devname, > > + u8 phy_addr, u8 phy_reg, u16 value) > > +{ > > + struct eth_device *dev = eth_get_dev_by_name(devname); > > + struct armdfec_device *darmdfec = to_darmdfec(dev); > > + struct armdfec_reg *regs = darmdfec->regs; > > + > > + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { > > + clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f); > > + return 0; > > + } > > + > > + /* check parameters */ > > + if (phy_addr > PHY_MASK) { > > + printf("Err..(%s) Invalid phy address\n", __func__); > > + return -EINVAL; > > + } > > + if (phy_reg > PHY_MASK) { > > + printf("Err..(%s) Invalid register offset\n", __func__); > > + return -EINVAL; > > + } > > + > > + /* wait for the SMI register to become available */ > > + if (armdfec_phy_timeout((u32)&regs->smi, SMI_BUSY, FALSE)) { > > + printf("Error (%s) PHY busy timeout\n", __func__); > > + return -1; > > + } > > + > > + writel(phy_addr << 16 | phy_reg << 21 | SMI_OP_W | (value & > 0xffff), > > + &regs->smi); > > + return 0; > > +} > > + > > +/* > > + * Abort any transmit and receive operations and put DMA > > + * in idle state. AT and AR bits are cleared upon entering > > + * in IDLE state. So poll those bits to verify operation. > > + */ > > +static void abortdma(struct eth_device *dev) > > +{ > > + struct armdfec_device *darmdfec = to_darmdfec(dev); > > + struct armdfec_reg *regs = darmdfec->regs; > > + int delay; > > + int maxretries = 40; > > + > > + do { > > + writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd); > > + udelay(100); > > + > > + delay = 10; > > + while ((readl(&regs->sdma_cmd) & > > + (SDMA_CMD_AR | SDMA_CMD_AT)) > > + && delay-- > 0) { > > + udelay(10); > > + } > > + } while (maxretries-- > 0 && delay <= 0); > > Didn't I comment on this one in V1? > Yes you did... > > + > > + if (maxretries <= 0) > > + printf("%s : DMA Stuck\n", __func__); > > +} > > [...] > > > +int armada100_fec_register() > > +{ > > + struct armdfec_device *darmdfec; > > + struct eth_device *dev; > > + int phy_adr; > > + > > + darmdfec = malloc(sizeof(struct armdfec_device)); > > + if (!darmdfec) > > + goto error; > > + > > + memset(darmdfec, 0, sizeof(struct armdfec_device)); > > + > > + darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE); > > + if (!darmdfec->htpr) > > + goto error; > > + > > + darmdfec->p_rxdesc = (struct rx_desc *) memalign(PKTALIGN, > > + ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1); > > + > > + if (!darmdfec->p_rxdesc) > > + goto error; > > + > > + darmdfec->p_rxbuf = (u8 *) memalign(PKTALIGN, > > + RINGSZ * PKTSIZE_ALIGN + 1); > > Is the cast needed ? You should review your casts, most of them can be > solved by > using proper type! > Thats a serious issue with me I guess :) > > + if (!darmdfec->p_rxbuf) > > + goto error; > > + > > + darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); > > + if (!darmdfec->p_aligned_txbuf) > > + goto error; > > + > > + darmdfec->p_txdesc = (struct tx_desc *) > > + memalign(PKTALIGN, sizeof(struct tx_desc) + 1); > > + if (!darmdfec->p_txdesc) > > + goto error; > > + > > + dev = &darmdfec->dev; > > + /* Assign ARMADA100 Fast Ethernet Controller Base Address */ > > + darmdfec->regs = (void *) ARMD1_FEC_BASE; > > Cheers! > Thanks, Ajay Bhargav

2 1

Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
by Ajay Bhargav 25 Aug '11

25 Aug '11

----- "Marek Vasut" <marek.vasut(a)gmail.com> wrote: [...] > > +static void abortdma(struct eth_device *dev) > > +{ > > + struct armdfec_device *darmdfec = to_darmdfec(dev); > > + struct armdfec_reg *regs = darmdfec->regs; > > + int delay; > > + int maxretries = 40; > > + > > + do { > > + writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd); > > + udelay(100); > > + > > + delay = 10; > > + while ((readl(&regs->sdma_cmd) & > > + (SDMA_CMD_AR | SDMA_CMD_AT)) > > + && delay-- > 0) { > > + udelay(10); > > + } > > + } while (maxretries-- > 0 && delay <= 0); > > Didn't I comment on this one in V1? > I modified it as follows... Is it more readable now? :) while (maxretries--) { writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd); udelay(100); delay = 10; while ((readl(&regs->sdma_cmd) & (SDMA_CMD_AR | SDMA_CMD_AT)) && delay--) udelay(10); if(delay) break; } Regards, Ajay Bhargav

2 2

[U-Boot] [PATCH v2 2/3] Armada100: Enable Ethernet support for GplugD
by Ajay Bhargav 25 Aug '11

25 Aug '11

This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- Changes for v2: - armada100_fec_initialize changed to armada100_fec_register arch/arm/include/asm/arch-armada100/armada100.h | 57 +++++++++++++++++++++++ arch/arm/include/asm/arch-armada100/mfp.h | 19 ++++++++ board/Marvell/gplugd/gplugd.c | 39 +++++++++++++++ include/configs/gplugd.h | 19 +++++++- 4 files changed, 132 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index 3d567eb..849638d 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -41,6 +41,10 @@ /* Functional Clock Selection Mask */ #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) +/* Fast Ethernet Controller Clock register definition */ +#define FE_CLK_RST 0x1 +#define FE_CLK_ENA 0x8 + /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_TIMER_BASE 0xD4014000 @@ -85,6 +89,59 @@ struct armd1mpmu_registers { }; /* + * Application Subsystem Power Management + * Refer Datasheet Appendix A.9 + */ +struct armd1apmu_registers { + u32 pcr; /* 0x000 */ + u32 ccr; /* 0x004 */ + u32 pad1; + u32 ccsr; /* 0x00C */ + u32 fc_timer; /* 0x010 */ + u32 pad2; + u32 ideal_cfg; /* 0x018 */ + u8 pad3[0x04C - 0x018 - 4]; + u32 lcdcrc; /* 0x04C */ + u32 cciccrc; /* 0x050 */ + u32 sd1crc; /* 0x054 */ + u32 sd2crc; /* 0x058 */ + u32 usbcrc; /* 0x05C */ + u32 nfccrc; /* 0x060 */ + u32 dmacrc; /* 0x064 */ + u32 pad4; + u32 buscrc; /* 0x06C */ + u8 pad5[0x07C - 0x06C - 4]; + u32 wake_clr; /* 0x07C */ + u8 pad6[0x090 - 0x07C - 4]; + u32 core_status; /* 0x090 */ + u32 rfsc; /* 0x094 */ + u32 imr; /* 0x098 */ + u32 irwc; /* 0x09C */ + u32 isr; /* 0x0A0 */ + u8 pad7[0x0B0 - 0x0A0 - 4]; + u32 mhst; /* 0x0B0 */ + u32 msr; /* 0x0B4 */ + u8 pad8[0x0C0 - 0x0B4 - 4]; + u32 msst; /* 0x0C0 */ + u32 pllss; /* 0x0C4 */ + u32 smb; /* 0x0C8 */ + u32 gccrc; /* 0x0CC */ + u8 pad9[0x0D4 - 0x0CC - 4]; + u32 smccrc; /* 0x0D4 */ + u32 pad10; + u32 xdcrc; /* 0x0DC */ + u32 sd3crc; /* 0x0E0 */ + u32 sd4crc; /* 0x0E4 */ + u8 pad11[0x0F0 - 0x0E4 - 4]; + u32 cfcrc; /* 0x0F0 */ + u32 mspcrc; /* 0x0F4 */ + u32 cmucrc; /* 0x0F8 */ + u32 fecrc; /* 0x0FC */ + u32 pciecrc; /* 0x100 */ + u32 epdcrc; /* 0x104 */ +}; + +/* * APB1 Clock Reset/Control Registers * Refer Datasheet Appendix A.10 */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index d6e0494..da76b58 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -64,6 +64,25 @@ #define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) #define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +/* Fast Ethernet */ +#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) + /* More macros can be defined here... */ #define MFP_PIN_MAX 117 diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index dc7d89d..4cd4086 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -33,6 +33,11 @@ #include <asm/arch/mfp.h> #include <asm/arch/armada100.h> +#ifdef CONFIG_ARMADA100_FEC +#include <net.h> +#include <netdev.h> +#endif /* CONFIG_ARMADA100_FEC */ + DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) @@ -45,6 +50,26 @@ int board_early_init_f(void) /* Enable Console on UART3 */ MFPO8_UART3_TXD, MFPO9_UART3_RXD, + + /* Ethernet PHY Interface */ + MFP086_ETH_TXCLK, + MFP087_ETH_TXEN, + MFP088_ETH_TXDQ3, + MFP089_ETH_TXDQ2, + MFP090_ETH_TXDQ1, + MFP091_ETH_TXDQ0, + MFP092_ETH_CRS, + MFP093_ETH_COL, + MFP094_ETH_RXCLK, + MFP095_ETH_RXER, + MFP096_ETH_RXDQ3, + MFP097_ETH_RXDQ2, + MFP098_ETH_RXDQ1, + MFP099_ETH_RXDQ0, + MFP100_ETH_MDC, + MFP101_ETH_MDIO, + MFP103_ETH_RXDV, + MFP_EOC /*End of configuration*/ }; /* configure MFP's */ @@ -60,3 +85,17 @@ int board_init(void) gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; return 0; } + +#ifdef CONFIG_ARMADA100_FEC +int board_eth_init(bd_t *bis) +{ + struct armd1apmu_registers *apmu_regs = + (struct armd1apmu_registers *) ARMD1_APMU_BASE; + + /* Enable clock of ethernet controller */ + writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); + + return armada100_fec_register(); +} +#endif /* CONFIG_ARMADA100_FEC */ + diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index cc14f49..f3b94d8 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -62,8 +62,23 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS + +/* Disable DCACHE */ +#define CONFIG_SYS_DCACHE_OFF + +/* Network configuration */ +#define CONFIG_CMD_PING +#define CONFIG_NET_MULTI +#define CONFIG_ARMADA100_FEC + +/* DHCP Support */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 +#define CONFIG_BOOTP_SERVERIP + +/* Default Boot Parameters */ +#define CONFIG_ROOTPATH "/tftpboot" +#define CONFIG_SYS_IMG_NAME "uImage" /* * mv-common.h should be defined after CMD configs since it used them -- 1.7.0.4

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[U-Boot] [PATCH] xilinx_emaclite.c ping-pong macro names
by alain.peteut＠space.unibe.ch 25 Aug '11

25 Aug '11

Dear all, The macro name configuring Ping/Pong didn't match. It has been checked on a Spartan3e Starterkit. Kind regards, Alain

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