August 2011 - U-Boot

[U-Boot] mii_phy.h
by Michal Simek 26 Aug '11

26 Aug '11

Hi, Can someone clear me purpose of mii_phy.h? It looks like that it is really ancient file which hasn't been touched from 2003. It is use for two files [monstr@monstr u-boot]$ grep -rn "mii_phy.h" * board/ep8260/mii_phy.c:2:#include <mii_phy.h> board/rpxsuper/mii_phy.c:2:#include <mii_phy.h> + different numbers of arguments against new "version" [monstr@monstr u-boot]$ grep -rn "mii_discover_phy" * arch/m68k/include/asm/fec.h:359:int mii_discover_phy(struct eth_device *dev); arch/powerpc/cpu/mpc8xx/fec.c:63:static int mii_discover_phy(struct eth_device *dev); arch/powerpc/cpu/mpc8xx/fec.c:728: efis->actual_phy_addr = mii_discover_phy (dev); arch/powerpc/cpu/mpc8xx/fec.c:872:static int mii_discover_phy(struct eth_device *dev) arch/powerpc/cpu/mpc85xx/ether_fcc.c:237: mii_discover_phy(); arch/powerpc/cpu/mpc8260/ether_fcc.c:234: mii_discover_phy(); board/ep8260/mii_phy.c:10:mii_discover_phy(void) board/rpxsuper/mii_phy.c:10:mii_discover_phy(void) drivers/net/mcfmii.c:150:int mii_discover_phy(struct eth_device *dev) drivers/net/mcfmii.c:253: info->phy_addr = mii_discover_phy(dev); include/mii_phy.h:4:void mii_discover_phy(void); + that functions without arg are not called either arch/powerpc/cpu/mpc85xx/ether_fcc.c:237: mii_discover_phy(); arch/powerpc/cpu/mpc8260/ether_fcc.c:234: mii_discover_phy(); I found that Frank Panno is ep8260 maintainer. Any comment? The best will be to remove mii_phy entirely. Wolfgang: What do you think? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian

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[U-Boot] [PATCH v3 3/3] Armada100: Enable 88E3015 PHY support for GplugD
by Ajay Bhargav 26 Aug '11

26 Aug '11

This patch adds support for 88E3015 PHY for Marvell GplugD board. This patch depends on series of patch which adds support for Marvell GuruPlug-Display. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- Changes for v2: - Not changed Changes for v3: - code cleanup; removed unwated cast board/Marvell/gplugd/gplugd.c | 33 ++++++++++++++++++++++++++++++++- include/configs/gplugd.h | 14 ++++++++++++++ 2 files changed, 46 insertions(+), 1 deletions(-) diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index db4d776..a7cabcd 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -32,6 +32,8 @@ #include <mvmfp.h> #include <asm/arch/mfp.h> #include <asm/arch/armada100.h> +#include <asm/gpio.h> +#include <miiphy.h> #ifdef CONFIG_ARMADA100_FEC #include <net.h> @@ -83,6 +85,11 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD; /* adress of boot parameters */ gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; + /* Assert PHY_RST# */ + gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW); + udelay(10); + /* Deassert PHY_RST# */ + gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH); return 0; } @@ -97,5 +104,29 @@ int board_eth_init(bd_t *bis) return armada100_fec_register(ARMD1_FEC_BASE); } -#endif /* CONFIG_ARMADA100_FEC */ +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY chip 88E3015 */ +void reset_phy(void) +{ + u16 phy_adr; + const char *name = "armd-fec0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xff, 0xff, (u16 *) &phy_adr)) { + printf("Err..%s could not read PHY dev address\n", __func__); + return; + } + /* Set Ethernet LED in TX blink mode */ + miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00); + miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL); + + /* reset the phy */ + miiphy_reset(name, phy_adr); + debug("88E3015 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ +#endif /* CONFIG_ARMADA100_FEC */ diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index f3b94d8..b63ffd5 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -80,6 +80,20 @@ #define CONFIG_ROOTPATH "/tftpboot" #define CONFIG_SYS_IMG_NAME "uImage" +/* GPIO Support */ +#define CONFIG_MARVELL_GPIO + +/* PHY configuration */ +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_RESET_PHY_R +/* 88E3015 register definition */ +#define PHY_LED_PAR_SEL_REG 22 +#define PHY_LED_MAN_REG 25 +#define PHY_LED_VAL 0x5b /* LINK LED1, ACT LED2 */ +/* GPIO Configuration for PHY */ +#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 1.7.0.4

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[U-Boot] [PATCH v3 2/3] Armada100: Enable Ethernet support for GplugD
by Ajay Bhargav 26 Aug '11

26 Aug '11

This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- Changes for v2: - armada100_fec_initialize changed to armada100_fec_register Changes for v3: - fec base address as argument to armada100_fec_register arch/arm/include/asm/arch-armada100/armada100.h | 57 +++++++++++++++++++++++ arch/arm/include/asm/arch-armada100/mfp.h | 19 ++++++++ board/Marvell/gplugd/gplugd.c | 39 +++++++++++++++ include/configs/gplugd.h | 19 +++++++- 4 files changed, 132 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index 3d567eb..849638d 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -41,6 +41,10 @@ /* Functional Clock Selection Mask */ #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) +/* Fast Ethernet Controller Clock register definition */ +#define FE_CLK_RST 0x1 +#define FE_CLK_ENA 0x8 + /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_TIMER_BASE 0xD4014000 @@ -85,6 +89,59 @@ struct armd1mpmu_registers { }; /* + * Application Subsystem Power Management + * Refer Datasheet Appendix A.9 + */ +struct armd1apmu_registers { + u32 pcr; /* 0x000 */ + u32 ccr; /* 0x004 */ + u32 pad1; + u32 ccsr; /* 0x00C */ + u32 fc_timer; /* 0x010 */ + u32 pad2; + u32 ideal_cfg; /* 0x018 */ + u8 pad3[0x04C - 0x018 - 4]; + u32 lcdcrc; /* 0x04C */ + u32 cciccrc; /* 0x050 */ + u32 sd1crc; /* 0x054 */ + u32 sd2crc; /* 0x058 */ + u32 usbcrc; /* 0x05C */ + u32 nfccrc; /* 0x060 */ + u32 dmacrc; /* 0x064 */ + u32 pad4; + u32 buscrc; /* 0x06C */ + u8 pad5[0x07C - 0x06C - 4]; + u32 wake_clr; /* 0x07C */ + u8 pad6[0x090 - 0x07C - 4]; + u32 core_status; /* 0x090 */ + u32 rfsc; /* 0x094 */ + u32 imr; /* 0x098 */ + u32 irwc; /* 0x09C */ + u32 isr; /* 0x0A0 */ + u8 pad7[0x0B0 - 0x0A0 - 4]; + u32 mhst; /* 0x0B0 */ + u32 msr; /* 0x0B4 */ + u8 pad8[0x0C0 - 0x0B4 - 4]; + u32 msst; /* 0x0C0 */ + u32 pllss; /* 0x0C4 */ + u32 smb; /* 0x0C8 */ + u32 gccrc; /* 0x0CC */ + u8 pad9[0x0D4 - 0x0CC - 4]; + u32 smccrc; /* 0x0D4 */ + u32 pad10; + u32 xdcrc; /* 0x0DC */ + u32 sd3crc; /* 0x0E0 */ + u32 sd4crc; /* 0x0E4 */ + u8 pad11[0x0F0 - 0x0E4 - 4]; + u32 cfcrc; /* 0x0F0 */ + u32 mspcrc; /* 0x0F4 */ + u32 cmucrc; /* 0x0F8 */ + u32 fecrc; /* 0x0FC */ + u32 pciecrc; /* 0x100 */ + u32 epdcrc; /* 0x104 */ +}; + +/* * APB1 Clock Reset/Control Registers * Refer Datasheet Appendix A.10 */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index d6e0494..da76b58 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -64,6 +64,25 @@ #define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) #define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +/* Fast Ethernet */ +#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) + /* More macros can be defined here... */ #define MFP_PIN_MAX 117 diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index dc7d89d..db4d776 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -33,6 +33,11 @@ #include <asm/arch/mfp.h> #include <asm/arch/armada100.h> +#ifdef CONFIG_ARMADA100_FEC +#include <net.h> +#include <netdev.h> +#endif /* CONFIG_ARMADA100_FEC */ + DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) @@ -45,6 +50,26 @@ int board_early_init_f(void) /* Enable Console on UART3 */ MFPO8_UART3_TXD, MFPO9_UART3_RXD, + + /* Ethernet PHY Interface */ + MFP086_ETH_TXCLK, + MFP087_ETH_TXEN, + MFP088_ETH_TXDQ3, + MFP089_ETH_TXDQ2, + MFP090_ETH_TXDQ1, + MFP091_ETH_TXDQ0, + MFP092_ETH_CRS, + MFP093_ETH_COL, + MFP094_ETH_RXCLK, + MFP095_ETH_RXER, + MFP096_ETH_RXDQ3, + MFP097_ETH_RXDQ2, + MFP098_ETH_RXDQ1, + MFP099_ETH_RXDQ0, + MFP100_ETH_MDC, + MFP101_ETH_MDIO, + MFP103_ETH_RXDV, + MFP_EOC /*End of configuration*/ }; /* configure MFP's */ @@ -60,3 +85,17 @@ int board_init(void) gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; return 0; } + +#ifdef CONFIG_ARMADA100_FEC +int board_eth_init(bd_t *bis) +{ + struct armd1apmu_registers *apmu_regs = + (struct armd1apmu_registers *) ARMD1_APMU_BASE; + + /* Enable clock of ethernet controller */ + writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); + + return armada100_fec_register(ARMD1_FEC_BASE); +} +#endif /* CONFIG_ARMADA100_FEC */ + diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index cc14f49..f3b94d8 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -62,8 +62,23 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS + +/* Disable DCACHE */ +#define CONFIG_SYS_DCACHE_OFF + +/* Network configuration */ +#define CONFIG_CMD_PING +#define CONFIG_NET_MULTI +#define CONFIG_ARMADA100_FEC + +/* DHCP Support */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 +#define CONFIG_BOOTP_SERVERIP + +/* Default Boot Parameters */ +#define CONFIG_ROOTPATH "/tftpboot" +#define CONFIG_SYS_IMG_NAME "uImage" /* * mv-common.h should be defined after CMD configs since it used them -- 1.7.0.4

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Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
by Ajay Bhargav 26 Aug '11

26 Aug '11

----- "Mike Frysinger" <vapier(a)gentoo.org> wrote: > On Thursday, August 25, 2011 01:10:30 Ajay Bhargav wrote: > > ----- "Mike Frysinger" <vapier(a)gentoo.org> wrote: > > > On Wednesday, August 24, 2011 09:07:18 Ajay Bhargav wrote: > > > > + /* Read mac from env if available */ > > > > + eth_getenv_enetaddr("ethaddr", dev->enetaddr); > > > > > > you shouldnt need to do this. the higher layers will take care > of > > > this for > > > you when you set write_hwaddr > > > > I do not have a hardware storage for MAC on my controller. > write_hwaddr > > is not needed for me. > > ok, but you should not be touching dev->enetaddr in your registration > > function. the main net/eth.c:eth_initialize() takes care of this for > you. > > > > > +int armada100_fec_initialize() > > > > +{ > > > > ... > > > > + darmdfec->regs = (void *) ARMD1_FEC_BASE; > > > > > > make the reg base a parameter to armada100_fec_initialize() > > > > This driver is for Armada100 series and base address is same for > > the whole series, so i did not feel passing it as a parameter. Can > > you please tell me if there is any specific reason for the same? > > drivers should be written for the IP they control, not for specific > SoCs or > boards. and what people often start off with "this SoC only has one > MAC so > screw multi-instance" quite frequently turns into "this next SoC > supports > multiple MACs!". > > i'm not familiar with the Armada100, or the MAC IP that is in that > SoC, but > this story repeats itself constantly in the SoC world because people > focus on > the one specific SoC they have in their hand and not the bigger > picture. > simply witness the ARM hell that Linux is currently in and is being > cleaned up > through the Linaro organization. > -mike Hi Mike, I got your point.. Thanks for clearing this. I will make sure that this kind of problem does not happen in my case :) Regards, Ajay

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[U-Boot] (no subject)
by Ronny D 26 Aug '11

26 Aug '11

<a href="http://www.locksplususa.com/images/vfst.htm">http://www.locksplususa.com/images/vfst.htm</a>

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[U-Boot] standalone application export eth_receive: undefined index
by Robin Theunis 26 Aug '11

26 Aug '11

Hi all I have a little problem. I need to access the eth_receive function in my standalone application. The U-boot version is 1.3.3 (I know it is old but it is a requirement). Also I have seen that I need to enable #define CONFIG_API but building with this option fails. Current platfom is a AT91RM9200, 16MB sdram, 16MB flash. If I comment out the switches in the net/eth.c net/net.c and include/net.h. It could work. I exported also eth_send. This function doesn't give me any problems when compiling the application. Is this a dummy problem? Or something else? Thanks Robin Theunis

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[U-Boot] fw_env bug for multi-sector environments on NOR flash
by Fei, Yiyang 26 Aug '11

26 Aug '11

Hi, I am storing u-boot environment variables on a NOR flash using two sectors. I encountered an error when writing changes using fw_setenv. /etc # cat fw_env.config # Configuration file for fw_(printenv/saveenv) utility. # Up to two entries are valid, in this case the redundand # environment sector is assumed present. # MTD device name Device offset Env. size Flash sector size Number of sectors /dev/mtd12 0x0000 0x20000 0x10000 2 /etc # fw_setenv test test End of range reached, aborting Error: can't write fw_env to flash The reason for the error is that although both sectors are written in one pass, the loop for the write is executed twice because the "processed" variable is incremented by the incorrect amount. The following change is needed to fix this issue for NOR multi-sector environments. diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index ed6b53f..e6b2cae 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -880,9 +880,8 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, ioctl (fd, MEMLOCK, &erase); - processed += blocklen; - block_seek = 0; - blockstart += blocklen; + processed += erasesize; + blockstart += erasesize; } if (write_total > count) Are there any objections to committing this change? Yiyang Fei

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[U-Boot] gcc-4.6 warnings
by Kumar Gala 25 Aug '11

25 Aug '11

We get a bunch of warnings like this with gcc-4.6.x: e1000.c:4334:3: warning: variable 'x' set but not used [-Wunused-but-set-variable] Are we get with adding -Wunused-but-set-variable so they don't show up? - k

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[U-Boot] [PATCH v2] ns16550: change to allow 32 bit access to registers
by Dave Aldridge 25 Aug '11

25 Aug '11

If CONFIG_SYS_NS16550_MEM32 is defined then 32 bit memory mapped access will be used to read/write the uart registers. This is especially useful for SoC devices that implement 16550 compatible uarts but that have peripheral access width constraints. Signed-off-by: Dave Aldridge <fovsoft(a)gmail.com> --- Changes for v2: - Add endian support drivers/serial/ns16550.c | 6 ++++++ include/ns16550.h | 2 ++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8eeb48f..e16685b 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -19,6 +19,12 @@ #ifdef CONFIG_SYS_NS16550_PORT_MAPPED #define serial_out(x,y) outb(x,(ulong)y) #define serial_in(y) inb((ulong)y) +#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0) +#define serial_out(x,y) writel(cpu_to_be32(x),y) +#define serial_in(y) cpu_to_be32(readl(y)) +#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0) +#define serial_out(x,y) writel(cpu_to_le32(x),y) +#define serial_in(y) cpu_to_le32(readl(y)) #else #define serial_out(x,y) writeb(x,y) #define serial_in(y) readb(y) diff --git a/include/ns16550.h b/include/ns16550.h index 9ea81e9..d4ffac9 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -23,6 +23,8 @@ #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) #error "Please define NS16550 registers size." +#elif defined(CONFIG_SYS_NS16550_MEM32) +#define UART_REG(x) unsigned int x; #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) #define UART_REG(x) \ unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ -- 1.7.3.4

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[U-Boot] Get a Legitimate Business offer
by Mr. Ma Guang Lu 25 Aug '11

25 Aug '11

Business Mail I am Mr. Ma Guang Lu; with a business deal worth $17.3Million, for us to transact from my bank. please reply for details.

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