August 2011 - U-Boot

[U-Boot] [PATCH 1/3] [v4] powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
by Timur Tabi 26 Aug '11

26 Aug '11

Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- v4: moved definition of CONFIG_SYS_CCSRBAR_DEFAULT to avoid merge conflicts v3: fixed default CCSR address for the P1012. README | 37 +++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 39 ++++++++++++++++++++++++++ include/configs/MPC8536DS.h | 17 ++--------- include/configs/MPC8540ADS.h | 11 +------ include/configs/MPC8541CDS.h | 10 +----- include/configs/MPC8544DS.h | 10 +----- include/configs/MPC8548CDS.h | 10 +----- include/configs/MPC8555CDS.h | 10 +----- include/configs/MPC8560ADS.h | 11 +------ include/configs/MPC8568MDS.h | 10 +----- include/configs/MPC8569MDS.h | 15 ++-------- include/configs/MPC8572DS.h | 17 ++--------- include/configs/P1022DS.h | 14 +-------- include/configs/P1023RDS.h | 9 ------ include/configs/P1_P2_RDB.h | 19 ++----------- include/configs/P2020DS.h | 14 +-------- include/configs/P2041RDB.h | 14 --------- include/configs/SBC8540.h | 14 --------- include/configs/TQM85xx.h | 16 +++------- include/configs/corenet_ds.h | 13 --------- include/configs/mpq101.h | 16 +--------- include/configs/sbc8548.h | 10 +----- include/configs/sbc8560.h | 14 --------- include/configs/socrates.h | 10 +----- include/configs/stxgp3.h | 7 +--- include/configs/stxssa.h | 8 ++--- include/configs/xpedite520x.h | 10 +----- include/configs/xpedite537x.h | 10 +----- include/configs/xpedite550x.h | 10 +----- include/mpc85xx.h | 42 +++++++++++++++++++++++++++++ 30 files changed, 170 insertions(+), 277 deletions(-) diff --git a/README b/README index bbe5789..d7b5e32 100644 --- a/README +++ b/README @@ -2829,6 +2829,43 @@ Low Level (hardware related) configuration options: and RPXsuper) to be able to adjust the position of the IMMR register after a reset. +- CONFIG_SYS_CCSRBAR_DEFAULT: + Default (power-on reset) physical address of CCSR on Freescale + PowerPC SOCs. + +- CONFIG_SYS_CCSRBAR: + Virtual address of CCSR. On a 32-bit build, this is typically + the same value as CONFIG_SYS_CCSRBAR_DEFAULT. + + CONFIG_SYS_DEFAULT_IMMR must also be set to this value, + for cross-platform code that uses that macro instead. + +- CONFIG_SYS_CCSRBAR_PHYS: + Physical address of CCSR. CCSR can be relocated to a new + physical address, if desired. In this case, this macro should + be set to that address. Otherwise, it should be set to the + same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR + is typically relocated on 36-bit builds. It is recommended + that this macro be defined via the _HIGH and _LOW macros: + + #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH + * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) + +- CONFIG_SYS_CCSRBAR_PHYS_HIGH: + Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically + either 0 (32-bit build) or 0xF (36-bit build). This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSRBAR_PHYS_LOW: + Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSR_DO_NOT_RELOCATE: + If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be + forced to a value that ensures that CCSR is not relocated. + - Floppy Disk Support: CONFIG_SYS_FDC_DRIVE_NUMBER diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 04ca989..34f01b9 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -23,6 +23,10 @@ /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ +#ifdef CONFIG_SYS_CCSRBAR_DEFAULT +#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." +#endif + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -34,34 +38,41 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8541) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8568) #define CONFIG_MAX_CPUS 1 @@ -70,6 +81,7 @@ #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 @@ -78,11 +90,13 @@ #define QE_MURAM_SIZE 0x20000UL #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 @@ -105,6 +119,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -115,6 +130,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -127,6 +143,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -149,6 +166,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -164,6 +182,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -177,6 +196,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -184,6 +204,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -193,6 +214,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -204,6 +226,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -219,6 +242,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -227,6 +251,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -237,6 +262,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -248,6 +274,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -255,6 +282,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -269,6 +297,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -285,6 +314,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -301,6 +331,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -313,6 +344,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -328,6 +360,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -354,6 +387,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -370,6 +404,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -378,4 +413,8 @@ #error Processor type not defined for this platform #endif +#ifndef CONFIG_SYS_CCSRBAR_DEFAULT +#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 783ed51..f3d325a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -127,22 +127,11 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index e1d933e..fc0edac 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -89,15 +89,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 5918e64..ae19036 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -62,14 +62,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b25fb55..6b03d27 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -74,14 +74,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c9a0f60..aca77ff 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -77,14 +77,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 4c580a3..93d4c3e 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -62,14 +62,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index f55ef9d..e03fea3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -86,15 +86,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f7df7f0..cf0ea47 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -71,14 +71,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index fa626bb..dd7278c 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -105,20 +105,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR - /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bb8fb66..6067e60 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -112,22 +112,11 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index a118975..a3cccf4 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -64,18 +64,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x7fffffff -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 95f3a2c..24042df 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -99,15 +99,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of addresses in the LBC */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xff600000 /* relocated CCSRBAR */ -/* physical addr of CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index df88b79..3ffdb1a 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -148,24 +148,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif - /* CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ - /* CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 90fe7c4..f6b788e 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -118,18 +118,8 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 638dbe7..03dbe55 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -138,20 +138,6 @@ #define CONFIG_SYS_L3_SIZE (1024 << 10) #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -/* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 72559c0..b5612d6 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -94,20 +94,6 @@ #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." #endif -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ /* DDR Setup */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index b336723..fe6b728 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -130,18 +130,12 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x10000000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */ -#else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xA0000000 +#else +#define CONFIG_SYS_CCSRBAR 0xE0000000 +#endif +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * DDR Setup diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index adf9906..eb89b30 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -144,19 +144,6 @@ #define CONFIG_SYS_L3_SIZE (1024 << 10) #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h index e76ca73..f0ed4d1 100644 --- a/include/configs/mpq101.h +++ b/include/configs/mpq101.h @@ -64,20 +64,8 @@ #define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_CCSRBAR 0xe0000000 - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull -#else -# define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 7bf9fc7..4ec323e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -103,14 +103,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 435b148..e0af0d2 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -92,20 +92,6 @@ #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." #endif -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ /* DDR Setup */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 5f2fb1e..af62aea 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -91,14 +91,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00C00000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xE0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index fc3881d..66738d5 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -109,12 +109,9 @@ #ifdef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xfdf00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 141da26..a421ba4 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -121,12 +121,10 @@ #ifdef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index b6b391f..42517c9 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -78,14 +78,8 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index a74766d..202f209 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -96,14 +96,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 17aab5a..f13e4db 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -93,14 +93,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 2495b99..11d8985 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,4 +26,46 @@ #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ +/* + * Define default values for some CCSR macros to make header files cleaner* + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ +CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + +#ifndef CONFIG_SYS_IMMR +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#endif + #endif /* __MPC85xx_H__ */ -- 1.7.3.4

2 3

[U-Boot] [PATCH 1/2] [v3] powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
by Timur Tabi 26 Aug '11

26 Aug '11

Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- v3: fixed default CCSR address for the P1012. README | 37 +++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 39 ++++++++++++++++++++++++++ include/configs/MPC8536DS.h | 17 ++--------- include/configs/MPC8540ADS.h | 11 +------ include/configs/MPC8541CDS.h | 10 +----- include/configs/MPC8544DS.h | 10 +----- include/configs/MPC8548CDS.h | 10 +----- include/configs/MPC8555CDS.h | 10 +----- include/configs/MPC8560ADS.h | 11 +------ include/configs/MPC8568MDS.h | 10 +----- include/configs/MPC8569MDS.h | 15 ++-------- include/configs/MPC8572DS.h | 17 ++--------- include/configs/P1022DS.h | 14 +-------- include/configs/P1023RDS.h | 9 ------ include/configs/P1_P2_RDB.h | 19 ++----------- include/configs/P2020DS.h | 14 +-------- include/configs/P2041RDB.h | 14 --------- include/configs/SBC8540.h | 14 --------- include/configs/TQM85xx.h | 16 +++------- include/configs/corenet_ds.h | 13 --------- include/configs/mpq101.h | 16 +--------- include/configs/sbc8548.h | 10 +----- include/configs/sbc8560.h | 14 --------- include/configs/socrates.h | 10 +----- include/configs/stxgp3.h | 7 +--- include/configs/stxssa.h | 8 ++--- include/configs/xpedite520x.h | 10 +----- include/configs/xpedite537x.h | 10 +----- include/configs/xpedite550x.h | 10 +----- include/mpc85xx.h | 42 +++++++++++++++++++++++++++++ 30 files changed, 170 insertions(+), 277 deletions(-) diff --git a/README b/README index bbe5789..d7b5e32 100644 --- a/README +++ b/README @@ -2829,6 +2829,43 @@ Low Level (hardware related) configuration options: and RPXsuper) to be able to adjust the position of the IMMR register after a reset. +- CONFIG_SYS_CCSRBAR_DEFAULT: + Default (power-on reset) physical address of CCSR on Freescale + PowerPC SOCs. + +- CONFIG_SYS_CCSRBAR: + Virtual address of CCSR. On a 32-bit build, this is typically + the same value as CONFIG_SYS_CCSRBAR_DEFAULT. + + CONFIG_SYS_DEFAULT_IMMR must also be set to this value, + for cross-platform code that uses that macro instead. + +- CONFIG_SYS_CCSRBAR_PHYS: + Physical address of CCSR. CCSR can be relocated to a new + physical address, if desired. In this case, this macro should + be set to that address. Otherwise, it should be set to the + same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR + is typically relocated on 36-bit builds. It is recommended + that this macro be defined via the _HIGH and _LOW macros: + + #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH + * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) + +- CONFIG_SYS_CCSRBAR_PHYS_HIGH: + Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically + either 0 (32-bit build) or 0xF (36-bit build). This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSRBAR_PHYS_LOW: + Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSR_DO_NOT_RELOCATE: + If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be + forced to a value that ensures that CCSR is not relocated. + - Floppy Disk Support: CONFIG_SYS_FDC_DRIVE_NUMBER diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 04ca989..d72aed2 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -23,6 +23,10 @@ /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ +#ifdef CONFIG_SYS_CCSRBAR_DEFAULT +#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." +#endif + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -34,34 +38,41 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8541) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8568) #define CONFIG_MAX_CPUS 1 @@ -70,6 +81,7 @@ #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 @@ -78,11 +90,13 @@ #define QE_MURAM_SIZE 0x20000UL #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 @@ -105,6 +119,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -115,6 +130,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -127,6 +143,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -149,6 +166,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -164,6 +182,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -177,6 +196,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -184,6 +204,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -193,6 +214,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -204,6 +226,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -219,6 +242,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -227,6 +251,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -237,6 +262,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -248,6 +274,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -255,6 +282,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -271,6 +299,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P2041) @@ -287,6 +316,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P3041) @@ -303,6 +333,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P4040) @@ -313,6 +344,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -328,6 +360,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -356,6 +389,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P5020) @@ -372,10 +406,15 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #else #error Processor type not defined for this platform #endif +#ifndef CONFIG_SYS_CCSRBAR_DEFAULT +#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 783ed51..f3d325a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -127,22 +127,11 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index e1d933e..fc0edac 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -89,15 +89,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 5918e64..ae19036 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -62,14 +62,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b25fb55..6b03d27 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -74,14 +74,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c9a0f60..aca77ff 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -77,14 +77,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 4c580a3..93d4c3e 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -62,14 +62,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index f55ef9d..e03fea3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -86,15 +86,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f7df7f0..cf0ea47 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -71,14 +71,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index fa626bb..dd7278c 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -105,20 +105,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR - /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bb8fb66..6067e60 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -112,22 +112,11 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index a118975..a3cccf4 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -64,18 +64,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x7fffffff -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 95f3a2c..24042df 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -99,15 +99,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of addresses in the LBC */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xff600000 /* relocated CCSRBAR */ -/* physical addr of CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index df88b79..3ffdb1a 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -148,24 +148,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif - /* CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ - /* CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 90fe7c4..f6b788e 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -118,18 +118,8 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 638dbe7..03dbe55 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -138,20 +138,6 @@ #define CONFIG_SYS_L3_SIZE (1024 << 10) #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -/* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 72559c0..b5612d6 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -94,20 +94,6 @@ #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." #endif -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ /* DDR Setup */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index b336723..fe6b728 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -130,18 +130,12 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x10000000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */ -#else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xA0000000 +#else +#define CONFIG_SYS_CCSRBAR 0xE0000000 +#endif +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * DDR Setup diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index adf9906..eb89b30 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -144,19 +144,6 @@ #define CONFIG_SYS_L3_SIZE (1024 << 10) #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h index e76ca73..f0ed4d1 100644 --- a/include/configs/mpq101.h +++ b/include/configs/mpq101.h @@ -64,20 +64,8 @@ #define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_CCSRBAR 0xe0000000 - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull -#else -# define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 7bf9fc7..4ec323e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -103,14 +103,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 435b148..e0af0d2 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -92,20 +92,6 @@ #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." #endif -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ /* DDR Setup */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 5f2fb1e..af62aea 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -91,14 +91,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00C00000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xE0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index fc3881d..66738d5 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -109,12 +109,9 @@ #ifdef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xfdf00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 141da26..a421ba4 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -121,12 +121,10 @@ #ifdef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index b6b391f..42517c9 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -78,14 +78,8 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index a74766d..202f209 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -96,14 +96,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 17aab5a..f13e4db 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -93,14 +93,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 2495b99..11d8985 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,4 +26,46 @@ #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ +/* + * Define default values for some CCSR macros to make header files cleaner* + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ +CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + +#ifndef CONFIG_SYS_IMMR +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#endif + #endif /* __MPC85xx_H__ */ -- 1.7.3.4

4 6

[U-Boot] git fetch failure
by Christopher Harvey 26 Aug '11

26 Aug '11

Today, I tried to run git fetch http://git.denx.de/u-boot.git but got the following error error: Unable to find dbf545f2d11cd3118c6c8b54122adfbe799ea1b8 under http://git.denx.de/u-boot.git Cannot obtain needed blob dbf545f2d11cd3118c6c8b54122adfbe799ea1b8 while processing commit fe0ddffac1ce63de71fe8e6398c4784937b52c84. error: Fetch failed. fe0ddffac1ce63de71fe8e6398c4784937b52c84 seems to be the HEAD of the repository. I'm not totally new to git, but this one has me stumped. Any ideas? thanks, Chris.

1 1

[U-Boot] [PATCH 1/2] powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
by Kumar Gala 26 Aug '11

26 Aug '11

From: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> CC: Remy Bohmer <linux(a)bohmer.net> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/config_mpc85xx.h | 2 + drivers/usb/host/ehci-fsl.c | 37 ++++++++++++++++++++++++++-- 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 04ca989..d9d04e7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -97,6 +97,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -141,6 +142,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY /* P1015 is single core version of P1024 */ #elif defined(CONFIG_P1015) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 6e0043a..66b7da5 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. * * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB * @@ -26,6 +26,7 @@ #include <usb.h> #include <asm/io.h> #include <usb/ehci-fsl.h> +#include <hwconfig.h> #include "ehci.h" #include "ehci-core.h" @@ -39,6 +40,11 @@ int ehci_hcd_init(void) { struct usb_ehci *ehci; + char usb_phy[5]; + const char *phy_type = NULL; + size_t len; + + usb_phy[0] = '\0'; ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); @@ -52,10 +58,35 @@ int ehci_hcd_init(void) out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ - if (!strcmp(getenv("usb_phy_type"), "utmi")) - out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + if (hwconfig_sub("usb1", "phy_type")) + phy_type = hwconfig_subarg("usb1", "phy_type", &len); else + phy_type = getenv("usb_phy_type"); + if (!phy_type) { +#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY + /* if none specified assume internal UTMI */ + strcpy(usb_phy, "utmi"); + phy_type = usb_phy; +#else + printf("WARNING: USB phy type not defined !!\n"); + return -1; +#endif + } + if (!strcmp(phy_type, "utmi")) { +#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) + setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); + setbits_be32(&ehci->control, UTMI_PHY_EN); + udelay(1000); /* delay required for PHY Clk to appear */ +#endif + out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + } else { +#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) + clrbits_be32(&ehci->control, UTMI_PHY_EN); + setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); + udelay(1000); /* delay required for PHY Clk to appear */ +#endif out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); + } /* Enable interface. */ setbits_be32(&ehci->control, USB_EN); -- 1.7.3.4

2 11

[U-Boot] [PATCH 1/3] powerpc/mpc8548cds: set pci1_hose.config_table after fsl_setup_hose
by Zhao Chenhui 26 Aug '11

26 Aug '11

The function fsl_setup_hose clears the variable pci1_hose. Set pci1_hose.config_table after it. Signed-off-by: Zhao Chenhui <chenhui.zhao(a)freescale.com> --- board/freescale/mpc8548cds/mpc8548cds.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index f5c799b..5ffae47 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt <smcnutt(a)artesyncp.com> * @@ -207,8 +207,7 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { {}, }; -static struct pci_controller pci1_hose = { - config_table: pci_mpc85xxcds_config_table}; +static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */ #ifdef CONFIG_PCI2 @@ -253,6 +252,7 @@ void pci_init_board(void) pci_arb ? "arbiter" : "external-arbiter", pci_info.regs); + pci1_hose.config_table = pci_mpc85xxcds_config_table; first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); -- 1.6.4.1

3 5

Re: [U-Boot] [PATCH] beagleboard: enable HUB power on all variants of the BeagleBoard
by Joel A Fernandes 26 Aug '11

26 Aug '11

On Wed, Aug 24, 2011 at 10:30 PM, Jason Kridner <jkridner(a)beagleboard.org> wrote: > On Wed, Aug 24, 2011 at 11:22 PM, Marek Vasut <marek.vasut(a)gmail.com> wrote: >> On Thursday, August 25, 2011 12:47:41 AM Joel A Fernandes wrote: >>> From: Christian Spielberger <c.spielberger(a)bct-electronic.com> >>> >>> Signed-off-by: Joel A Fernandes <joelagnel(a)ti.com> >>> Cc: "Eric Bأ�nard" <eric(a)eukrea.com> >>> Cc: "Christian Spielberger" <c.spielberger(a)bct-electronic.com> >>> --- >>> Pushing this patch myself as no one else did. >>> >>> Previous discussions: >>> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105663/ >>> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/101540/ >>> >>> board/ti/beagle/beagle.c | 10 +++++++++- >>> 1 files changed, 9 insertions(+), 1 deletions(-) >>> >>> diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c >>> index 13fe39b..9d65e9e 100644 >>> --- a/board/ti/beagle/beagle.c >>> +++ b/board/ti/beagle/beagle.c >>> @@ -332,7 +332,15 @@ int misc_init_r(void) >>> setenv(expansion_config.env_var, expansion_config.env_setting); >>> >>> twl4030_power_init(); >>> - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); >>> + switch (get_board_revision()) { >>> + case REVISION_XM_C: >>> + case REVISION_C4: >>> + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); >>> + break; >>> + default: >>> + twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); >>> + break; >>> + } > > Please excuse if this is a duplicate, but I'm configuring a new mail > tool and I don't think my other message got sent. > > It is XM_A and XM_B that are odd-balls, so the correct code should be > something like: > > + switch (get_board_revision()) { > + case REVISION_XM_A: > + case REVISION_XM_B: > + twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); /* LEDA > signal set low */ > + break; > + default: > + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | > TWL4030_LED_LEDEN_LEDBON); > + break; Hi Jason, I think it should be: + switch (get_board_revision()) { + case REVISION_XM_A: + case REVISION_XM_B: + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); /* LEDA signal set low */ + break; + default: + twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); + break; Here's the equivalent in the linux kernel board file (default is GPIOF_OUT_INIT_LOW) printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n"); omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; beagle_config.usb_pwr_level = GPIOF_OUT_INIT_HIGH; Let me know your comments. thanks, Joel

1 0

[U-Boot] [PATCH] NAND: Add nand read.raw and write.raw commands
by Marek Vasut 26 Aug '11

26 Aug '11

These commands should work around various "hardware" ECC and BCH methods. This is important for example in case where the user needs to write precisely what's in a buffer to a NAND page, with no interference of hardware ECC engine or such. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- common/cmd_nand.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index b767cd2..ca510ae 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -606,6 +606,20 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) ret = nand->read_oob(nand, off, &ops); else ret = nand->write_oob(nand, off, &ops); + } else if (!strcmp(s, ".raw")) { + /* Raw access */ + mtd_oob_ops_t ops = { + .datbuf = (u8 *)addr, + .oobbuf = ((u8 *)addr) + nand->writesize, + .len = nand->writesize, + .ooblen = nand->oobsize, + .mode = MTD_OOB_RAW + }; + + if (read) + ret = nand->read_oob(nand, off, &ops); + else + ret = nand->write_oob(nand, off, &ops); } else { printf("Unknown nand command suffix '%s'.\n", s); return 1; -- 1.7.5.4

3 4

[U-Boot] [PATCH 1/7] powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
by York Sun 26 Aug '11

26 Aug '11

Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 19 ++++++++++--------- arch/powerpc/include/asm/fsl_ddr_sdram.h | 4 ++++ 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 3824aad..eb8d8e3 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -146,7 +146,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, break; case 2: if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ - (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0)) + (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) go_config = 1; break; case 3: @@ -617,7 +617,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ unsigned int dll_rst_dis; /* DLL reset disable */ unsigned int dqs_cfg; /* DQS configuration */ - unsigned int odt_cfg; /* ODT configuration */ + unsigned int odt_cfg = 0; /* ODT configuration */ unsigned int num_pr; /* Number of posted refreshes */ unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ unsigned int ap_en; /* Address Parity Enable */ @@ -625,15 +625,16 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int rcw_en = 0; /* Register Control Word Enable */ unsigned int md_en = 0; /* Mirrored DIMM Enable */ unsigned int qd_en = 0; /* quad-rank DIMM Enable */ + int i; dll_rst_dis = 1; /* Make this configurable */ dqs_cfg = popts->DQS_config; - if (popts->cs_local_opts[0].odt_rd_cfg - || popts->cs_local_opts[0].odt_wr_cfg) { - /* FIXME */ - odt_cfg = 2; - } else { - odt_cfg = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->cs_local_opts[i].odt_rd_cfg + || popts->cs_local_opts[i].odt_wr_cfg) { + odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; + break; + } } num_pr = 1; /* Make this configurable */ @@ -1018,7 +1019,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR2) const unsigned int mclk_ps = get_memory_clk_period_ps(); #endif - + dqs_en = !popts->DQS_config; rtt = fsl_ddr_get_rtt(); al = additive_latency; diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index bc063ea..5b6e8d9 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -92,6 +92,10 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG2_D_INIT 0x00000010 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 +#define SDRAM_CFG2_ODT_NEVER 0 +#define SDRAM_CFG2_ODT_ONLY_WRITE 1 +#define SDRAM_CFG2_ODT_ONLY_READ 2 +#define SDRAM_CFG2_ODT_ALWAYS 3 #define TIMING_CFG_2_CPO_MASK 0x0F800000 -- 1.7.0.4

3 19

[U-Boot] bitte lesen und antworten Sie mir dringend <Miss Nicole>..Reply to me urgently < Miss Nicole >
by Nicole Nicole 26 Aug '11

26 Aug '11

Liebste, wie war dein Tag, ich hoffe, alles gut bei dir? Ich entschied mich für Sie, weil meine derzeitige Situation wenden, ich bin in einer privaten Hilfsorganisation Aufenthalt unter St Johns Church hier in Ouagadougou in Burkina-Faso und ich bete, dass Gott das Herz berühren, zu verstehen und gib mir deine helfende Hand Ich bin Miss, Nicole Moses Akumi, und ich bin ein Mädchen von 24 Jahre alt, ein Medizinstudent, mein Vater seligen Angedenkens nach Name verstorbenen Herrn Moses Akumi, die ein Manager mit CNPC Ölgesellschaft wurde an der Khartoum-Raffinerie in Sudan, wurde an der Seite mit meiner geliebten Mutter und unsere Familie Haus von den Rebellen während der letzten Krise in meinem Land verbrannt getötet Ich bin jetzt schreibe Ihnen aus Ouagadougou Burkina-Faso, wo ich durch Straße entkommen, und jetzt um Asyl in einem privaten Hilfsorganisation unter St Johns Church hier in Ouagadougou in Burkina-Faso, können Sie mehr von meiner Geschichte über folgende Seite im Netz zu finden BBC News http://news.bbc.co.uk/2/hi/africa/6469857.stm so bin ich jetzt auf der Suche nach einem ehrlichen und zuverlässigen Person, die Hilfe für mich in keinem der westlichen Welt zu verlagern nach einem besseren Leben und mein Studium fortsetzen wird, habe ich mich entschlossen, Sie, nachdem sie durch Ihr Profil Kontakt und ich glaube, Sie sind eine zuverlässige Person, die nicht im Stich lässt mich oder mein Vertrauen verraten Ich weiß, Sie fragen sich vielleicht, warum ich so bald erzählen Sie über all das, auch ohne zu sehen oder zu wissen Sie ganz genau, wirklich etwas in mir sagt mir, dass du ein guter Mensch sind und ich denke, ich bin nicht falsch kurz will ich gerne etwas mehr über mich dir offenbaren und sehen, wenn Sie dazu beitragen können, um Ihr Land zu verlagern, um so mit meinem Studium fortsetzen und ein neues Leben, und bitte dies ist ein wenig abzusondern und flehe ich Sie zu halten es sich selbst allein, bis alles richtig angeordnet und ausgeführt wird, dann werde ich kommen, um Sie in Ihrem Land beitreten Ich habe die Summe von 5,2 Millionen Dollar als Erbe von meinem verstorbenen Vater, die Ich mag, um in Ihrem Land mit Ihrer Hilfe zu investieren wird, ist der Grund, warum ich brauche deine Hilfe auf Anweisung meines verstorbenen Vaters an die Bank gab in den Fonds-Release mir im Alter von 24 durch einen Ausländer, der mir helfen kann, den Fonds klug investieren, und es hat mein Vater den Wunsch für mich, einen Ausländer zu heiraten, so wird die Bank nicht freigeben der Fonds für mich ohne die Hilfe eines Ausländers wie mein Vater wies die Bank Dieser Fonds ist in meinem verstorbenen Vater das Bankkonto mit einer der Banken hier in Burkina-Faso hinterlegt und ich werde Ihnen alle Details / Kontakt, weil ich das Geld auf Ihr Konto überwiesen werden, bevor ich zu Ihnen kommen kommen wollen in Ihrem Land, ich will dich mit 15% des gesamten Fonds zu kompensieren, und Sie können mir auch helfen, um meinen eigenen Teil in jedem guten Geschäft zu investieren, möchte ich mein Studium beenden, weil ich Arzt werden, so dass ich positiv beitragen können wollen die Menschheit, i Ihre dringende Antwort auf Ihre Fähigkeit, das für mich verarbeiten, so dass i wird Ihnen sagen, den nächsten Schritt brauchen, weil ich zu diesem Flüchtlingslager so schnell wie möglich verlassen wollen, ist das Leben hier, um mir eine Hölle gibt, keine Liebe, keine Zuneigung und keine Annehmlichkeiten, was noch wichtiger ist, ich meine Studien Liebe und hier nichts los ist und die Menschen hier sind nicht freundlich, ich bin wirklich Leid an diesem Ort, es ist zu schmerzhaft, aber ich hoffe, mit Ihrer Hilfe, um die Übertragung der Fonds in Ihrem Konto , werde ich ein besseres Leben zu leben so freundlich mir Ihre Bereitschaft, mir zu helfen und ich verspreche, immer nett sein und dir treu, ich will gerne mit 15% des gesamten Fonds für die Hilfe zu kompensieren, und Sie können mir auch helfen, den Fonds zu investieren, während Ich setze meine Studien, weil ich Arzt werden wollen, ist es mein Wunsch, einen positiven Beitrag für die Menschheit Ich schicke Ihnen mein Foto und ich hoffe, Ihnen und Ihrer Telefonnummer, damit wir per Telefon sprechen kann und ich werde auch gerne deine Stimme zu hören Vielen Dank und Gott segne Sie Mit freundlichen Grüßen, Nicole ............ dearest, how was your day, i hope everything is well with you? i decided to contact you because of my present situation, i am staying in a private charity organization under St Johns Church here in Ouagadougou Burkina-Faso and i pray that God will touch your heart to understand and give me your helping hand i am miss, Nicole Moses Akumi, and i am a girl of 24 years old, a medical student, my father of blessed memory by name late Mr. Moses Akumi who was the a manager with CNPC oil company at the Khartoum refinery in Sudan, was killed along side with my beloved mother and our family house burnt down by the rebels during the last crisis in my country i am now writing you from Ouagadougou Burkina-Faso where i escaped through road, and now seeking asylum in a private charity organization under St Johns Church here in Ouagadougou Burkina-Faso, you can find more of my story through the following site on the net bbc news http://news.bbc.co.uk/2/hi/africa/6469857.stm so i am now in search of an honest and reliable person who will help to relocate me in any of the western world for a better life and to continue my studies, i have chosen to contact you after going through your profile and i believe you are a reliable person who will not let me down or betray my trust i know you may wonder why i am so soon telling you about all this, even without seeing or knowing you fully well, really something in me tells me that you are a good person and i guess i am not wrong briefly i will like to disclose little more about myself to you and see if you can help to relocate to your country so as to continue with my studies and have a new life, and please this is a little secrete and i plead with you to keep it to yourself alone until everything is properly arranged and executed, then i will come over to join you in your country i have the sum of $5.2 Million as an inheritance from my late father which i will like to invest in your country with your help, the reason why i need your help is based on the instruction my late father gave to the bank to release the fund to me at the age of 24 through a foreigner who can help me to invest the fund wisely, and it has been my father's desire for me to marry a foreigner, so the bank will not release the fund to me without the help of a foreigner as my father instructed the bank this fund is deposited in my late father's bank account with one of the banks here in Burkina-Faso and i am going to give you all the details / contact because i want the money to be transferred to your account before i come over to join you in your country, I will compensate you with 15% of the total fund and you can also help me to invest my own part into any good business, I want to finish my studies because I want to be a doctor so that I can contribute positively to humanity, i need your urgent answer of your ability to handle this for me so that i will tell you the next step because i want to leave this refugee camp as soon as possible, life here is to me a hell, no love, no affection and no amenities, more importantly, i love my studies and here nothing is happening and people here are not friendly, i am really suffering in this place, it is too painful, but i hope with your help to transferring the fund in your account, i will have a better life to live so kindly let me know your readiness to help me and i promise to always be nice and faithful to you, I will glad to compensate you with 15% of the total fund for helping me, and you can also help me to invest the fund while I continue my studies because I want to be a doctor, it is my desire to contribute positively to humanity i will send you my photo and i hope to have yours and your phone number so that we can talk through phone and i will also like to hear your voice thank you and God bless you sincerely yours, Nicole

1 0

[U-Boot] Pull request: u-boot-sh
by Nobuhiro Iwamatsu 26 Aug '11

26 Aug '11

Dear Wolfgang Denk. Please pull from git://git.denx.de/u-boot-sh.git master. The following changes since commit fa82f871c8dbc9a15e8dc274b3f99dd5fa0da458: Convert ISO-8859 files to UTF-8 (2011-08-04 23:34:02 +0200) are available in the git repository at: git://git.denx.de/u-boot-sh.git master Nobuhiro Iwamatsu (2): sh: sh2a: Add sh2a optimize to config.mk usb: r8a66597: Fix argument mistake of inl Phil Edworthy (4): sh: Add Renesas rsk7264 board sh: Add support for SH2A freestanding build sh: Fix rsk7203 alignment problem sh: Clean up rsk7264 board settings Yoshihiro Shimoda (2): sh: sh7757lcr: Add KEEP order to start.o section sh: add calling mmc_initialize in board.c MAINTAINERS | 4 + arch/sh/cpu/sh2/config.mk | 5 + arch/sh/cpu/sh2/cpu.c | 7 + arch/sh/include/asm/cpu_sh2.h | 2 + arch/sh/include/asm/cpu_sh7264.h | 41 ++++++ arch/sh/lib/Makefile | 22 +++ arch/sh/lib/ashiftlt.S | 192 ++++++++++++++++++++++++++ arch/sh/lib/ashiftrt.S | 149 ++++++++++++++++++++ arch/sh/lib/ashldi3.c | 25 ++++ arch/sh/lib/board.c | 12 ++ arch/sh/lib/libgcc.h | 25 ++++ arch/sh/lib/lshiftrt.S | 192 ++++++++++++++++++++++++++ arch/sh/lib/lshrdi3.c | 25 ++++ arch/sh/lib/movmem.S | 238 +++++++++++++++++++++++++++++++++ board/renesas/rsk7203/lowlevel_init.S | 1 + board/renesas/rsk7264/Makefile | 32 +++++ board/renesas/rsk7264/lowlevel_init.S | 212 +++++++++++++++++++++++++++++ board/renesas/rsk7264/rsk7264.c | 72 ++++++++++ board/renesas/sh7757lcr/u-boot.lds | 2 +- boards.cfg | 1 + drivers/serial/serial_sh.h | 5 +- drivers/usb/host/r8a66597.h | 2 +- include/configs/rsk7264.h | 78 +++++++++++ 23 files changed, 1341 insertions(+), 3 deletions(-) create mode 100644 arch/sh/include/asm/cpu_sh7264.h create mode 100644 arch/sh/lib/ashiftlt.S create mode 100644 arch/sh/lib/ashiftrt.S create mode 100644 arch/sh/lib/ashldi3.c create mode 100644 arch/sh/lib/libgcc.h create mode 100644 arch/sh/lib/lshiftrt.S create mode 100644 arch/sh/lib/lshrdi3.c create mode 100644 arch/sh/lib/movmem.S create mode 100644 board/renesas/rsk7264/Makefile create mode 100644 board/renesas/rsk7264/lowlevel_init.S create mode 100644 board/renesas/rsk7264/rsk7264.c create mode 100644 include/configs/rsk7264.h -- Nobuhiro Iwamatsu iwamatsu at {nigauri.org / debian.org} GPG ID: 40AD1FA6

2 1