January 2011 - U-Boot

[U-Boot] Coding Style question
by Kumar Gala 18 Jan '11

18 Jan '11

In a header define register fields we have something like: > +#define CSOR_NAND_TRHZ_MASK 0x0000001C /* Time for Read Enable > + High to Output High > + Impedance */ Is this multiple line comment style ok - since we are dealing with line wrap ? - k

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[U-Boot] [PATCH 1/2] BLOCK: Add freescale IMX51 PATA driver
by Marek Vasut 18 Jan '11

18 Jan '11

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- drivers/block/Makefile | 1 + drivers/block/mxc_ata.c | 149 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+), 0 deletions(-) create mode 100644 drivers/block/mxc_ata.c diff --git a/drivers/block/Makefile b/drivers/block/Makefile index e27175b..aa7dc87 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o COBJS-$(CONFIG_LIBATA) += libata.o COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o +COBJS-$(CONFIG_MX51_PATA) += mxc_ata.o COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o diff --git a/drivers/block/mxc_ata.c b/drivers/block/mxc_ata.c new file mode 100644 index 0000000..62c5cf4 --- /dev/null +++ b/drivers/block/mxc_ata.c @@ -0,0 +1,149 @@ +/* + * Freescale iMX51 ATA driver + * + * Copyright (C) 2010 Marek Vasut <marek.vasut(a)gmail.com> + * + * Based on code by: + * Mahesh Mahadevan <mahesh.mahadevan(a)freescale.com> + * + * Based on code from original FSL ATA driver, which is + * part of eCos, the Embedded Configurable Operating System. + * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <config.h> +#include <asm/byteorder.h> +#include <asm/io.h> +#include <ide.h> + +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +/* MXC ATA register offsets */ +struct mxc_ata_config_regs { + u8 time_off; /* 0x00 */ + u8 time_on; + u8 time_1; + u8 time_2w; + u8 time_2r; + u8 time_ax; + u8 time_pio_rdx; + u8 time_4; + u8 time_9; + u8 time_m; + u8 time_jn; + u8 time_d; + u8 time_k; + u8 time_ack; + u8 time_env; + u8 time_udma_rdx; + u8 time_zah; /* 0x10 */ + u8 time_mlix; + u8 time_dvh; + u8 time_dzfs; + u8 time_dvs; + u8 time_cvh; + u8 time_ss; + u8 time_cyc; + u32 fifo_data_32; /* 0x18 */ + u32 fifo_data_16; + u32 fifo_fill; + u32 ata_control; + u32 interrupt_pending; + u32 interrupt_enable; + u32 interrupt_clear; + u32 fifo_alarm; +}; + +struct mxc_data_hdd_regs { + u32 drive_data; /* 0xa0 */ + u32 drive_features; + u32 drive_sector_count; + u32 drive_sector_num; + u32 drive_cyl_low; + u32 drive_cyl_high; + u32 drive_dev_head; + u32 command; + u32 status; + u32 alt_status; +}; + +/* PIO timing table */ +#define NR_PIO_SPECS 5 +uint16_t pio_t0[NR_PIO_SPECS] = { 600, 383, 240, 180, 120 }; +uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 }; +uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 }; +uint16_t pio_t2_16[NR_PIO_SPECS] = { 165, 125, 100, 80, 70 }; +uint16_t pio_t2i[NR_PIO_SPECS] = { 40, 0, 0, 0, 0 }; +uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 }; +uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 }; +uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 }; + +#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8) +static void set_ata_bus_timing(unsigned char mode) +{ + uint32_t val; + uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK); + + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; + + if (mode >= NR_PIO_SPECS) + return; + + /* Write TIME_OFF/ON/1/2W */ + val = (3 << REG2OFF(&ata_cfg_regs->time_off)) | + (3 << REG2OFF(&ata_cfg_regs->time_on)) | + (((pio_t1[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_1)) | + (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2w)); + writel(val, &ata_cfg_regs->time_off); + + /* Write TIME_2R/AX/RDX/4 */ + val = (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2r)) | + (((pio_tA[mode] + T) / T + 2) << REG2OFF(&ata_cfg_regs->time_ax)) | + (1 << REG2OFF(&ata_cfg_regs->time_pio_rdx)) | + (((pio_t4[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_4)); + writel(val, &ata_cfg_regs->time_2r); + + /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ + val = (((pio_t9[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_9)); + writel(val, &ata_cfg_regs->time_9); +} + +int ide_preinit(void) +{ + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; + + /* 46.3.3.4 @ FSL iMX51 manual */ + /* FIFO normal op., drive reset */ + writel(0x80, &ata_cfg_regs->ata_control); + /* FIFO normal op., drive not reset */ + writel(0xc0, &ata_cfg_regs->ata_control); + + /* Configure the PIO timing */ + set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE); + + /* 46.3.3.4 @ FSL iMX51 manual */ + /* Drive not reset, IORDY handshake */ + writel(0x41, &ata_cfg_regs->ata_control); + + return 0; +} -- 1.7.2.3

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[U-Boot] [PATCH] nios2: add gpio_is_valid
by Thomas Chou 18 Jan '11

18 Jan '11

Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/include/asm/gpio.h | 6 ++++++ board/altera/nios2-generic/custom_fpga.h | 1 + board/altera/nios2-generic/gpio.c | 6 ++++++ 3 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h index 36a7132..4b21c8f 100644 --- a/arch/nios2/include/asm/gpio.h +++ b/arch/nios2/include/asm/gpio.h @@ -52,6 +52,11 @@ static inline void gpio_set_value(unsigned gpio, int value) { writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2)); } + +static inline int gpio_is_valid(int number) +{ + return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH; +} #else extern int gpio_request(unsigned gpio, const char *label); extern int gpio_free(unsigned gpio); @@ -59,6 +64,7 @@ extern int gpio_direction_input(unsigned gpio); extern int gpio_direction_output(unsigned gpio, int value); extern int gpio_get_value(unsigned gpio); extern void gpio_set_value(unsigned gpio, int value); +extern int gpio_is_valid(int number); #endif /* CONFIG_SYS_GPIO_BASE */ #endif /* _ASM_NIOS2_GPIO_H_ */ diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index a11add5..f7f3853 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -50,6 +50,7 @@ /* led_pio.s1 is a altera_avalon_pio */ #define LED_PIO_BASE 0x82120870 +#define LED_PIO_WIDTH 8 /* high_res_timer.s1 is a altera_avalon_timer */ #define CONFIG_SYS_TIMER_BASE 0x82120820 diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c index 8c639ce..4a30564 100644 --- a/board/altera/nios2-generic/gpio.c +++ b/board/altera/nios2-generic/gpio.c @@ -10,6 +10,7 @@ #ifndef CONFIG_SYS_GPIO_BASE #define ALTERA_PIO_BASE LED_PIO_BASE +#define ALTERA_PIO_WIDTH LED_PIO_WIDTH #define ALTERA_PIO_DATA (ALTERA_PIO_BASE + 0) #define ALTERA_PIO_DIR (ALTERA_PIO_BASE + 4) static u32 pio_data_reg; @@ -62,4 +63,9 @@ void gpio_set_value(unsigned gpio, int value) pio_data_reg &= ~mask; writel(pio_data_reg, ALTERA_PIO_DATA); } + +int gpio_is_valid(int number) +{ + return ((unsigned)number) < ALTERA_PIO_WIDTH; +} #endif -- 1.7.3.4

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[U-Boot] [PATCH] nios2: use long for ssize_t
by Thomas Chou 18 Jan '11

18 Jan '11

This is consistent with nios2-linux. And resolved the warning, cmd_nvedit.c: In function `do_env_export': cmd_nvedit.c:660: warning: size_t format, ssize_t arg (arg 3) Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/include/asm/posix_types.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/nios2/include/asm/posix_types.h b/arch/nios2/include/asm/posix_types.h index c2deea6..6733640 100644 --- a/arch/nios2/include/asm/posix_types.h +++ b/arch/nios2/include/asm/posix_types.h @@ -17,7 +17,7 @@ typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; typedef unsigned long __kernel_size_t; -typedef int __kernel_ssize_t; +typedef long __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t; -- 1.7.3.4

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[U-Boot] [PATCH] altera_spi: add spi_set_speed
by Thomas Chou 18 Jan '11

18 Jan '11

Added this for mmc_spi driver. Though altera spi core does not support programmable speed. It is fixed when configured in sopc-builder. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/spi/altera_spi.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 918b223..138d6f4 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -70,6 +70,11 @@ void spi_init(void) { } +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + /* altera spi core does not support programmable speed */ +} + struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { -- 1.7.3.4

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[U-Boot] [PATCH] nios2: add gpio_free
by Thomas Chou 18 Jan '11

18 Jan '11

Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/include/asm/gpio.h | 6 ++++++ board/altera/nios2-generic/gpio.c | 5 +++++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h index cff1dd9..36a7132 100644 --- a/arch/nios2/include/asm/gpio.h +++ b/arch/nios2/include/asm/gpio.h @@ -26,6 +26,11 @@ static inline int gpio_request(unsigned gpio, const char *label) return 0; } +static inline int gpio_free(unsigned gpio) +{ + return 0; +} + static inline int gpio_direction_input(unsigned gpio) { writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2)); @@ -49,6 +54,7 @@ static inline void gpio_set_value(unsigned gpio, int value) } #else extern int gpio_request(unsigned gpio, const char *label); +extern int gpio_free(unsigned gpio); extern int gpio_direction_input(unsigned gpio); extern int gpio_direction_output(unsigned gpio, int value); extern int gpio_get_value(unsigned gpio); diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c index d449684..8c639ce 100644 --- a/board/altera/nios2-generic/gpio.c +++ b/board/altera/nios2-generic/gpio.c @@ -20,6 +20,11 @@ int gpio_request(unsigned gpio, const char *label) return 0; } +int gpio_free(unsigned gpio) +{ + return 0; +} + int gpio_direction_input(unsigned gpio) { u32 mask = 1 << gpio; -- 1.7.3.4

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[U-Boot] Boot Count Limit Feature Query
by Sean Preston 18 Jan '11

18 Jan '11

Hi I am working with a TI Davinci DM365 and would love to use the boot count limit feature for a product that we are working on but the docs state it is only supported by Power Architecture processors. Could someone please explain why this is and how it works as I will need to either find an alternate solution or investigate implementing something similar for this project and would appreciate any insights. Regards Sean -- Sean Preston Software Engineer Email: seanp(a)pfk.co.za

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[U-Boot] Please let me hear from you.
by Dr.Jaja Edward 18 Jan '11

18 Jan '11

Hi, I am the General Audit Manager, Accounts Department in our bank. I have the opportunity of transferring the sum of $6.500.000 (Six million Five Hundred Thousand Dollars) to one of our bank Customer who died in the year 23rd september of 2007. My request for foreigner to stand as next of kin in this business is because the fact that the customer is a foreigner. Based on the fact that this is a deal, I propose that 50% of this fund for you and 50% for me. I will give more detail of the transfer process as soon as you show your interest in this transaction. Thanks, Dr.Jaja Edward

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[U-Boot] INQUIRY
by BARR ZAID IBRAHIM 18 Jan '11

18 Jan '11

I am Barrister Zaid Ibrahim, an attorney at law. A deceased client of mine, that shares the same last name as yours died as the result of a heart-related condition on March 12th 2005. His heart condition was due to the death of all the members of his family in the tsunami disaster on the 26th December 2004 in Sumatra Indonesia. And in the record there is no known successor to this deposit of the deceased who died without a will. My late Client has a deposit of Eighteen Million Dollars left behind. Contact me via my private email account for more information:barrzaidibrahim_1949@yahoo.com.cn Best regards, Zaid Ibrahim Attorney at Law

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[U-Boot] [PATCH v2] spi: add support SuperH SPI module
by Yoshihiro Shimoda 18 Jan '11

18 Jan '11

SH7757 has SPI module. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- about v2: - add prefix of "SH_" to some defines. - modify spi_cs_is_valid() drivers/spi/Makefile | 1 + drivers/spi/sh_spi.c | 301 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 302 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/sh_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e34a124..d582fbb 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o +COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c new file mode 100644 index 0000000..633450c --- /dev/null +++ b/drivers/spi/sh_spi.c @@ -0,0 +1,301 @@ +/* + * SH SPI driver + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> + +#define SH_SPI_TBR 0x00 +#define SH_SPI_RBR 0x00 +#define SH_SPI_CR1 0x08 +#define SH_SPI_CR2 0x10 +#define SH_SPI_CR3 0x18 +#define SH_SPI_CR4 0x20 + +/* CR1 */ +#define SH_SPI_TBE 0x80 +#define SH_SPI_TBF 0x40 +#define SH_SPI_RBE 0x20 +#define SH_SPI_RBF 0x10 +#define SH_SPI_PFONRD 0x08 +#define SH_SPI_SSDB 0x04 +#define SH_SPI_SSD 0x02 +#define SH_SPI_SSA 0x01 + +/* CR2 */ +#define SH_SPI_RSTF 0x80 +#define SH_SPI_LOOPBK 0x40 +#define SH_SPI_CPOL 0x20 +#define SH_SPI_CPHA 0x10 +#define SH_SPI_L1M0 0x08 + +/* CR3 */ +#define SH_SPI_MAX_BYTE 0xFF + +/* CR4 */ +#define SH_SPI_TBEI 0x80 +#define SH_SPI_TBFI 0x40 +#define SH_SPI_RBEI 0x20 +#define SH_SPI_RBFI 0x10 +#define SH_SPI_WPABRT 0x04 +#define SH_SPI_SSS 0x01 + +#define SH_SPI_FIFO_SIZE 32 + +static void sh_spi_write(unsigned long data, unsigned long offset) +{ + writel(data, CONFIG_SH_SPI_BASE + offset); +} + +static unsigned long sh_spi_read(unsigned long offset) +{ + return readl(CONFIG_SH_SPI_BASE + offset); +} + +static void sh_spi_set_bit(unsigned long val, unsigned long offset) +{ + unsigned long tmp; + + tmp = sh_spi_read(offset); + tmp |= val; + sh_spi_write(tmp, offset); +} + +static void sh_spi_clear_bit(unsigned long val, unsigned long offset) +{ + unsigned long tmp; + + tmp = sh_spi_read(offset); + tmp &= ~val; + sh_spi_write(tmp, offset); +} + +static void clear_fifo(void) +{ + sh_spi_set_bit(SH_SPI_RSTF, SH_SPI_CR2); + sh_spi_clear_bit(SH_SPI_RSTF, SH_SPI_CR2); +} + +static int recvbuf_wait(void) +{ + while (sh_spi_read(SH_SPI_CR1) & SH_SPI_RBE) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +static int write_fifo_full_wait(void) +{ + while (sh_spi_read(SH_SPI_CR1) & SH_SPI_TBF) { + udelay(10); + if (ctrlc()) + return 1; + } + return 0; +} + +static int write_fifo_empty_wait(void) +{ + while (!(sh_spi_read(SH_SPI_CR1) & SH_SPI_TBE)) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +void spi_init(void) +{ + +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* SPI sycle stop */ + sh_spi_write(0xfe, SH_SPI_CR1); + /* CR1 init */ + sh_spi_write(0x00, SH_SPI_CR1); + /* CR3 init */ + sh_spi_write(0x00, SH_SPI_CR3); + + clear_fifo(); + + /* 1/8 clock */ + sh_spi_write(sh_spi_read(SH_SPI_CR2) | 0x07, SH_SPI_CR2); + udelay(10); + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + sh_spi_write(sh_spi_read(SH_SPI_CR1) & + ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), SH_SPI_CR1); +} + +static int sh_spi_send(const unsigned char *tx_data, unsigned int len, + unsigned long flags) +{ + int i, cur_len, ret = 0; + int remain = (int)len; + unsigned long tmp; + + if (len >= SH_SPI_FIFO_SIZE) + sh_spi_set_bit(SH_SPI_SSA, SH_SPI_CR1); + + while (remain > 0) { + cur_len = (remain < SH_SPI_FIFO_SIZE) ? + remain : SH_SPI_FIFO_SIZE; + for (i = 0; i < cur_len && + !(sh_spi_read(SH_SPI_CR4) & SH_SPI_WPABRT) && + !(sh_spi_read(SH_SPI_CR1) & SH_SPI_TBF); + i++) + sh_spi_write(tx_data[i], SH_SPI_TBR); + + cur_len = i; + + if (sh_spi_read(SH_SPI_CR4) & SH_SPI_WPABRT) { + /* Abort the transaction */ + flags |= SPI_XFER_END; + sh_spi_set_bit(SH_SPI_WPABRT, SH_SPI_CR4); + ret = 1; + break; + } + + remain -= cur_len; + tx_data += cur_len; + + if (remain > 0) + write_fifo_empty_wait(); + } + + if (flags & SPI_XFER_END) { + tmp = sh_spi_read(SH_SPI_CR1); + tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); + sh_spi_write(tmp, SH_SPI_CR1); + sh_spi_set_bit(SH_SPI_SSA, SH_SPI_CR1); + udelay(100); + write_fifo_empty_wait(); + } + + return ret; +} + +static int sh_spi_receive(unsigned char *rx_data, unsigned int len, + unsigned long flags) +{ + int i; + unsigned long tmp; + + if (len > SH_SPI_MAX_BYTE) + sh_spi_write(SH_SPI_MAX_BYTE, SH_SPI_CR3); + else + sh_spi_write(len, SH_SPI_CR3); + + tmp = sh_spi_read(SH_SPI_CR1); + tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); + sh_spi_write(tmp, SH_SPI_CR1); + sh_spi_set_bit(SH_SPI_SSA, SH_SPI_CR1); + + for (i = 0; i < len; i++) { + if (recvbuf_wait()) + return 0; + + rx_data[i] = (unsigned char)sh_spi_read(SH_SPI_RBR); + } + sh_spi_write(0, SH_SPI_CR3); + + return 0; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + const unsigned char *tx_data = dout; + unsigned char *rx_data = din; + unsigned int len = bitlen / 8; + int ret = 0; + + if (flags & SPI_XFER_BEGIN) + sh_spi_write(sh_spi_read(SH_SPI_CR1) & ~SH_SPI_SSA, SH_SPI_CR1); + + if (tx_data) + ret = sh_spi_send(tx_data, len, flags); + + if (ret == 0 && rx_data) + ret = sh_spi_receive(rx_data, len, flags); + + if (flags & SPI_XFER_END) { + sh_spi_set_bit(SH_SPI_SSD, SH_SPI_CR1); + udelay(100); + + sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD, + SH_SPI_CR1); + clear_fifo(); + } + + return ret; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* This driver supports "bus = 0" and "cs = 0" only. */ + if (!bus && !cs) + return 1; + else + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + +} + -- 1.7.1

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