January 2011 - U-Boot

[U-Boot] [PATCH] sh: Fix MigoR of boards.cfg
by Nobuhiro Iwamatsu 19 Jan '11

19 Jan '11

There is not break character between board name and CPU. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- boards.cfg | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/boards.cfg b/boards.cfg index 0574bb2..705847c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -755,7 +755,7 @@ r7780mp sh sh4 r7780mp renesas sh7763rdp sh sh4 sh7763rdp renesas - sh7785lcr sh sh4 sh7785lcr renesas - sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1 -MigoRsh sh4 MigoR renesas - +MigoR sh sh4 MigoR renesas - grsim_leon2 sparc leon2 - gaisler gr_cpci_ax2000 sparc leon3 - gaisler gr_ep2s60 sparc leon3 - gaisler -- 1.7.2.3

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[U-Boot] [PATCH] spi: add support SuperH SPI module
by Yoshihiro Shimoda 19 Jan '11

19 Jan '11

SH7757 has SPI module. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- drivers/spi/Makefile | 1 + drivers/spi/sh_spi.c | 295 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 296 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/sh_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e34a124..d582fbb 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o +COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c new file mode 100644 index 0000000..89ea5e2 --- /dev/null +++ b/drivers/spi/sh_spi.c @@ -0,0 +1,295 @@ +/* + * SH SPI driver + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> + +#define SPI_TBR 0x00 +#define SPI_RBR 0x00 +#define SPI_CR1 0x08 +#define SPI_CR2 0x10 +#define SPI_CR3 0x18 +#define SPI_CR4 0x20 + +/* CR1 */ +#define SPI_TBE 0x80 +#define SPI_TBF 0x40 +#define SPI_RBE 0x20 +#define SPI_RBF 0x10 +#define SPI_PFONRD 0x08 +#define SPI_SSDB 0x04 +#define SPI_SSD 0x02 +#define SPI_SSA 0x01 + +/* CR2 */ +#define SPI_RSTF 0x80 +#define SPI_LOOPBK 0x40 +#define SH_SPI_CPOL 0x20 +#define SH_SPI_CPHA 0x10 +#define SPI_L1M0 0x08 + +/* CR3 */ +#define SPI_MAX_BYTE 0xFF + +/* CR4 */ +#define SPI_TBEI 0x80 +#define SPI_TBFI 0x40 +#define SPI_RBEI 0x20 +#define SPI_RBFI 0x10 +#define SPI_WPABRT 0x04 +#define SPI_SSS 0x01 + +#define SPI_FIFO_SIZE 32 + +static void sh_spi_write(unsigned long data, unsigned long offset) +{ + writel(data, CONFIG_SH_SPI_BASE + offset); +} + +static unsigned long sh_spi_read(unsigned long offset) +{ + return readl(CONFIG_SH_SPI_BASE + offset); +} + +static void sh_spi_set_bit(unsigned long val, unsigned long offset) +{ + unsigned long tmp; + + tmp = sh_spi_read(offset); + tmp |= val; + sh_spi_write(tmp, offset); +} + +static void sh_spi_clear_bit(unsigned long val, unsigned long offset) +{ + unsigned long tmp; + + tmp = sh_spi_read(offset); + tmp &= ~val; + sh_spi_write(tmp, offset); +} + +static void clear_fifo(void) +{ + sh_spi_set_bit(SPI_RSTF, SPI_CR2); + sh_spi_clear_bit(SPI_RSTF, SPI_CR2); +} + +static int recvbuf_wait(void) +{ + while (sh_spi_read(SPI_CR1) & SPI_RBE) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +static int write_fifo_full_wait(void) +{ + while (sh_spi_read(SPI_CR1) & SPI_TBF) { + udelay(10); + if (ctrlc()) + return 1; + } + return 0; +} + +static int write_fifo_empty_wait(void) +{ + while (!(sh_spi_read(SPI_CR1) & SPI_TBE)) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +void spi_init(void) +{ + +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* SPI sycle stop */ + sh_spi_write(0xfe, SPI_CR1); + /* CR1 init */ + sh_spi_write(0x00, SPI_CR1); + /* CR3 init */ + sh_spi_write(0x00, SPI_CR3); + + clear_fifo(); + + /* 1/8 clock */ + sh_spi_write(sh_spi_read(SPI_CR2) | 0x07, SPI_CR2); + udelay(10); + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + sh_spi_write(sh_spi_read(SPI_CR1) & ~(SPI_SSA | SPI_SSDB | SPI_SSD), + SPI_CR1); +} + +static int sh_spi_send(const unsigned char *tx_data, unsigned int len, + unsigned long flags) +{ + int i, cur_len, ret = 0; + int remain = (int)len; + unsigned long tmp; + + if (len >= SPI_FIFO_SIZE) + sh_spi_set_bit(SPI_SSA, SPI_CR1); + + while (remain > 0) { + cur_len = (remain < SPI_FIFO_SIZE) ? remain : SPI_FIFO_SIZE; + for (i = 0; i < cur_len && + !(sh_spi_read(SPI_CR4) & SPI_WPABRT) && + !(sh_spi_read(SPI_CR1) & SPI_TBF); + i++) + sh_spi_write(tx_data[i], SPI_TBR); + + cur_len = i; + + if (sh_spi_read(SPI_CR4) & SPI_WPABRT) { + /* Abort the transaction */ + flags |= SPI_XFER_END; + sh_spi_set_bit(SPI_WPABRT, SPI_CR4); + ret = 1; + break; + } + + remain -= cur_len; + tx_data += cur_len; + + if (remain > 0) + write_fifo_empty_wait(); + } + + if (flags & SPI_XFER_END) { + tmp = sh_spi_read(SPI_CR1); + tmp = tmp & ~(SPI_SSD | SPI_SSDB); + sh_spi_write(tmp, SPI_CR1); + sh_spi_set_bit(SPI_SSA, SPI_CR1); + udelay(100); + write_fifo_empty_wait(); + } + + return ret; +} + +static int sh_spi_receive(unsigned char *rx_data, unsigned int len, + unsigned long flags) +{ + int i; + unsigned long tmp; + + if (len > SPI_MAX_BYTE) + sh_spi_write(SPI_MAX_BYTE, SPI_CR3); + else + sh_spi_write(len, SPI_CR3); + + tmp = sh_spi_read(SPI_CR1); + tmp = tmp & ~(SPI_SSD | SPI_SSDB); + sh_spi_write(tmp, SPI_CR1); + sh_spi_set_bit(SPI_SSA, SPI_CR1); + + for (i = 0; i < len; i++) { + if (recvbuf_wait()) + return 0; + + rx_data[i] = (unsigned char)sh_spi_read(SPI_RBR); + } + sh_spi_write(0, SPI_CR3); + + return 0; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + const unsigned char *tx_data = dout; + unsigned char *rx_data = din; + unsigned int len = bitlen / 8; + int ret = 0; + + if (flags & SPI_XFER_BEGIN) + sh_spi_write(sh_spi_read(SPI_CR1) & ~SPI_SSA, SPI_CR1); + + if (tx_data) + ret = sh_spi_send(tx_data, len, flags); + + if (ret == 0 && rx_data) + ret = sh_spi_receive(rx_data, len, flags); + + if (flags & SPI_XFER_END) { + sh_spi_set_bit(SPI_SSD, SPI_CR1); + udelay(100); + + sh_spi_clear_bit(SPI_SSA | SPI_SSDB | SPI_SSD, SPI_CR1); + clear_fifo(); + } + + return ret; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + +} + -- 1.7.1

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[U-Boot] {Spam?} NetRxPackets
by Marcel 19 Jan '11

19 Jan '11

Hi, ether.c contains the following code : req->buf = (u8 *) NetRxPackets[0]; req->length = size; req->complete = rx_complete; retval = usb_ep_queue(dev->out_ep, req, gfp_flags); My USB controller code that I'm writing responds that req->buf is NULL. So the OUT packets don't get processed. I know OUT data arrives in my controller code as I can read it, so my OUT endpoint is working. Also my status endpoint is working correctly and my guess is there's nothing wrong with my controller code. Anyone have an idea how NetRxPackets is allocated ? Best regards, Marcel

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[U-Boot] [PATCH V4 0/5] Add Pantheon soc and dkb board support
by Lei Wen 19 Jan '11

19 Jan '11

This patch set add the Pantheon soc and dkb board support. V2: This patch seris update the seperate mv_common part as suggested. V3: Fix config.h include place and copyright claim year. V4: Add change log to each patch. Lei Wen (5): mv: seperate kirkwood and armada from common setting ARM: Add Support for Marvell Pantheon Familiy SoCs serial: add pantheon soc support mvmfp: add MFP configuration support for PANTHEON Pantheon: Add Board Support for Marvell dkb board MAINTAINERS | 4 + arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++++++++++ arch/arm/cpu/arm926ejs/pantheon/dram.c | 130 ++++++++++++++++ arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 +++++++++++++++++++++++++ arch/arm/include/asm/arch-armada100/config.h | 50 ++++++ arch/arm/include/asm/arch-kirkwood/config.h | 145 ++++++++++++++++++ arch/arm/include/asm/arch-pantheon/config.h | 44 ++++++ arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++++++++++ arch/arm/include/asm/arch-pantheon/mfp.h | 42 +++++ arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++++++ board/Marvell/dkb/Makefile | 51 ++++++ board/Marvell/dkb/dkb.c | 53 +++++++ boards.cfg | 1 + drivers/gpio/mvmfp.c | 2 + drivers/serial/serial.c | 2 + include/configs/aspenite.h | 1 + include/configs/dkb.h | 64 ++++++++ include/configs/mv-common.h | 147 +++--------------- 19 files changed, 1071 insertions(+), 126 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c create mode 100644 arch/arm/include/asm/arch-armada100/config.h create mode 100644 arch/arm/include/asm/arch-kirkwood/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h create mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h create mode 100644 board/Marvell/dkb/Makefile create mode 100644 board/Marvell/dkb/dkb.c create mode 100644 include/configs/dkb.h

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[U-Boot] [PATCH 1/2] net: sh_eth: add cache handling
by Yoshihiro Shimoda 19 Jan '11

19 Jan '11

Some CPU needs cache handling. So this patch add the config of CONFIG_SH_ETHER_CACHE_WRITEBACK, and it calls wback function. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- drivers/net/sh_eth.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 86cc324..53d918d 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -36,6 +36,12 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif +#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK +#define flush_cache_wback(addr, len) \ + dcache_wback_range((u32)addr, (u32)(addr + len - 1)) +#else +#define flush_cache_wback(...) +#endif #define SH_ETH_PHY_DELAY 50000 @@ -197,6 +203,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) } /* Update tx descriptor */ + flush_cache_wback(packet, len); port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); port_info->tx_desc_cur->td1 = len << 16; /* Must preserve the end of descriptor list indication */ @@ -312,6 +319,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & ~(TX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); port_info->tx_desc_cur = port_info->tx_desc_base; @@ -361,6 +369,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & ~(RX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); -- 1.7.1

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[U-Boot] [PATCH] add checking the CONFIG_ENV_IS_IN_SPI_FLASH in Enbedded env
by Yoshihiro Shimoda 19 Jan '11

19 Jan '11

Fix the problem which cannot build the U-boot, if we only set the CONFIG_ENV_IS_IN_SPI_FLASH. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- include/environment.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/environment.h b/include/environment.h index 082b3e1..8a4f393 100644 --- a/include/environment.h +++ b/include/environment.h @@ -106,6 +106,7 @@ extern unsigned long nand_env_oob_offset; /* Embedded env is only supported for some flash types */ #ifdef CONFIG_ENV_IS_EMBEDDED # if !defined(CONFIG_ENV_IS_IN_FLASH) && \ + !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \ !defined(CONFIG_ENV_IS_IN_NAND) && \ !defined(CONFIG_ENV_IS_IN_ONENAND) # error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type" -- 1.7.1

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[U-Boot] Microsoft New Year Promotion
by MICROSOFT EMAIL PROMOTION 19 Jan '11

19 Jan '11

Microsoft New Year Promotion You are a winner of £450,000 Pounds Sterling courtesy of Microsoft Corporation,United Kingdom in our monthly lottery held on 18th January 2011. your secret pin code 092075ML and your reference number REF NO:MICRO-L/2009-END10. Please acknowledge the receipt of this email by sending your details below to: NAME: Glenn Bradley EMAIL: mrglennbradley1(a)yahoo.com.hk PLEASE NOTE YOU ARE TO SEND THE FOLLOWING INFORMATION TO CLAIM YOUR PRIZE: 1.Full Name:.... 2.Address:...... 3.Phone:........ 4.Country:...... 5.Sex/Gender:... YOURS SINCERELY, STACY GARRETS.

1 0

[U-Boot] [PATCH] Net: Add Intel E1000 82574L PCIe card support
by Roy Zang 19 Jan '11

19 Jan '11

Add Intel E1000 82574L PCIe card support. Test on MPC8544DS and MPC8572 board. Add the missing contact information for future support. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- based on commit e1ccf97c5d7651664d37c0c5aa243874b8851b2d drivers/net/e1000.c | 35 +++++++++++++++++++++++++++-------- drivers/net/e1000.h | 11 +++++++++++ include/pci_ids.h | 1 + 3 files changed, 39 insertions(+), 8 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 5f390bd..a545cd1 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -40,6 +40,10 @@ tested on both gig copper and gig fiber boards * Copyright (C) Linux Networx. * Massive upgrade to work with the new intel gigabit NICs. * <ebiederman at lnxi dot com> + * + * Copyright 2009, 2011 Freescale Semiconductor, Inc. + * Authors: Roy Zang <tie-fei.zang(a)freescale.com> + * - Add PCI Express card support in Jul. 2009 */ #include "e1000.h" @@ -100,6 +104,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, @@ -331,7 +336,7 @@ static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) if (hw->mac_type == e1000_ich8lan) return FALSE; - if (hw->mac_type == e1000_82573) { + if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { eecd = E1000_READ_REG(hw, EECD); /* Isolate bits 15 & 16 */ @@ -364,7 +369,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw) return -E1000_ERR_SWFW_SYNC; eecd = E1000_READ_REG(hw, EECD); - if (hw->mac_type != e1000_82573) { + if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) { /* Request EEPROM Access */ if (hw->mac_type > e1000_82544) { eecd |= E1000_EECD_REQ; @@ -498,6 +503,7 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->use_eewr = FALSE; break; case e1000_82573: + case e1000_82574: eeprom->type = e1000_eeprom_spi; eeprom->opcode_bits = 8; eeprom->delay_usec = 1; @@ -1317,6 +1323,9 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_82573L: hw->mac_type = e1000_82573; break; + case E1000_DEV_ID_82574L: + hw->mac_type = e1000_82574; + break; case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: @@ -1487,6 +1496,7 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) E1000_WRITE_REG(hw, TARC1, reg_tarc1); break; case e1000_82573: + case e1000_82574: reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); reg_ctrl_ext &= ~(1 << 23); reg_ctrl_ext |= (1 << 22); @@ -1728,12 +1738,11 @@ e1000_init_hw(struct eth_device *nic) | E1000_TXDCTL_FULL_TX_DESC_WB; E1000_WRITE_REG(hw, TXDCTL1, ctrl); break; - } - - if (hw->mac_type == e1000_82573) { - uint32_t gcr = E1000_READ_REG(hw, GCR); - gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; - E1000_WRITE_REG(hw, GCR, gcr); + case e1000_82573: + case e1000_82574: + reg_data = E1000_READ_REG(hw, GCR); + reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; + E1000_WRITE_REG(hw, GCR, reg_data); } #if 0 @@ -1812,6 +1821,7 @@ e1000_setup_link(struct eth_device *nic) switch (hw->mac_type) { case e1000_ich8lan: case e1000_82573: + case e1000_82574: hw->fc = e1000_fc_full; break; default: @@ -4560,6 +4570,9 @@ static int e1000_set_phy_type (struct e1000_hw *hw) hw->phy_type = e1000_phy_gg82563; break; } + case BME1000_E_PHY_ID: + hw->phy_type = e1000_phy_bm ; + break; /* Fall Through */ default: /* Should never have loaded on this device */ @@ -4646,6 +4659,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; break; + case e1000_82574: + if (hw->phy_id == BME1000_E_PHY_ID) + match = TRUE; + break; case e1000_80003es2lan: if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; @@ -4710,6 +4727,7 @@ e1000_set_media_type(struct e1000_hw *hw) break; case e1000_ich8lan: case e1000_82573: + case e1000_82574: /* The STATUS_TBIMODE bit is reserved or reused * for the this device. */ @@ -5125,6 +5143,7 @@ void e1000_get_bus_type(struct e1000_hw *hw) case e1000_82571: case e1000_82572: case e1000_82573: + case e1000_82574: case e1000_80003es2lan: hw->bus_type = e1000_bus_type_pci_express; break; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index eb0804b..4c60b70 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -24,12 +24,18 @@ Linux NICS <linux.nics(a)intel.com> Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + *******************************************************************************/ /* e1000_hw.h * Structures, enums, and macros for the MAC */ +/* Copyright 2009, 2011 Freescale Semiconductor, Inc. + * Authors: Roy Zang <tie-fei.zang(a)freescale.com> + * - Add PCI Express card support in Jul. 2009 + */ + #ifndef _E1000_HW_H_ #define _E1000_HW_H_ @@ -81,6 +87,7 @@ typedef enum { e1000_82571, e1000_82572, e1000_82573, + e1000_82574, e1000_80003es2lan, e1000_ich8lan, e1000_num_macs @@ -200,6 +207,7 @@ typedef enum { e1000_phy_gg82563, e1000_phy_igp_3, e1000_phy_ife, + e1000_phy_bm, e1000_phy_undefined = 0xFF } e1000_phy_type; @@ -286,6 +294,7 @@ struct e1000_phy_stats { #define E1000_DEV_ID_82573E 0x108B #define E1000_DEV_ID_82573E_IAMT 0x108C #define E1000_DEV_ID_82573L 0x109A +#define E1000_DEV_ID_82574L 0x10D3 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 @@ -2417,6 +2426,8 @@ struct e1000_hw { #define L1LXT971A_PHY_ID 0x001378E0 #define GG82563_E_PHY_ID 0x01410CA0 +#define BME1000_E_PHY_ID 0x01410CB0 + /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF #define PHY_SOF 0x01 diff --git a/include/pci_ids.h b/include/pci_ids.h index cb8398d..02a6c6e 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1853,6 +1853,7 @@ #define PCI_DEVICE_ID_INTEL_82573E 0x108B #define PCI_DEVICE_ID_INTEL_82573E_IAMT 0x108C #define PCI_DEVICE_ID_INTEL_82573L 0x109A +#define PCI_DEVICE_ID_INTEL_82574L 0x10D3 #define PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3 0x10B5 #define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT 0x1096 #define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT 0x1098 -- 1.7.3.5

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[U-Boot] [PATCH 1/2] Fix typo ("comand" instead of "command")
by Loïc Minier 19 Jan '11

19 Jan '11

Signed-off-by: Loïc Minier <loic.minier(a)linaro.org> --- tools/kwbimage.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 7b26920..964796e 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -33,7 +33,7 @@ * Supported commands for configuration file */ static table_entry_t kwbimage_cmds[] = { - {CMD_BOOT_FROM, "BOOT_FROM", "boot comand", }, + {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, {CMD_NAND_ECC_MODE, "NAND_ECC_MODE", "NAND mode", }, {CMD_NAND_PAGE_SIZE, "NAND_PAGE_SIZE", "NAND size", }, {CMD_SATA_PIO_MODE, "SATA_PIO_MODE", "SATA mode", }, -- 1.7.2.3

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[U-Boot] [PATCH] cmd_jffs2: Fix get_part_sector_size_nor() overflow bug
by Peter Tyser 19 Jan '11

19 Jan '11

When a flash partition was positioned at the very top of a 32-bit memory map (eg located at 0xf8000000 with a size of 0x8000000) get_part_sector_size_nor() would incorrectly calculate the partition's ending address to 0x0 due to overflow. When the overflow occurred get_part_sector_size_nor() would falsely return a sector size of 0. A sector size of 0 results in subsequent jffs2 operations failing. To workaround the overflow subtract 1 from calculated address of the partition endpoint. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- common/cmd_jffs2.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 0e7a6b0..27296dd 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -281,7 +281,7 @@ static inline u32 get_part_sector_size_nor(struct mtdids *id, struct part_info * flash = &flash_info[id->num]; start_phys = flash->start[0] + part->offset; - end_phys = start_phys + part->size; + end_phys = start_phys + part->size - 1; for (i = 0; i < flash->sector_count; i++) { if (flash->start[i] >= end_phys) -- 1.7.0.4

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