September 2010 - U-Boot

[U-Boot] [PATCH] ARMV7: OMAP4: Calculate SDRAM size
by Steve Sakoman 28 Sep '10

28 Sep '10

From: Aneesh V <aneesh(a)ti.com> Calculate the SDRAM size from DMM configuration registers instead of using hard-coded values. This gives correct values for all different boards. It's assumed that DMM sections do not overlap memory areas. Signed-off-by: Aneesh V <aneesh(a)ti.com> Tested-by: Steve Sakoman <steve(a)sakoman.com> --- arch/arm/cpu/armv7/omap4/board.c | 30 +++++++++++++++++++++++++++++- arch/arm/include/asm/arch-omap4/omap4.h | 10 ++++++++++ 2 files changed, 39 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 195be6e..8c1f395 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -30,6 +30,7 @@ #include <common.h> #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> +#include <asm/sizes.h> /* * Routine: s_init @@ -66,6 +67,33 @@ void watchdog_init(void) writel(WD_UNLOCK2, &wd2_base->wspr); } + +/* + * This function finds the SDRAM size available in the system + * based on DMM section configurations + * This is needed because the size of memory installed may be + * different on different versions of the board + */ +u32 sdram_size(void) +{ + u32 section, i, total_size = 0, size, addr; + for (i = 0; i < 4; i++) { + section = __raw_readl(DMM_LISA_MAP_BASE + i*4); + addr = section & DMM_LISA_MAP_SYS_ADDR_MASK; + /* See if the address is valid */ + if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) && + (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) { + size = ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >> + DMM_LISA_MAP_SYS_SIZE_SHIFT); + size = 1 << size; + size *= SZ_16M; + total_size += size; + } + } + return total_size; +} + + /* * Routine: dram_init * Description: sets uboots idea of sdram size @@ -75,7 +103,7 @@ int dram_init(void) DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start = 0x80000000; - gd->bd->bi_dram[0].size = 512 << 20; + gd->bd->bi_dram[0].size = sdram_size(); return 0; } diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index d0c808d..a30bb33 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -42,6 +42,10 @@ #define OMAP44XX_L4_WKUP_BASE 0x4A300000 #define OMAP44XX_L4_PER_BASE 0x48000000 +#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 +#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 + + /* CONTROL */ #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) @@ -66,6 +70,12 @@ /* GPMC */ #define OMAP44XX_GPMC_BASE 0x50000000 +/* DMM */ +#define OMAP44XX_DMM_BASE 0x4E000000 +#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40) +#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) +#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 +#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) /* * Hardware Register Details */ -- 1.7.0.4

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[U-Boot] [PATCH] ARMV7: OMAP: Use default vendor/product ID for USB gadget
by Steve Sakoman 28 Sep '10

28 Sep '10

TI hasn't reserved a USB Product ID for gadgets, so use the default vendor and product ID to avoid confusion. Signed-off-by: Steve Sakoman <steve(a)sakoman.com> --- include/configs/omap3_beagle.h | 5 ----- include/configs/omap4_panda.h | 5 ----- include/configs/omap4_sdp4430.h | 5 ----- 3 files changed, 0 insertions(+), 15 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 71553f9..fbe96aa 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -111,11 +111,6 @@ #define CONFIG_USB_DEVICE 1 #define CONFIG_USB_TTY 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "Beagle" /* commands to include */ #include <config_cmd_default.h> diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index a0d27a4..d4a1d1c 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -120,11 +120,6 @@ #define CONFIG_USB_DEVICE 1 #define CONFIG_USB_TTY 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "OMAP4 Panda" /* Flash */ #define CONFIG_SYS_NO_FLASH 1 diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index d5439f9..98a86c3 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -121,11 +121,6 @@ #define CONFIG_USB_DEVICE 1 #define CONFIG_USB_TTY 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "SDP4430" /* Flash */ #define CONFIG_SYS_NO_FLASH 1 -- 1.7.0.4

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[U-Boot] Coldfire Architecture and SELF
by SANCHEZ VITORICA, GUILLERMO 28 Sep '10

28 Sep '10

Hi all, I wanted to develop a personalized U-Boot to my MCF54455 Coldfire V4 microcontroller. I got the sources from DENX FTP server and now I wanted to get the SELF but I don't really know wich one should I download. Maybe someone could push me in the right direction?. Thanks. Cheers: Guillermo Sanchez Vitorica Email: gsanchez(a)gamesacorp.com " Before printing this mail or any of its attachments, please be sure it is absolutely necessary. Protection of the environment is everyone's responsibility. We have the right to enjoy it but also the obligation to preserve it" ADVERTENCIA: "El contenido de la presente comunicación y en su caso, sus anexos, tiene carácter meramente informativo sin que represente, en ningún caso, oferta, aceptación u opinión vinculantes para GAMESA, salvo que así se indique expresamente en documento aparte suscrito por persona con facultades suficientes. Esta comunicación está dirigida exclusivamente a su destinatario y puede contener información privada y confidencial. GAMESA no asumirá obligación alguna, ni ejecutará órdenes, encargos o pedidos recibidos y /o enviados por correo electrónico." DISCLAIMER: "The content of the present communication, and its annexes, is for informational purposes only and does not in any case constitute a binding offer, acceptance or opinion for GAMESA unless so set forth in separate document subscribed by a representative of the company with sufficient faculties to do so. This message may contain private and confidential information and is directed exclusively to its addressee. GAMESA will not assume any obligation, nor execute orders or mandates received or sent by electronic mail."

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[U-Boot-Users] how to u-boot in LPC2468 board using uClinux
by anand 28 Sep '10

28 Sep '10

do any one have u-boot.bin file for LPC2468 i downloaded u-boot-1.1.6 but i din't get the u-boot prombt in the terminal window its gets struck in the starting display itself anyone pls help thanks in advance

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Re: [U-Boot] [PATCH] usb: fix usb start problem with SMSC USB hub and Toshiba USB stick
by Roland Kletzing 28 Sep '10

28 Sep '10

Hello, i`m searching for a solution for a while, so i`m trying my luck here. I`m using Seagate Dockstar (ARM926EJ-S based) NAS device and installed Debian ARM on that as documented at http://jeff.doozan.com/debian/ While it`s running fine with a sandisk flash usb stick and a sd-card in a usb cardreader, i`m not able to get the thingie boot with 2 different real 2.5" ide disks attached to two different kinds of ide2usb converter cables. The pogoplug linux (which runs on dockstar by default) detects the disks very fine and debian installation from there runs fine too, but booting from that always fails like this: U-Boot 2010.06-00695-gbd23130-dirty (Aug 30 2010 - 23:04:56) Marvell-Dockstar/Pogoplug by Jeff Doozan Hit any key to stop autoboot: 0 (Re)start USB... USB: Register 10011 NbrPorts 1 USB EHCI 1.00 scanning bus for devices... 3 USB Device(s) found scanning bus for storage devices... 1 Storage Device(s) found ** Bad partition 1 ** ** Bad partition 1 ** Wrong Image Format for bootm command ERROR: can't get kernel image! stopping USB.. I found a LOT of references on the net where people report similar problems for sheevaplug, pogoplug, dockstar - even with flash based media and just came across this posting on u-boot list. looks related to me!? i assume there is something which needs be fixed in u-boot and this is not storage-device specific but must be specific to the usb chipset or platform. the problem is that i don`t know how to unbrick dockstar yet, but i`d like to let you know that a lot of people will be happy if this gets fixed. i will read deeper into how to build uboot and safely replace it on my device, if there is anything more i can do to provide input or do testing please let me know. i think i can dig out tons of reports of similar issues. as my "i replace my homeserver with a dockstar"-projects depends on this, maybe i can even donate a dockstar for the person willing or be able to fix this issue. from another post: >Is this problem only valid for the EHCI code? I can imagine that the >other host controllers (like UHCI and OHCI and so on) code suffer the >same problem and need similar fixes... >(At least I know that I have here a couple of USB sticks that show >similar problems with OHCI ;-) ) If this helps - this is some info from a successful linux boot on that dockstar platform. usb runs perfectly when in linux, but it seems that there are problems only in u-boot. [ 1.180000] ehci_marvell ehci_marvell.70059: Marvell Orion EHCI [ 1.190000] ehci_marvell ehci_marvell.70059: new USB bus registered, assigned bus number 1 [ 1.230000] ehci_marvell ehci_marvell.70059: irq 19, io base 0xf1050100 [ 1.250000] ehci_marvell ehci_marvell.70059: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004 [ 1.250000] usb usb1: configuration #1 chosen from 1 choice [ 1.260000] hub 1-0:1.0: USB hub found [ 1.260000] hub 1-0:1.0: 1 port detected [ 1.380000] ohci_hcd: 2006 August 04 USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.380000] USB Universal Host Controller Interface driver v3.0 [ 1.660000] usb 1-1: new high speed USB device using ehci_marvell and address 2 [ 1.810000] usb 1-1: configuration #1 chosen from 1 choice [ 1.810000] hub 1-1:1.0: USB hub found [ 1.820000] hub 1-1:1.0: 4 ports detected [ 2.170000] usb 1-1.3: new high speed USB device using ehci_marvell and address 3 [ 2.270000] usb 1-1.3: configuration #1 chosen from 1 choice regards roland ps: i found the following line in common/usb_storage.c - so maybe we cannot expect the usb code to work with real disks at all !? /* * New Note: * Support for USB Mass Storage Devices (BBB) has been added. It has * only been tested with USB memory sticks. */ quote: [U-Boot] [PATCH] usb: fix usb start problem with SMSC USB hub and Toshiba USB stick Anatolij Gustschin agust at denx.de Tue Aug 31 20:45:14 CEST 2010 Previous message: [U-Boot] [PATCH] zlib: Add further watchdog reset calls Next message: [U-Boot] [PATCH] [v2] mpc8610: refactor DIU initialization code to use existing bitmap and logo features Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] Checking the status field of the qTD token in the current code do not take into acount cases where endpoint stall (halted) bit is set together with some other status bits. As a result clearing stall on an endpoint won't be done if other status bits were set. E.g. 'usb start' often fails with Toshiba USB stick 0x930/0x6545 connected to the SMSC USB 2.0 hub 0x424/0x2514. Debugging the issue showed that while bulk IN transfers with length of 13 or 18 the status field of the qTD token sometimes indicates trans- action error (XactErr) and sometimes additionally endpoint halted state. In the latter case resetting the USB device in error recovery code fails as no clear stall request on the endpoint will be done. The patch fixes status field checking code to properly handle endpoint halted state. However this fix is not enough to solve 'usb start' problem with hub/stick combination mentioned above. Running with lot of debug code in ehci_submit_async() I've never seen the problem with usb stick recognition. After removing this debug code the similar problem sometimes showed up again. Therefore the patch also adds delay in ehci_submit_async() for above-mentioned hub/stick combination. Even without this delay the fix is an improvement since it fixes the problem with board freezy after subsequent failed 'usb start/stop' cycles as it was observed on mpc5121ads board. Signed-off-by: Anatolij Gustschin <agust at denx.de> --- common/usb_storage.c | 5 +++-- drivers/usb/host/ehci-hcd.c | 8 ++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/common/usb_storage.c b/common/usb_storage.c index 76949b8..5ca92c3 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -680,7 +680,8 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT * 5); /* special handling of STALL in DATA phase */ - if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { + if ((result < 0) && + (us->pusb_dev->status & (USB_ST_STALLED | USB_ST_CRC_ERR))) { USB_STOR_PRINTF("DATA:stall\n"); /* clear the STALL on the endpoint */ result = usb_stor_BBB_clear_endpt_stall(us, @@ -710,7 +711,7 @@ again: /* special handling of STALL in STATUS phase */ if ((result < 0) && (retry < 1) && - (us->pusb_dev->status & USB_ST_STALLED)) { + (us->pusb_dev->status & (USB_ST_STALLED | USB_ST_CRC_ERR))) { USB_STOR_PRINTF("STATUS:stall\n"); /* clear the STALL on the endpoint */ result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 37d056e..7463a75 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -430,6 +430,12 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, usbsts = ehci_readl(&hcor->or_usbsts); ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); + if (dev->descriptor.idVendor == 0x930 && + dev->descriptor.idProduct == 0x6545 && + dev->parent->descriptor.idVendor == 0x424 && + dev->parent->descriptor.idProduct == 0x2514) + wait_ms(10); + /* Enable async. schedule. */ cmd = ehci_readl(&hcor->or_usbcmd); cmd |= CMD_ASE; @@ -490,6 +496,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, break; default: dev->status = USB_ST_CRC_ERR; + if ((token & 0x40) == 0x40) + dev->status |= USB_ST_STALLED; break; } dev->act_len = length - ((token >> 16) & 0x7fff); -- 1.7.0.4

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[U-Boot] [PATCH] ppc44x: config GPIOs for USB on canyonlands board
by Rupjyoti Sarmah 28 Sep '10

28 Sep '10

The GPIO 16 and 19 reconfiguration should be done once USB is initialized. So moved the reconfiguration to the USB init function Signed-off-by: Rupjyoti Sarmah <rsarmah(a)apm.com> --- board/amcc/canyonlands/canyonlands.c | 19 +++++++++---------- 1 files changed, 9 insertions(+), 10 deletions(-) diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 158f7bb..1e547f7 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -195,16 +195,6 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - if (pvr_460ex()) { - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - } #endif return 0; @@ -222,6 +212,15 @@ int usb_board_init(void) val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); out_8(&bcsr_data->usb_ctrl, val); + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + return 0; } -- 1.5.6.3

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[U-Boot] [PATCH 1/2] ixp/npe: Remove duplicated comment
by Thomas Weber 28 Sep '10

28 Sep '10

Signed-off-by: Thomas Weber <weber(a)corscience.de> --- arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c index f5a4c5f..a9ea8bc 100644 --- a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c +++ b/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c @@ -51,11 +51,6 @@ /* * Put the user defined include files required. */ - - -/* - * Put the user defined include files required. - */ #include "IxOsal.h" #include "IxNpeDl.h" #include "IxNpeDlNpeMgr_p.h" -- 1.7.3

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[U-Boot] [PATCH] Add support for operating system OSE
by Torkel Lundgren 28 Sep '10

28 Sep '10

Add OSE as operating system for mkimage and bootm. Signed-off-by: Torkel Lundgren <torkel.lundgren(a)enea.com> --- common/cmd_bootm.c | 39 +++++++++++++++++++++++++++++++++++++++ common/image.c | 1 + include/config_defaults.h | 1 + include/image.h | 1 + 4 files changed, 42 insertions(+), 0 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 4c6ed48..b2c2e07 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -118,6 +118,9 @@ extern void lynxkdi_boot (image_header_t *); #ifdef CONFIG_BOOTM_RTEMS static boot_os_fn do_bootm_rtems; #endif +#if defined(CONFIG_BOOTM_OSE) +static boot_os_fn do_bootm_ose; +#endif #if defined(CONFIG_CMD_ELF) static boot_os_fn do_bootm_vxworks; static boot_os_fn do_bootm_qnxelf; @@ -141,6 +144,9 @@ static boot_os_fn *boot_os[] = { #ifdef CONFIG_BOOTM_RTEMS [IH_OS_RTEMS] = do_bootm_rtems, #endif +#if defined(CONFIG_BOOTM_OSE) + [IH_OS_OSE] = do_bootm_ose, +#endif #if defined(CONFIG_CMD_ELF) [IH_OS_VXWORKS] = do_bootm_vxworks, [IH_OS_QNX] = do_bootm_qnxelf, @@ -1382,6 +1388,39 @@ static int do_bootm_rtems (int flag, int argc, char * const argv[], } #endif /* CONFIG_BOOTM_RTEMS */ +#if defined(CONFIG_BOOTM_OSE) +static int do_bootm_ose (int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + + if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) + return 1; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset ("OSE"); + return 1; + } +#endif + + entry_point = (void (*)(void))images->ep; + + printf ("## Transferring control to OSE (at address %08lx) ...\n", + (ulong)entry_point); + + show_boot_progress (15); + + /* + * OSE Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif /* CONFIG_BOOTM_OSE */ + #if defined(CONFIG_CMD_ELF) static int do_bootm_vxworks (int flag, int argc, char * const argv[], bootm_headers_t *images) diff --git a/common/image.c b/common/image.c index fcb938b..3a2f25e 100644 --- a/common/image.c +++ b/common/image.c @@ -103,6 +103,7 @@ static table_entry_t uimage_os[] = { { IH_OS_LYNXOS, "lynxos", "LynxOS", }, #endif { IH_OS_NETBSD, "netbsd", "NetBSD", }, + { IH_OS_OSE, "ose", "Enea OSE", }, { IH_OS_RTEMS, "rtems", "RTEMS", }, { IH_OS_U_BOOT, "u-boot", "U-Boot", }, #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC) diff --git a/include/config_defaults.h b/include/config_defaults.h index 0337163..abdf3be 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -12,6 +12,7 @@ /* Support bootm-ing different OSes */ #define CONFIG_BOOTM_LINUX 1 #define CONFIG_BOOTM_NETBSD 1 +#define CONFIG_BOOTM_OSE 1 #define CONFIG_BOOTM_RTEMS 1 #define CONFIG_GZIP 1 diff --git a/include/image.h b/include/image.h index bcc08d1..18a9f0e 100644 --- a/include/image.h +++ b/include/image.h @@ -83,6 +83,7 @@ #define IH_OS_ARTOS 19 /* ARTOS */ #define IH_OS_UNITY 20 /* Unity OS */ #define IH_OS_INTEGRITY 21 /* INTEGRITY */ +#define IH_OS_OSE 22 /* OSE */ /* * CPU Architecture Codes (supported by Linux) -- 1.6.3.3

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[U-Boot] [PATCH] README: Fix description of version numbering scheme
by Thomas Weber 28 Sep '10

28 Sep '10

The version numbering scheme was changed in Oct, 2008. This patch brings the documentation to the actual level. The description is taken from: http://www.denx.de/wiki/U-Boot/ReleaseCycle Signed-off-by: Thomas Weber <weber(a)corscience.de> --- README | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/README b/README index ccaace7..58ef06a 100644 --- a/README +++ b/README @@ -126,14 +126,16 @@ the string "u_boot" or on "U_BOOT". Example: Versioning: =========== -U-Boot uses a 3 level version number containing a version, a -sub-version, and a patchlevel: "U-Boot-2.34.5" means version "2", -sub-version "34", and patchlevel "4". - -The patchlevel is used to indicate certain stages of development -between released versions, i. e. officially released versions of -U-Boot will always have a patchlevel of "0". - +Starting with the release in October 2008, the names of the releases were +changed from numerical release numbers without deeper meaning into a +time stamp based numbering. Regular releases are identified by names +consisting of the calendar year and month of the release date. +Additional fields (if present) indicate intermediate (hot fix) releases, +and bug fix releases in "stable" maintenance trees. + +Examples: + U-Boot v2010.09-rc1 - version September 2010, release candidate 1 + U-Boot v2009.11.1 - version November 2009, bug fix release 1 Directory Hierarchy: ==================== -- 1.7.3

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[U-Boot] [PATCH v5 1/2] APM821xx: Add CPU support
by tmarri＠apm.com 28 Sep '10

28 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- V4: * Rebase with Stefan Roese tree V5: * Move CONFIG_SYS_PERIPHERAL_BASE to apm821xx.h --- arch/powerpc/cpu/ppc4xx/cpu.c | 19 ++++++++ arch/powerpc/cpu/ppc4xx/cpu_init.c | 5 +- arch/powerpc/cpu/ppc4xx/speed.c | 75 ++++++++++++++++++++++++++++++- arch/powerpc/cpu/ppc4xx/start.S | 11 +++-- arch/powerpc/include/asm/apm821xx.h | 70 ++++++++++++++++++++++++++++ arch/powerpc/include/asm/ppc4xx-ebc.h | 3 +- arch/powerpc/include/asm/ppc4xx-isram.h | 14 +++++- arch/powerpc/include/asm/ppc4xx-sdram.h | 12 +++--- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/ppc4xx.h | 4 ++ arch/powerpc/include/asm/processor.h | 1 + 11 files changed, 200 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 6009b0c..f3bdf18 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -250,6 +250,20 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_APM821XX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "RESERVED", + "RESERVED", + "RESERVED", + "NAND (8 bits)", + "NOR (8 bits)", + "NOR (8 bits) w/PLL Bypassed", + "I2C (Addr 0x54)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#endif #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -590,6 +604,11 @@ int checkcpu (void) strcpy(addstr, "No Security support"); break; + case PVR_APM821XX_RA: + puts("APM821XX Rev. A"); + strcpy(addstr, "Security support"); + break; + case PVR_VIRTEX5: puts("440x5 VIRTEX5"); break; diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index d54b30e..125241b 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -237,7 +237,8 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if !defined(CONFIG_APM821XX) && (defined(CONFIG_405EP) ||\ + defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -393,7 +394,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index abd4e91..09d6671 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -189,7 +189,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -250,6 +250,78 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } +#if defined(CONFIG_APM821XX) + +void get_sys_info(sys_info_t *sysInfo) +{ + unsigned long plld; + unsigned long temp; + unsigned long mul; + unsigned long cpudv; + unsigned long plb2dv; + unsigned long ddr2dv; + + /* Calculate Forward divisor A and Feeback divisor */ + mfcpr(CPR0_PLLD, plld); + + temp = CPR0_PLLD_FWDVA(plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); + + temp = CPR0_PLLD_FDV(plld); + sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + + /* Calculate OPB clock divisor */ + mfcpr(CPR0_OPBD, temp); + temp = CPR0_OPBD_OPBDV(temp); + sysInfo->pllOpbDiv = temp ? temp : 4; + + /* Calculate Peripheral clock divisor */ + mfcpr(CPR0_PERD, temp); + temp = CPR0_PERD_PERDV(temp); + sysInfo->pllExtBusDiv = temp ? temp : 4; + + /* Calculate CPU clock divisor */ + mfcpr(CPR0_CPUD, temp); + temp = CPR0_CPUD_CPUDV(temp); + cpudv = temp ? temp : 8; + + /* Calculate PLB2 clock divisor */ + mfcpr(CPR0_PLB2D, temp); + temp = CPR0_PLB2D_PLB2DV(temp); + plb2dv = temp ? temp : 4; + + /* Calculate DDR2 clock divisor */ + mfcpr(CPR0_DDR2D, temp); + temp = CPR0_DDR2D_DDR2DV(temp); + ddr2dv = temp ? temp : 4; + + /* Calculate 'M' based on feedback source */ + mfcpr(CPR0_PLLC, temp); + temp = CPR0_PLLC_SEL(temp); + if (temp == 0) { + /* PLL internal feedback */ + mul = sysInfo->pllFbkDiv; + } else { + /* PLL PerClk feedback */ + mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv + * plb2dv * 2 * sysInfo->pllOpbDiv * + sysInfo->pllExtBusDiv; + } + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv; + sysInfo->freqPLB = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / plb2dv / 2; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqDDR = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; + sysInfo->freqUART = sysInfo->freqPLB; +} + +#else /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -307,6 +379,7 @@ void get_sys_info (sys_info_t * sysInfo) return; } +#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 7a65d9f..c2d52bf 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -703,7 +703,8 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -731,7 +732,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ + defined(CONFIG_460GT) || defined(CONFIG_APM821XX) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -744,7 +746,8 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC @@ -755,7 +758,7 @@ _start: mtdcr ISRAM1_PMEG,r1 lis r1,0x0004 /* BAS = 4_0004_0000 */ - ori r1,r1,0x0984 /* 64k */ + ori r1,r1,ISRAM1_SIZE /* ocm size */ mtdcr ISRAM1_SB0CR,r1 #endif #elif defined(CONFIG_460SX) diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h new file mode 100644 index 0000000..d08f8a6 --- /dev/null +++ b/arch/powerpc/include/asm/apm821xx.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _APM821XX_H_ +#define _APM821XX_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ +/* Memory mapped registers */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +#define SDR0_SRST0_DMC 0x00200000 +#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ +/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 + + +#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ +#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ +#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ +#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ +#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ +#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ +#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ +/* + + * Clocking Controller + + */ +/* values for clkcfga register - indirect addressing of these regs */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 + +#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 9c17e46..75af130 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -69,7 +69,8 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_APM821XX) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index d6d17ac..32e1297 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -25,7 +25,8 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_APM821XX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -42,7 +43,8 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -54,13 +56,19 @@ #define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define ISRAM1_SIZE 0x0984 /* OCM size 64k */ +#elif defined(CONFIG_APM821XX) +#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ +#endif + /* * L2 Cache */ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index ac150c2..d570d79 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -292,7 +292,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -365,7 +365,7 @@ /* * Memory controller registers */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -375,9 +375,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX */ +#else /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX */ +#endif /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -423,12 +423,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#ifndef CONFIG_405EX +#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 782d045..3714a0a 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -31,7 +31,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -252,7 +252,8 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index 87a16ec..1b98f8b 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -79,6 +79,10 @@ #include <asm/ppc460sx.h> #endif +#if defined(CONFIG_APM821XX) +#include <asm/apm821xx.h> +#endif + /* * Configure which SDRAM/DDR/DDR2 controller is equipped */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 84a1e2e..9cafe85 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -916,6 +916,7 @@ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 -- 1.6.1.rc3

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