September 2010 - U-Boot

[U-Boot] [PATCH v1 1/2] Add CPU and other peripheral support
by tmarri＠apm.com 01 Sep '10

01 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> APM82XXX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB AHB bus, DDR and Some common register definitions. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- V1: * Squash some of the patches. * add space between "||" and "\". * Add spaces around operators. * Unsigned int to u32. * Add empty line which was removed. * remove warning "unused variable" in cpu_init.c --- arch/powerpc/cpu/ppc4xx/cpu.c | 35 ++++++++++++- arch/powerpc/cpu/ppc4xx/cpu_init.c | 8 ++- arch/powerpc/cpu/ppc4xx/speed.c | 85 ++++++++++++++++++++++++++++++- arch/powerpc/cpu/ppc4xx/start.S | 10 +++- arch/powerpc/include/asm/ppc4xx-ebc.h | 4 ++ arch/powerpc/include/asm/ppc4xx-isram.h | 8 ++- arch/powerpc/include/asm/ppc4xx-sdram.h | 25 +++++++-- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/processor.h | 1 + include/ppc440.h | 57 ++++++++++++++++++++- include/ppc4xx.h | 7 ++- 11 files changed, 220 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 851065c..5fe5d8c 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -80,7 +80,8 @@ static int pci_async_enabled(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ - !defined(CONFIG_405) && !defined(CONFIG_405EX) + !defined(CONFIG_405) && !defined(CONFIG_405EX) && \ + !defined(CONFIG_APM82XXX) int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) @@ -250,6 +251,21 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_APM82XXX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "RESERVED", + "RESERVED", + "RESERVED", + "NAND (8 bits)", + "NOR (8 bits)", + "NOR (8 bits) w/PLL Bypassed", + "I2C (Addr 0x54)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -285,7 +301,7 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM82XXX) u32 reg; #endif @@ -304,6 +320,8 @@ int checkcpu (void) #if defined(CONFIG_XILINX_440) puts("IBM PowerPC 4"); +#elif defined(CONFIG_APM82XXX) + puts("APM PowerPC APM82"); #else puts("AMCC PowerPC 4"); #endif @@ -316,7 +334,7 @@ int checkcpu (void) #if defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) puts("60"); -#else +#elif !defined(CONFIG_APM82XXX) puts("40"); #endif #endif @@ -598,7 +616,18 @@ int checkcpu (void) puts("GX Rev. A"); strcpy(addstr, "No Security support"); break; +#if defined(CONFIG_APM82XXX) + case PVR_APM82XXX_RA: + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00200000) + puts("181 Rev. A"); + if (reg & 0x00100000) + strcpy(addstr, "No Security support"); + else + strcpy(addstr, "Security support"); + break; +#endif case PVR_VIRTEX5: puts("x5 VIRTEX5"); break; diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..5428909 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -222,13 +222,15 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) u32 val; #endif reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if (defined(CONFIG_405EP) || defined(CONFIG_405EX)) && \ + !defined(CONFIG_SYS_4xx_GPIO_TABLE) && !defined(CONFIG_APM82XXX) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -384,7 +386,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 906face..b613275 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -189,7 +189,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -250,6 +250,88 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } +#if defined(CONFIG_APM82XXX) + +/* + * Specific for APM82XXX + * Change: + * PLL registers reflect the current PLL setting of the chip. + * So unlike previous implementation that reads bootstrap + * registers to determine system clocking information, this + * implementation directly extracts the information from + * current PLL registers values. + */ +void get_sys_info(sys_info_t *sysInfo) +{ + unsigned long plld; + unsigned long temp; + unsigned long mul; + unsigned long cpudv; + unsigned long plb2dv; + unsigned long ddr2dv; + + /* Calculate Forward divisor A and Feeback divisor */ + mfcpr(CPR0_PLLD, plld); + + temp = CPR0_PLLD_FWDVA(plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); + + temp = CPR0_PLLD_FDV(plld); + sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + + /* Calculate OPB clock divisor */ + mfcpr(CPR0_OPBD, temp); + temp = CPR0_OPBD_OPBDV(temp); + sysInfo->pllOpbDiv = temp ? temp : 4; + + /* Calculate Peripheral clock divisor */ + mfcpr(CPR0_PERD, temp); + temp = CPR0_PERD_PERDV(temp); + sysInfo->pllExtBusDiv = temp ? temp : 4; + + /* Calculate CPU clock divisor */ + mfcpr(CPR0_CPUD, temp); + temp = CPR0_CPUD_CPUDV(temp); + cpudv = temp ? temp : 8; + + /* Calculate PLB2 clock divisor */ + mfcpr(CPR0_PLB2D, temp); + temp = CPR0_PLB2D_PLB2DV(temp); + plb2dv = temp ? temp : 4; + + /* Calculate DDR2 clock divisor */ + mfcpr(CPR0_DDR2D, temp); + temp = CPR0_DDR2D_DDR2DV(temp); + ddr2dv = temp ? temp : 4; + + /* Calculate 'M' based on feedback source */ + mfcpr(CPR0_PLLC, temp); + temp = CPR0_PLLC_SEL(temp); + if (temp == 0) { + /* PLL internal feedback */ + mul = sysInfo->pllFbkDiv; + } else { + /* PLL PerClk feedback */ + mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv + * plb2dv * 2 * sysInfo->pllOpbDiv * + sysInfo->pllExtBusDiv; + } + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv; + sysInfo->freqPLB = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / plb2dv / 2; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqDDR = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; + sysInfo->freqUART = sysInfo->freqPLB; +} + +#else + /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -307,6 +389,7 @@ void get_sys_info (sys_info_t * sysInfo) return; } +#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad..9cb818d 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -700,7 +700,8 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -728,7 +729,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ + defined(CONFIG_460GT) || defined(CONFIG_APM82XXX) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -752,7 +754,11 @@ _start: mtdcr ISRAM1_PMEG,r1 lis r1,0x0004 /* BAS = 4_0004_0000 */ +#if defined(CONFIG_APM82XXX) /* APM82XXX only has 32KB of OCM */ + ori r1,r1,0x0784 /* 32k */ +#else ori r1,r1,0x0984 /* 64k */ +#endif mtdcr ISRAM1_SB0CR,r1 #endif #elif defined(CONFIG_460SX) diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 9c17e46..245e487 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -73,6 +73,10 @@ #define EBC_NUM_BANKS 3 #endif +#if defined(CONFIG_APM82XXX) +#define EBC_NUM_BANKS 3 +#endif + /* Bank Configuration Register */ #define EBC_BXCR(n) (n) #define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17)) diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index d6d17ac..fa9e164 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -25,7 +25,8 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_APM82XXX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -42,7 +43,8 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -60,7 +62,7 @@ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 4ec1ef8..a6cdace 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -292,7 +292,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -322,6 +322,7 @@ * Revisit this file to check if all these 405EX defines are correct and * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02 */ +#define SDRAM_MBXCF_BASE_ENCODE(n) (((n) & 0xFFC00000) >> 3) #define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF) #define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0) #define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1) @@ -346,6 +347,18 @@ #define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB #define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB #define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB +#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0) +#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1) +#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2) +#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3) +#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4) +#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5) +#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6) +#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7) +#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8) +#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9) +#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0) +#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1) #endif /* CONFIG_405EX */ /* The mode definitions are the same for all PPC4xx variants */ @@ -365,7 +378,7 @@ /* * Memory controller registers */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM82XXX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -375,9 +388,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX */ +#else /* CONFIG_405EX || CONFIG_APM82XXX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX */ +#endif /* CONFIG_405EX || CONFIG_APM82XXX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -423,12 +436,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#ifndef CONFIG_405EX +#if !defined(CONFIG_405EX) && !defined(CONFIG_APM82XXX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM82XXX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 782d045..787e9f7 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -31,7 +31,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -252,7 +252,8 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 84a1e2e..c58492d 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -916,6 +916,7 @@ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_APM82XXX_RA 0x12C41C80 /* APM82XXX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/ppc440.h b/include/ppc440.h index c807dda..b559709 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -58,6 +58,25 @@ | Clocking Controller +----------------------------------------------------------------------------*/ /* values for clkcfga register - indirect addressing of these regs */ +#if defined(CONFIG_APM82XXX) +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 +#else #define CPR0_PLLC 0x0040 #define CPR0_PLLD 0x0060 #define CPR0_PRIMAD0 0x0080 @@ -67,6 +86,7 @@ #define CPR0_MALD 0x0100 #define CPR0_SPCID 0x0120 #define CPR0_ICFG 0x0140 +#endif /*if defined(CONFIG_APM82XXX) */ /* 440EPX boot strap options */ #define BOOT_STRAP_OPTION_A 0x00000000 @@ -1275,7 +1295,36 @@ #define SDR0_AHB_CFG 0x370 #define SDR0_USB2HOST_CFG 0x371 #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_APM82XXX) + +#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((u32)(n)) & 0x03) << 29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((u32)(n)) & 0x2FF) <<0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((u32)(n)) >> 0) & 0x2FF) + +#define SDR_SDSTP1_RL_DECODE(x) (((x) & 0x000C0000) >> 18) +#define SDR_SDSTP1_RL_EBC 0x0 +#define SDR_SDSTP1_RL_NDFC 0x2 + +/* ECID */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + +/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 +#define SDR0_AHB_CFG 0x370 + +/* DDR SDRAM Controller clock (CPR register)*/ +#define SDR0_DDRCE 0x00E0 /* SDR register */ +#define CPR0_DDR2D 0x0100 /* CPR register */ +#define CPR0_DDR2D_DDR2DV_ENCODE(n) ((((u32)(n)) & 0x03) << 25) +#define CPR0_DDR2D_DDR2DV_DECODE(n) ((((u32)(n)) >> 25) & 0x03) +#endif #define SDR0_SDCS_SDD (0x80000000 >> 31) #if defined(CONFIG_440GP) @@ -1517,7 +1566,8 @@ #define SDR0_EBC0 0x00000100 #define SDR0_SDSTP2 0x00004001 #define SDR0_SDSTP3 0x00004001 -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) #define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ @@ -1909,9 +1959,12 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) +#if !defined(CONFIG_APM82XXX) #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00) +#endif #define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_TCR (GPIO0_BASE+0x4) diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ee30a4c..3224d5f 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -44,14 +44,15 @@ #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) #define CONFIG_NAND_NDFC #endif @@ -61,7 +62,7 @@ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) #define PLB_ARBITER_BASE 0x80 -- 1.6.1.rc3

2 1

[U-Boot] [PATCH v1 2/2] APM82xxx: Add bluestone board support
by tmarri＠apm.com 01 Sep '10

01 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> Add support code for bluestone board wth APM82XXX processor based. This patch includes early board init, misc init, configure EBC, initializes UIC, MAKEALL, board.cfg and MAINTAINERS file. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- V1: * Remove "All rights reserved" phrase from headers. * Add empty line which was removed. * Move EBC definititions to bluestone_config.h file * Remove reconfigure_EBC() function. * Remove unused CONFIG_SDRAM16BIT_OFFSET. * Remove unused CONFIG_SDRAM_INFO_EEPROM_ADDR. * Add empty lines in bluestone.c file. * Replacing AC_R | AC_W | AC_X with AC_RWX. * Remove changes to main Makefile * Remove NAND references from config file. * Squash some of the patches. * Remove top Makefile change. --- MAINTAINERS | 3 + MAKEALL | 1 + board/amcc/bluestone/Makefile | 52 +++++++++++ board/amcc/bluestone/bluestone.c | 162 +++++++++++++++++++++++++++++++++++ board/amcc/bluestone/config.mk | 40 +++++++++ board/amcc/bluestone/init.S | 55 ++++++++++++ boards.cfg | 1 + include/configs/bluestone.h | 175 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 489 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..263c00b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -253,6 +253,9 @@ Feng Kan <fkan(a)amcc.com> redwood PPC4xx +Tirumala Marri<tmarri(a)apm.com> + bluestone APM82XXX + Brad Kemp <Brad.Kemp(a)seranoa.com> ppmc8260 MPC8260 diff --git a/MAKEALL b/MAKEALL index b34ae33..02d5c17 100755 --- a/MAKEALL +++ b/MAKEALL @@ -191,6 +191,7 @@ LIST_4xx=" \ ASH405 \ bamboo \ bamboo_nand \ + bluestone \ bubinga \ CANBT \ canyonlands \ diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile new file mode 100644 index 0000000..41751c8 --- /dev/null +++ b/board/amcc/bluestone/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri(a)apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +SOBJS := init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c new file mode 100644 index 0000000..fbb70e3 --- /dev/null +++ b/board/amcc/bluestone/bluestone.c @@ -0,0 +1,162 @@ +/* + * Bluestone board support + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc440.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SDR_AHB_CFG 0x370 + +/* Define Boot devices */ +#define BOOT_FROM_8BIT_SRAM 0x00 +#define BOOT_FROM_8BIT_SRAM_FULL_ADDR 0x01 +#define BOOT_FROM_8BIT_NAND 0x02 +#define BOOT_FROM_8BIT_NOR 0x03 +#define BOOT_FROM_8BIT_NOR_FULL_ADDR 0x04 +#define BOOT_DEVICE_UNKNOWN 0xff + +#define APM82161_MASK (u32)(0x1 << 21) + +/* + * Get bootdevice information and + * setup EBC configuration + * NOTE: Assume that I2C had been initialized + */ +int bootdevice_selected(void) +{ + unsigned long rl; + unsigned long bootstrap_settings; + int computed_boot_device = BOOT_DEVICE_UNKNOWN; + + mfsdr(SDR0_SDSTP1, bootstrap_settings); + rl = SDR_SDSTP1_RL_DECODE(bootstrap_settings); + if (rl == SDR_SDSTP1_RL_EBC) /* Boot device is NOR */ + computed_boot_device = BOOT_FROM_8BIT_NOR; + else if (rl == SDR_SDSTP1_RL_NDFC) + computed_boot_device = BOOT_FROM_8BIT_NAND; + return computed_boot_device; +} + +int board_early_init_f(void) +{ + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 2 pins + */ + mtsdr(SDR0_PFC1, 0x0000000); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Bluestone Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +int board_early_init_r(void) +{ + u32 bootdevice; + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + /* Reconfigure EBC here */ + bootdevice = bootdevice_selected(); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk new file mode 100644 index 0000000..13cd6c0 --- /dev/null +++ b/board/amcc/bluestone/config.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri(a)apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Applied Micro APM82XXX Evaluation board. +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S new file mode 100644 index 0000000..528de19 --- /dev/null +++ b/board/amcc/bluestone/init.S @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_RWX|SA_G) + + /* TLB-entry for OCM */ + tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, + AC_RWX|SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, + CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX|SA_IG) + tlbtab_end diff --git a/boards.cfg b/boards.cfg index 69c6897..48001d3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -196,6 +196,7 @@ redwood powerpc ppc4xx - amcc taihu powerpc ppc4xx - amcc taishan powerpc ppc4xx - amcc yucca powerpc ppc4xx - amcc +bluestone powerpc ppc4xx - amcc AP1000 powerpc ppc4xx ap1000 amirix CRAYL1 powerpc ppc4xx L1 cray ADCIOP powerpc ppc4xx adciop esd diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h new file mode 100644 index 0000000..8ee5f94 --- /dev/null +++ b/include/configs/bluestone.h @@ -0,0 +1,175 @@ +/* + * bluestone.h - configuration for Blouestone (APM82XXX) + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_APM82181 1 /* Specific APM82XXX */ +#define CONFIG_APM82XXX 1 /* APM82XXX series */ +#define CONFIG_HOSTNAME bluestone + +#define CONFIG_440 1 +#define CONFIG_4xx 1 /* ... PPC4xx family */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" +#define CONFIG_SYS_CLK_FREQ 50000000 + +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* EBC stuff */ +#define CONFIG_SYS_EXTSRAM_BASE 0xE1000000 /* 2MB */ +/* later mapped to this addr */ +#define CONFIG_SYS_FLASH_BASE 0xFFF00000 +#define CONFIG_SYS_FLASH_SIZE (1 << 20) /* 1MB usable */ + +/* EBC Boot Space: 0xFF000000 */ +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ + +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Environment + */ +/* + * Define here the location of the environment variables (FLASH). + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +/* Reduce the actual size of the flash */ +#define CONFIG_SIZE_REDUCE (3 << 20) +/* Reduce the actual sectors of the flash */ +#define CONFIG_SECTOR_REDUCE 48 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 80 +/* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +/* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 +/* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* NOR Flash */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(64) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(2) | \ + EBC_BXAP_WBN_ENCODE(2) | \ + EBC_BXAP_WBF_ENCODE(2) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +/* Peripheral Bank Configuration Register - EBC_BxCR */ +#define CONFIG_SYS_EBC_PB0CR \ + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT) + +/* SDRAM */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII +#define CONFIG_HAS_ETH0 +#define CONFIG_M88E1111_PHY +/* PHY address, See schematics */ +#define CONFIG_PHY_ADDR 0x1f +/* reset phy upon startup */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_R +/* Include GbE speed/duplex detection */ +#define CONFIG_PHY_GIGE 1 +#define CONFIG_PHY_DYNAMIC_ANEG 1 +/* + * External Bus Controller (EBC) Setup + **/ +#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */ + +#endif /* __CONFIG_H */ -- 1.6.1.rc3

2 1

[U-Boot] AT91: Hitachi LCD problem
by Chris Isbell 01 Sep '10

01 Sep '10

Hello, Our system is based on the AT91SAM9263 and has a Hitachi LCD screen in portrait mode. The U-Boot splash screen is not displaying correctly. The left hand half is correct, but the right hand half either flickers or breaks up completely into a pattern of vertical lines. The whole screen works correctly under Linux. The screen configuration appears to match other U-Boot configurations for this hardware. U-Boot - our board: vidinfo_t panel_info = { vl_col: 240, vl_row: 320, vl_clk: 4965000, vl_sync: ATMEL_LCDC_INVLINE_INVERTED | ATMEL_LCDC_INVFRAME_INVERTED, vl_bpix: 3, vl_tft: 1, vl_hsync_len: 5, vl_left_margin: 10, vl_right_margin:33, vl_vsync_len: 1, vl_upper_margin:8, vl_lower_margin:0, mmio: AT91SAM9263_LCDC_BASE, }; U_Boot board-at91sam9263ek: vidinfo_t panel_info = { vl_col: 240, vl_row: 320, vl_clk: 4965000, vl_sync: ATMEL_LCDC_INVLINE_INVERTED | ATMEL_LCDC_INVFRAME_INVERTED, vl_bpix: 3, vl_tft: 1, vl_hsync_len: 5, vl_left_margin: 1, vl_right_margin:33, vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, mmio: AT91SAM9263_LCDC_BASE, }; Linux - our hardware: /* Hitachi TX07D9VM1CAB - 2.4", 320x240 */ static struct fb_videomode at91_tft_vga_modes[] = { { .name = "TX07D9VM1CAB @ 60", .refresh = 60, .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), .left_margin = 10, .right_margin = 0, .upper_margin = 8, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1, .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .vmode = FB_VMODE_NONINTERLACED, }, }; Changing the settings for our board to be exactly the same as board-at91sam9263ek does not resolve the problem. Any clues as to where else to look would be very much appreciated. Thanks, -- Chris Isbell Systems Integration Manager, CDSRail Fareham, Hampshire, UK.

1 0

[U-Boot] [PATCH] support spi gpio driver by control gpio bitbang
by Donghwa Lee 01 Sep '10

01 Sep '10

This patch adds basic support for spi mode 0~3 by control gpio bitbang. It uses several gpio pin and emulates spi chipselect signal, clock signal and sda signal as if spi controller generate spi signal. Signed-off-by: Donghwa Lee <dh09.lee at samsung.com <http://lists.denx.de/mailman/listinfo/u-boot>> --- drivers/spi/spi_gpio.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++++ include/spi.h | 27 +++++++++ 2 files changed, 180 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi_gpio.c diff --git a/drivers/spi/spi_gpio.c b/drivers/spi/spi_gpio.c new file mode 100644 index 0000000..cce809e --- /dev/null +++ b/drivers/spi/spi_gpio.c @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * spi_gpio.c - SPI master driver using generic bitbanged GPIO + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <asm/arch/gpio.h> +#include <spi.h> + +static void spi_gpio_set_sck(struct spi_platform_data *spi, int is_on) +{ + gpio_set_value(spi->clk_bank, spi->clk_num, is_on); +} + +static void spi_gpio_set_mosi(struct spi_platform_data *spi, int is_on) +{ + gpio_set_value(spi->si_bank, spi->si_num, is_on); +} + +static void spi_gpio_chipselect(struct spi_platform_data *spi, + int cpol) +{ + gpio_set_value(spi->cs_bank, spi->cs_num, + !spi->cs_active); + + /* set initial clock polarity */ + if (cpol) + spi_gpio_set_sck(spi, spi->mode & SPI_CPOL); + + /* SPI is normally active-low */ + gpio_set_value(spi->cs_bank, spi->cs_num, + spi->cs_active); +} + +static void +spi_gpio_tx_cpha0(struct spi_platform_data *spi, + unsigned int nsecs, unsigned int cpol, + unsigned int word, unsigned int bits) +{ + int i; + unsigned int data; + + data = (word << spi->word_len) + bits; + + spi_gpio_chipselect(spi, cpol); + + /* clock starts at inactive polarity */ + for (i = spi->word_len; i >= 0; i--) { + + /* data high or low */ + if ((data >> i) & 0x1) + spi_gpio_set_mosi(spi, 1); + else + spi_gpio_set_mosi(spi, 0); + + udelay(nsecs); + + spi_gpio_set_sck(spi, !cpol); + udelay(nsecs); + + spi_gpio_set_sck(spi, cpol); + } +} + +static void +spi_gpio_tx_cpha1(struct spi_platform_data *spi, + unsigned int nsecs, unsigned int cpol, + unsigned int word, unsigned int bits) +{ + int i; + unsigned int data; + + data = (word << spi->word_len) + bits; + + spi_gpio_chipselect(spi, cpol); + + /* clock starts at inactive polarity */ + for (i = spi->word_len; i >= 0; i--) { + + /* setup MSB (to slave) on leading edge */ + spi_gpio_set_sck(spi, !cpol); + + /* data high or low */ + if ((data >> i) & 0x1) + spi_gpio_set_mosi(spi, 1); + else + spi_gpio_set_mosi(spi, 0); + + udelay(nsecs); + + spi_gpio_set_sck(spi, cpol); + udelay(nsecs); + } +} + +static void spi_gpio_tx_word_mode0(struct spi_platform_data *spi, + unsigned int nsecs, unsigned int word, unsigned int bits) +{ + return spi_gpio_tx_cpha0(spi, nsecs, 0, word, bits); +} + +static void spi_gpio_tx_word_mode1(struct spi_platform_data *spi, + unsigned int nsecs, unsigned int word, unsigned int bits) +{ + return spi_gpio_tx_cpha1(spi, nsecs, 0, word, bits); +} + +static void spi_gpio_tx_word_mode2(struct spi_platform_data *spi, + unsigned int nsecs, unsigned int word, unsigned int bits) +{ + return spi_gpio_tx_cpha0(spi, nsecs, 1, word, bits); +} + +static void spi_gpio_tx_word_mode3(struct spi_platform_data *spi, + unsigned int nsecs, unsigned int word, unsigned int bits) +{ + return spi_gpio_tx_cpha1(spi, nsecs, 1, word, bits); +} + +void spi_gpio_write(struct spi_platform_data *spi, + unsigned int address, unsigned int command) +{ + switch (spi->mode) { + case SPI_MODE_0: + spi_gpio_tx_word_mode0(spi, + 1, address, command); + case SPI_MODE_1: + spi_gpio_tx_word_mode1(spi, + 1, address, command); + case SPI_MODE_2: + spi_gpio_tx_word_mode2(spi, + 1, address, command); + case SPI_MODE_3: + spi_gpio_tx_word_mode3(spi, + 1, address, command); + } +} diff --git a/include/spi.h b/include/spi.h index 320e50e..ef3f94d 100644 --- a/include/spi.h +++ b/include/spi.h @@ -62,6 +62,33 @@ struct spi_slave { unsigned int cs; }; +#define COMMAND_ONLY 0xFE +#define DATA_ONLY 0xFF +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + + +struct spi_platform_data { + struct s5p_gpio_bank *cs_bank; + struct s5p_gpio_bank *clk_bank; + struct s5p_gpio_bank *si_bank; + struct s5p_gpio_bank *so_bank; + + unsigned int cs_num; + unsigned int clk_num; + unsigned int si_num; + unsigned int so_num; + + unsigned int mode; + unsigned int cs_active; + unsigned int word_len; + + unsigned int set_rev; +}; + +void spi_gpio_write(struct spi_platform_data *spi, + unsigned int address, unsigned int command); + /*----------------------------------------------------------------------- * Initialization, must be called once on start up. * -- 1.6.0.4

2 1

[U-Boot] [PATCH 8/8] APM82xxx: Add top level common file changes
by tmarri＠apm.com 01 Sep '10

01 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> Add bluestone board name to the board.cfg. Change Makefile to include bluestone board support. Modified MAINTAINERS file to include board maintainers name. Modified to include blouestone entry in the MAKEALL file. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- MAINTAINERS | 3 +++ MAKEALL | 1 + Makefile | 7 +++++++ boards.cfg | 1 + 4 files changed, 12 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..263c00b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -253,6 +253,9 @@ Feng Kan <fkan(a)amcc.com> redwood PPC4xx +Tirumala Marri<tmarri(a)apm.com> + bluestone APM82XXX + Brad Kemp <Brad.Kemp(a)seranoa.com> ppmc8260 MPC8260 diff --git a/MAKEALL b/MAKEALL index b34ae33..02d5c17 100755 --- a/MAKEALL +++ b/MAKEALL @@ -191,6 +191,7 @@ LIST_4xx=" \ ASH405 \ bamboo \ bamboo_nand \ + bluestone \ bubinga \ CANBT \ canyonlands \ diff --git a/Makefile b/Makefile index 4f1cb1b..8cd5bd3 100644 --- a/Makefile +++ b/Makefile @@ -926,6 +926,13 @@ bamboo_nand_config: unconfig @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk @$(MKCONFIG) -n $@ -a bamboo powerpc ppc4xx bamboo amcc +# Maui Bluestone board images +bluestone_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ + tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h + @$(MKCONFIG) -n $@ -a bluestone powerpc ppc4xx bluestone amcc + # Arches, Canyonlands & Glacier use different U-Boot images arches_config \ canyonlands_config \ diff --git a/boards.cfg b/boards.cfg index 69c6897..48001d3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -196,6 +196,7 @@ redwood powerpc ppc4xx - amcc taihu powerpc ppc4xx - amcc taishan powerpc ppc4xx - amcc yucca powerpc ppc4xx - amcc +bluestone powerpc ppc4xx - amcc AP1000 powerpc ppc4xx ap1000 amirix CRAYL1 powerpc ppc4xx L1 cray ADCIOP powerpc ppc4xx adciop esd -- 1.6.1.rc3

5 7

[U-Boot] Hi
by Vaishali Dhakate 01 Sep '10

01 Sep '10

Hi , I am trying to cross compile some libraries for ARM board I will port a Linux OS to the hawkboard. Want to study u-boot specific to this board so I ll be able to do this. The first chore is to port u-boot on this board. PLz help me , I was going through the uboot readme which directed me to straight away mail and share my concern. Thanks for the help Regards Vaishali

2 1

[U-Boot] "UnCorrectable RS-ECC Error" occurs when reading NAND flash under u-boot 2009.08 for i.mx25
by dajiang.zhong＠tektronix.com 01 Sep '10

01 Sep '10

Hi, every one. This is my first time of posting a message here, firstly , thanks for any body who builds such a nice platform give help. In recent two weeks, I added a NAND flash driver support for Micron's MT29F2G08ABD (SLC;page size: x8 2048+64bytes; Block size: 64 pages; Device size: 2Gb) memory chip base on u-boot 2009.08 for i.mx25. Block Erasing and Page Programming functions worked properly, but when I do page reading operation, "UnCorrectable RS-ECC Error" error message prompted. I checked the NFC (NAND Flash Controller) spare area buffer and found that the 4th 512-byte spare area buffer's data were very weird, there is not any ECC code that should be generated by the FEC but contained the data what I programmed to the memory. In order to easy to do troubleshooting works, I make a simply testing process, what I do is, firstly, I only erase page 0 of block 0, and later I program the erased page with a 2k file which consisted of 2048 same character 'E', at last I read the page back , but "UnCorrectable RS-ECC Error" occurs. I pasted the contents of NFC's spare area buffer as following: bb001000: ffffffff 66ffffff bab935d1 22446bbd .......f.5...kD" bb001010: b935d166 ffffffba ffffffff ffffffff f.5............. bb001020: 5f7467b9 21650de8 4d97fbd0 3166372c .gt_..e!...M,7f1 bb001030: 3b7e8bef b1cf62a5 bb8f50f6 de0031b3 ..~;.b...P...1.. bb001040: ffffffff 66ffffff bab935d1 22446bbd .......f.5...kD" bb001050: b935d166 ffffffba ffffffff ffffffff f.5............. bb001060: bafcf1fa 0c0698ef 09089d72 e6200c80 ........r..... . bb001070: d638f5ef 20130b40 591dd763 e224f527 ..8.@.. c..Y'.$. bb001080: ffffffff 66ffffff bab935d1 22446bbd .......f.5...kD" bb001090: b935d166 ffffffba ffffffff ffffffff f.5............. bb0010a0: 76fa88ba 7a648809 d27bbc43 6b2b81cf ...v..dzC.{...+k bb0010b0: f6b95e3b 1286638e 73d324fb 22880ce5 ;^...c...$.s..." bb0010c0: 45454545 45454545 45454545 45454545 EEEEEEEEEEEEEEEE bb0010d0: 45454545 45454545 45454545 45454545 EEEEEEEEEEEEEEEE bb0010e0: 36d8f3d5 0099a9e7 eb289d07 11664624 ...6......(.$Ff. bb0010f0: 4fbb9f24 505ab041 25ff61f6 43280406 $..OA.ZP.a.%..(C Contents written in red characters should be ECC code, but changed to what I programmed to the memory in preverious programming process. Any advice, please feel free to tell me. Thanks very much in advance. Thanks & Regards, Leon Zhong

3 3

[U-Boot] [PATCH 0/2] fix little endian build
by xiangfu＠openmobilefree.net 01 Sep '10

01 Sep '10

From: Xiangfu Liu <xiangfu(a)openmobilefree.net> those two patches fix the little endian build. done by Shinya Kuribayashi. Makefile | 1 + arch/mips/config.mk | 27 +++++++++++++++++++++++++-- arch/mips/cpu/config.mk | 8 -------- board/dbau1x00/u-boot.lds | 2 +- board/gth2/u-boot.lds | 2 +- board/incaip/u-boot.lds | 2 +- board/pb1x00/u-boot.lds | 2 +- board/purple/u-boot.lds | 2 +- board/qemu-mips/u-boot.lds | 2 +- examples/standalone/mips.lds | 2 +- include/configs/pb1x00.h | 2 ++ 11 files changed, 35 insertions(+), 17 deletions(-)

4 10

[U-Boot] [PATCH v1 0/2] Add support for new SoC APM82XXX
by tmarri＠apm.com 01 Sep '10

01 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> APM8XXXX is Applied Micro Circuits Corporations naming convention for new line of SoCs. V1: * Squash some of the patches. * add space between "||" and "\". * Add spaces around operators. * Unsigned int to u32. * Add empty line which was removed. * remove warning "unused variable" in cpu_init.c * Remove "All rights reserved" phrase from headers. * Add empty line which was removed. * Move EBC definititions to bluestone_config.h file * Remove reconfigure_EBC() function. * Remove unused CONFIG_SDRAM16BIT_OFFSET. * Remove unused CONFIG_SDRAM_INFO_EEPROM_ADDR. * Add empty lines in bluestone.c file. * Replacing AC_R | AC_W | AC_X with AC_RWX. * Remove changes to main Makefile * Remove NAND references from config file. * Squash some of the patches. * Remove top Makefile change. Tirumala Marri (2): Add CPU and other peripheral support APM82xxx: Add bluestone board support MAINTAINERS | 3 + MAKEALL | 1 + arch/powerpc/cpu/ppc4xx/cpu.c | 35 ++++++- arch/powerpc/cpu/ppc4xx/cpu_init.c | 8 +- arch/powerpc/cpu/ppc4xx/speed.c | 85 +++++++++++++++- arch/powerpc/cpu/ppc4xx/start.S | 10 ++- arch/powerpc/include/asm/ppc4xx-ebc.h | 4 + arch/powerpc/include/asm/ppc4xx-isram.h | 8 +- arch/powerpc/include/asm/ppc4xx-sdram.h | 25 ++++- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/processor.h | 1 + board/amcc/bluestone/Makefile | 52 +++++++++ board/amcc/bluestone/bluestone.c | 162 ++++++++++++++++++++++++++++ board/amcc/bluestone/config.mk | 40 +++++++ board/amcc/bluestone/init.S | 55 ++++++++++ boards.cfg | 1 + include/configs/bluestone.h | 175 +++++++++++++++++++++++++++++++ include/ppc440.h | 57 ++++++++++- include/ppc4xx.h | 7 +- 19 files changed, 709 insertions(+), 25 deletions(-) create mode 100644 board/amcc/bluestone/Makefile create mode 100644 board/amcc/bluestone/bluestone.c create mode 100644 board/amcc/bluestone/config.mk create mode 100644 board/amcc/bluestone/init.S create mode 100644 include/configs/bluestone.h

1 0