September 2010 - U-Boot

[U-Boot] [PATCH] AT91/AVR32: atmel_spi.c: flush RDR before next SPI transaction
by Reinhard Meyer 03 Sep '10

03 Sep '10

From: Reinhard Meyer <info(a)emk-elektronik.de> Signed-off-by: Reinhard Meyer <u-boot(a)emk-elektronik.de> --- drivers/spi/atmel_spi.c | 13 +++++++++++-- 1 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 317c0b4..d0de931 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -43,7 +43,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, u32 csrx; void *regs; - if (cs > 3 || !spi_cs_is_valid(bus, cs)) + if (!spi_cs_is_valid(bus, cs)) return NULL; switch (bus) { @@ -168,8 +168,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, * somewhat quirky, and it doesn't really buy us much anyway * in the context of U-Boot. */ - if (flags & SPI_XFER_BEGIN) + if (flags & SPI_XFER_BEGIN) { spi_cs_activate(slave); + /* + * sometimes the RDR is not empty when we get here, + * in theory that should not happen, but it DOES happen. + * Read it here to be on the safe side. + * That also clears the OVRES flag. Required if the + * following loop exits due to OVRES! + */ + spi_readl(as, RDR); + } for (len_tx = 0, len_rx = 0; len_rx < len; ) { status = spi_readl(as, SR); -- 1.5.6.5

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[U-Boot] [PATCH] ppc4xx: Invalidate d-cache when used as init-ram
by Stefan Roese 03 Sep '10

03 Sep '10

We need to invalidate the data cache after it has been used as init-ram. This problem was detected on the lwmon5 update. Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/powerpc/cpu/ppc4xx/start.S | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad..4bad32f 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1459,6 +1459,11 @@ relocate_code: mtspr SPRN_DTV3,r6 msync isync + + /* Invalidate data cache, now no longer our stack */ + dccci 0,0 + sync + isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ /* -- 1.7.2.2

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[U-Boot] [PATCH] ppc4xx: Fix 440EPx bug in reconfigure_pll()
by Stefan Roese 03 Sep '10

03 Sep '10

This patch fixes a bug in reconfigure_pll(), where the detection of the current bootstrap option is wrong. The ICS bits where incorrectly shifted. This bug was found on the lwmon5 board, which uses bootstrap option H (I2C bootstrap EEPROM). Additionally a bit of code was moved into the if statement, since its only used after later on. No need to run this code all the time. Also, a few empty lines are added to make the code better readable. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Rupjyoti Sarmah <rsarmah(a)amcc.com> Cc: Victor Gallardo <vgallardo(a)appliedmicro.com> --- arch/powerpc/cpu/ppc4xx/cpu_init.c | 27 ++++++++++++++++++--------- include/ppc440.h | 1 + 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..b31bd0b 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq) * modify it. */ if (temp == 1) { - mfcpr(CPR0_PLLD, reg); - /* Get current value of fbdv. */ - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - /* Get current value of lfbdv. */ - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; /* * Load register that contains current boot strapping option. */ mfcpr(CPR0_ICFG, reg); - /* Shift strapping option into low 3 bits.*/ - reg = (reg >> 28); + /* + * Strapping option bits (ICS) are already in correct position, + * only masking needed. + */ + reg &= CPR0_ICFG_ICS_MASK; if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { + mfcpr(CPR0_PLLD, reg); + + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + /* * Get current value of FWDVA. Assign current FWDVA to * new FWDVB. @@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq) mfcpr(CPR0_PLLD, reg); target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; fwdvb = target_fwdvb ? target_fwdvb : 8; + /* * Get current value of FWDVB. Assign current FWDVB to * new FWDVA. */ target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; fwdva = target_fwdva ? target_fwdva : 16; + /* * Update CPR0_PLLD with switched FWDVA and FWDVB. */ @@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq) ((fbdv == 32 ? 0 : fbdv) << 24) | (lfbdv == 64 ? 0 : lfbdv); mtcpr(CPR0_PLLD, reg); + /* Acknowledge that a reset is required. */ reset_needed = 1; } diff --git a/include/ppc440.h b/include/ppc440.h index c807dda..6727753 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1711,6 +1711,7 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_ICFG_ICS_MASK 0x00000007 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 #define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 #define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 -- 1.7.2.2

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[U-Boot] [PATCH] ppc4xx: Fix APC405 board support
by Matthias Fuchs 03 Sep '10

03 Sep '10

Opps, after a long time I tested recent u-boot on our APC405 board. This simple fix makes networking work again. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- include/configs/APC405.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 20849bc..a7724ad 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -104,6 +104,7 @@ #define CONFIG_NET_MULTI 1 #undef CONFIG_HAS_ETH1 +#define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 -- 1.6.1

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[U-Boot] [PATCH] AT91: reset.c: fix comments, add option
by Reinhard Meyer 03 Sep '10

03 Sep '10

- The comment was wrong/misleading - One would assume that a u-boot "reset" command should also reset the external hardware outside the SoC. Since its unknown whether some boards rely on that NOT being so, asserting the external reset signal is optional Signed-off-by: Reinhard Meyer <u-boot(a)emk-elektronik.de> --- arch/arm/cpu/arm926ejs/at91/reset.c | 17 ++++++++--------- 1 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index 1b67e77..22f3277 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -27,18 +27,17 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/io.h> -/* - * Reset the cpu by setting up the watchdog timer and let him time out. - */ +/* Reset the cpu by telling the reset controller to do so */ void reset_cpu(ulong ignored) { at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; - /* this is the way Linux does it */ - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST, - &rstc->cr); - + writel(AT91_RSTC_KEY + | AT91_RSTC_CR_PROCRST /* Processor Reset */ + | AT91_RSTC_CR_PERRST /* Peripheral Reset */ +#ifdef CONFIG_AT91RESET_EXTRST + | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */ +#endif + , &rstc->cr); while (1); - /* Never reached */ } -- 1.5.6.5

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[U-Boot] [PATCH v3] AT91: fix at91sam9260.h for AT91SAM9XE
by Reinhard Meyer 03 Sep '10

03 Sep '10

Define the different location of the GPBRs for the 9XE Define the proper CPU Name Signed-off-by: Reinhard Meyer <u-boot(a)emk-elektronik.de> --- arch/arm/include/asm/arch-at91/at91sam9260.h | 18 ++++++++++++++---- 1 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index ec04318..cb34a94 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -59,7 +59,15 @@ #define AT91_RTT_BASE 0xfffffd20 #define AT91_PIT_BASE 0xfffffd30 #define AT91_WDT_BASE 0xfffffd40 -#define AT91_GPR_BASE 0xfffffd50 +/* + * The AT91SAM9XE has the GPBRs at a different address than + * the AT91SAM9260/9G20. + */ +#ifdef CONFIG_AT91SAM9XE +# define AT91_GPR_BASE 0xfffffd60 +#else +# define AT91_GPR_BASE 0xfffffd50 +#endif #ifdef CONFIG_AT91_LEGACY @@ -140,10 +148,12 @@ /* * Cpu Name */ -#if defined(CONFIG_AT91SAM9260) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" +#if defined(CONFIG_AT91SAM9XE) +# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9XE" +#elif defined(CONFIG_AT91SAM9260) +# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" #elif defined(CONFIG_AT91SAM9G20) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" +# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" #endif #endif -- 1.5.6.5

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[U-Boot] [PATCH v3] AT91SAM9XE: add embedded flash support
by Reinhard Meyer 03 Sep '10

03 Sep '10

Add support for the embedded flash in the AT91SAM9XE128/256/512 SoCs: - Environment can be put into that flash - U-Boot can be in that flash - Commands "cp" and "protect" are supported Signed-off-by: Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> --- Rebased and cosmetical cleanups arch/arm/cpu/arm926ejs/at91/Makefile | 1 + arch/arm/cpu/arm926ejs/at91/eflash.c | 271 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-at91/at91_dbu.h | 41 +++++ arch/arm/include/asm/arch-at91/at91_eefc.h | 51 ++++++ 4 files changed, 364 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/at91/eflash.c create mode 100644 arch/arm/include/asm/arch-at91/at91_dbu.h create mode 100644 arch/arm/include/asm/arch-at91/at91_eefc.h diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index 4f467be..def3980 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o +COBJS-$(CONFIG_AT91_EFLASH) += eflash.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o COBJS-y += cpu.o diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c new file mode 100644 index 0000000..2e851db --- /dev/null +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -0,0 +1,271 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer(a)emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * this driver supports the enhanced embedded flash in the Atmel + * AT91SAM9XE devices with the following geometry: + * + * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages) + * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages) + * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages) + * (the exact geometry is read from the flash at runtime, so any + * future devices should already be covered) + * + * Regions can be write/erase protected. + * Whole (!) pages can be individually written with erase on the fly. + * Writing partial pages will corrupt the rest of the page. + * + * The flash is presented to u-boot with each region being a sector, + * having the following effects: + * Each sector can be hardware protected (protect on/off). + * Each page in a sector can be rewritten anytime. + * Since pages are erased when written, the "erase" does nothing. + * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected + * by u-Boot commands. + * + * Note: Redundant environment will not work in this flash since + * it does use partial page writes. Make sure the environent spans + * whole pages! + */ + +/* + * optional TODOs (nice to have features): + * + * make the driver coexist with other NOR flash drivers + * (use an index into flash_info[], requires work + * in those other drivers, too) + * Make the erase command fill the sectors with 0xff + * (if the flashes grow larger in the future and + * someone puts a jffs2 into them) + * do a read-modify-write for partially programmed pages + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_eefc.h> +#include <asm/arch/at91_dbu.h> + +/* checks to detect configuration errors */ +#if CONFIG_SYS_MAX_FLASH_BANKS!=1 +#error eflash: this driver can only handle 1 bank +#endif + +/* global structure */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static u32 pagesize; + +unsigned long flash_init (void) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + at91_dbu_t *dbu = (at91_dbu_t *) 0xfffff200; + u32 id, size, nplanes, planesize, nlocks; + u32 addr, i, tmp=0; + + debug("eflash: init\n"); + + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* check if its an AT91ARM9XE SoC */ + if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { + puts("eflash: not an AT91SAM9XE\n"); + return 0; + } + + /* now query the eflash for its structure */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + id = readl(&eefc->frr); /* word 0 */ + size = readl(&eefc->frr); /* word 1 */ + pagesize = readl(&eefc->frr); /* word 2 */ + nplanes = readl(&eefc->frr); /* word 3 */ + planesize = readl(&eefc->frr); /* word 4 */ + debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n", + id, size, pagesize, nplanes, planesize); + for (i=1; i<nplanes; i++) { + tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */ + }; + nlocks = readl(&eefc->frr); /* word 4+nplanes */ + debug("nlocks=%u\n", nlocks); + /* since we are going to use the lock regions as sectors, check count */ + if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) { + printf("eflash: number of lock regions(%u) "\ + "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n", + nlocks); + nlocks = CONFIG_SYS_MAX_FLASH_SECT; + } + flash_info[0].size = size; + flash_info[0].sector_count = nlocks; + flash_info[0].flash_id = id; + + addr = AT91SAM9XE_FLASH_BASE; + for (i=0; i<nlocks; i++) { + tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */ + flash_info[0].start[i] = addr; + flash_info[0].protect[i] = 0; + addr += tmp; + }; + + /* now read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; i<flash_info[0].sector_count; i++) { + if (i%32 == 0) + tmp = readl(&eefc->frr); + flash_info[0].protect[i] = (tmp >> (i%32)) & 1; +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (i < CONFIG_EFLASH_PROTSECTORS) + flash_info[0].protect[i] = 1; +#endif + } + + return size; +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + puts("AT91SAM9XE embedded flash\n Size: "); + print_size(info->size, " in "); + printf("%d Sectors\n", info->sector_count); + + printf(" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +int flash_real_protect (flash_info_t *info, long sector, int prot) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + u32 pagenum = (info->start[sector]-AT91SAM9XE_FLASH_BASE)/pagesize; + u32 i, tmp=0; + + debug("protect sector=%ld prot=%d\n", sector, prot); + +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (sector < CONFIG_EFLASH_PROTSECTORS) { + if (!prot) { + printf("eflash: sector %lu cannot be unprotected\n", + sector); + } + return 1; /* return anyway, caller does not care for result */ + } +#endif + if (prot) { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } else { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* now re-read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; i<info->sector_count; i++) { + if (i%32 == 0) + tmp = readl(&eefc->frr); + info->protect[i] = (tmp >> (i%32)) & 1; + } + return 0; +} + +static u32 erase_write_page (u32 pagenum) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + + debug("erase+write page=%u\n", pagenum); + + /* give erase and write page command */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* return status */ + return readl(&eefc->fsr) + & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE); +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + debug("erase first=%d last=%d\n", s_first, s_last); + puts("this flash does not need and support erasing!\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + u32 pagenum; + u32 *src32, *dst32; + u32 i; + + debug("write src=%08lx addr=%08lx cnt=%lx\n", + (ulong)src, addr, cnt); + + /* REQUIRE addr to be on a page start, abort if not */ + if (addr % pagesize) { + printf ("eflash: start %08lx is not on page start\n"\ + " write aborted\n", addr); + return 1; + } + + /* now start copying data */ + pagenum = (addr-AT91SAM9XE_FLASH_BASE)/pagesize; + src32 = (u32 *) src; + dst32 = (u32 *) addr; + while (cnt > 0) { + i = pagesize / 4; + /* fill page buffer */ + while (i--) + *dst32++ = *src32++; + /* write page */ + if (erase_write_page(pagenum)) + return 1; + pagenum++; + if (cnt > pagesize) + cnt -= pagesize; + else + cnt = 0; + } + return 0; +} + diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h new file mode 100644 index 0000000..3429293 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_dbu.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer(a)emk-elektronik.de + * + * Debug Unit + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_DBU_H +#define AT91_DBU_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_dbu { + u32 cr; /* Control Register WO */ + u32 mr; /* Mode Register RW */ + u32 ier; /* Interrupt Enable Register WO */ + u32 idr; /* Interrupt Disable Register WO */ + u32 imr; /* Interrupt Mask Register RO */ + u32 sr; /* Status Register RO */ + u32 rhr; /* Receive Holding Register RO */ + u32 thr; /* Transmit Holding Register WO */ + u32 brgr; /* Baud Rate Generator Register RW */ + u32 res1[7];/* 0x0024 - 0x003C Reserved */ + u32 cidr; /* Chip ID Register RO */ + u32 exid; /* Chip ID Extension Register RO */ + u32 fnr; /* Force NTRST Register RW */ +} at91_dbu_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_DBU_CID_ARCH_MASK 0x0ff00000 +#define AT91_DBU_CID_ARCH_9xx 0x01900000 +#define AT91_DBU_CID_ARCH_9XExx 0x02900000 + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/include/asm/arch-at91/at91_eefc.h new file mode 100644 index 0000000..d45b3de --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_eefc.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer(a)emk-elektronik.de + * + * Enhanced Embedded Flash Controller + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_EEFC_H +#define AT91_EEFC_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_eefc { + u32 fmr; /* Flash Mode Register RW */ + u32 fcr; /* Flash Command Register WO */ + u32 fsr; /* Flash Status Register RO */ + u32 frr; /* Flash Result Register RO */ +} at91_eefc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_EEFC_FMR_FWS_MASK 0x00000f00 +#define AT91_EEFC_FMR_FRDY_BIT 0x00000001 + +#define AT91_EEFC_FCR_KEY 0x5a000000 +#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 +#define AT91_EEFC_FCR_FARG_SHIFT 8 +#define AT91_EEFC_FCR_FCMD_GETD 0x0 +#define AT91_EEFC_FCR_FCMD_WP 0x1 +#define AT91_EEFC_FCR_FCMD_WPL 0x2 +#define AT91_EEFC_FCR_FCMD_EWP 0x3 +#define AT91_EEFC_FCR_FCMD_EWPL 0x4 +#define AT91_EEFC_FCR_FCMD_EA 0x5 +#define AT91_EEFC_FCR_FCMD_SLB 0x8 +#define AT91_EEFC_FCR_FCMD_CLB 0x9 +#define AT91_EEFC_FCR_FCMD_GLB 0xA +#define AT91_EEFC_FCR_FCMD_SGPB 0xB +#define AT91_EEFC_FCR_FCMD_CGPB 0xC +#define AT91_EEFC_FCR_FCMD_GGPB 0xD + +#define AT91_EEFC_FSR_FRDY 1 +#define AT91_EEFC_FSR_FCMDE 2 +#define AT91_EEFC_FSR_FLOCKE 4 + +#endif -- 1.5.6.5

1 1

[U-Boot] [PATCH v4] AT91: add RTT and GPBR based RTC
by Reinhard Meyer 03 Sep '10

03 Sep '10

From: Reinhard Meyer <info(a)emk-elektronik.de> Signed-off-by: Reinhard Meyer <u-boot(a)emk-elektronik.de> --- arch/arm/include/asm/arch-at91/at91_gpbr.h | 45 +++++++++++++ arch/arm/include/asm/arch-at91/at91_rtt.h | 36 ++++++++++ drivers/rtc/Makefile | 1 + drivers/rtc/at91sam9_rtt.c | 100 ++++++++++++++++++++++++++++ 4 files changed, 182 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-at91/at91_gpbr.h create mode 100644 arch/arm/include/asm/arch-at91/at91_rtt.h create mode 100644 drivers/rtc/at91sam9_rtt.c diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h b/arch/arm/include/asm/arch-at91/at91_gpbr.h new file mode 100644 index 0000000..cf1d790 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_gpbr.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer(a)emk-elektronik.de + * + * General Purpose Backup Registers + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_GPBR_H +#define AT91_GPBR_H + +/* + * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile + * 32 Bit registers (buffered by the Vbu power). + * + * Please consider carefully before using this resource for tasks + * that do not really need nonvolatile registers. Maybe you can + * store information in EEPROM or FLASH instead. + * + * However, if you use a GPBR please document its use here and + * reference the define in your code! + * + * known typical uses of the GPBRs: + * GPBR[0]: offset for RTT timekeeping (u-boot, kernel) + * GPBR[1]: unused + * GPBR[2]: unused + * GPBR[3]: bootcount (u-boot) + */ +#define AT91_GPBR_INDEX_TIMEOFF 0 +#define AT91_GPBR_INDEX_BOOTCOUNT 3 + +#ifndef __ASSEMBLY__ + +typedef struct at91_gpbr { + u32 reg[4]; +} at91_gpbr_t; + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h b/arch/arm/include/asm/arch-at91/at91_rtt.h new file mode 100644 index 0000000..e0253ef --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_rtt.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer(a)emk-elektronik.de + * + * Real-time Timer + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_RTT_H +#define AT91_RTT_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_rtt { + u32 mr; /* Mode Register RW 0x00008000 */ + u32 ar; /* Alarm Register RW 0xFFFFFFFF */ + u32 vr; /* Value Register RO 0x00000000 */ + u32 sr; /* Status Register RO 0x00000000 */ +} at91_rtt_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_RTT_MR_RTPRES 0x0000ffff +#define AT91_RTT_MR_ALMIEN 0x00010000 +#define AT91_RTT_RTTINCIEN 0x00020000 +#define AT91_RTT_RTTRST 0x00040000 + +#define AT91_RTT_SR_ALMS 0x00000001 +#define AT91_RTT_SR_RTTINC 0x00000002 + +#endif diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 772a49a..98734db 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)librtc.a +COBJS-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o COBJS-$(CONFIG_RTC_BFIN) += bfin_rtc.o COBJS-y += date.o COBJS-$(CONFIG_RTC_DS12887) += ds12887.o diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c new file mode 100644 index 0000000..de8e30d --- /dev/null +++ b/drivers/rtc/at91sam9_rtt.c @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, reinhard.meyer(a)emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the internal Real-time Timer + * of AT91SAM9260 and compatibles. + * Compatible with the LinuX rtc driver workaround: + * The RTT cannot be written to, but only reset. + * The actual time is the sum of RTT and one of + * the four GPBR registers. + * + * The at91sam9260 has 4 GPBR (0-3). + * For their typical use see at91_gpbr.h ! + * + * make sure u-boot and kernel use the same GPBR ! + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <asm/errno.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_rtt.h> +#include <asm/arch/at91_gpbr.h> + +#if defined(CONFIG_CMD_DATE) + +int rtc_get (struct rtc_time *tmp) +{ + at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + ulong tim; + ulong tim2; + ulong off; + + do { + tim = readl(&rtt->vr); + tim2 = readl(&rtt->vr); + } while (tim!=tim2); + off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); + /* off==0 means time is invalid, but we ignore that */ + to_tm (tim+off, tmp); + return 0; +} + +int rtc_set (struct rtc_time *tmp) +{ + at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + ulong tim; + + tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* clear alarm, set prescaler to 32768, clear counter */ + writel(32768+AT91_RTT_RTTRST, &rtt->mr); + writel(~0, &rtt->ar); + writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); + /* wait for counter clear to happen, takes less than a 1/32768th second */ + while (readl(&rtt->vr) != 0) + ; + return 0; +} + +void rtc_reset (void) +{ + at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + + /* clear alarm, set prescaler to 32768, clear counter */ + writel(32768+AT91_RTT_RTTRST, &rtt->mr); + writel(~0, &rtt->ar); + writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); + /* wait for counter clear to happen, takes less than a 1/32768th second */ + while (readl(&rtt->vr) != 0) + ; +} + +#endif -- 1.5.6.5

1 1

[U-Boot] [PATCH] AT91SAM9260/9XE: add support for MultiMedia Card Interface (MCI)
by Reinhard Meyer (-VC) 03 Sep '10

03 Sep '10

This patch adds support for the Atmel MultiMedia Card Interface (MCI) in AT91SAM9260 and AT91SAM9XE SoCs and preserves the original support for the AVR32AP700x SoCs. It patches the original atmel_mci.c driver to remove byte order and toolchain dependencies and makes it a common MCI driver for Atmels AVR32AP7000 and AT91SAM9260 based SoCs. The driver itself is not specific to those SoCs and should work with other Atmel devices having an identical MultiMedia Card Interface (MCI), provided the functions get_mci_clk_rate() and <SoC>_mci_hw_init() are defined. Tested on AT91SAM9XE-EK (AT91SAM9XE512) Tested on ATNGW100 (AVR32AP7000) Signed-off-by: Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> --- arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 20 ++++ arch/arm/include/asm/arch-at91/clk.h | 5 + arch/arm/include/asm/arch-at91/hardware.h | 1 + doc/README.atmel_mci | 68 +++++++++++++ drivers/mmc/atmel_mci.c | 112 ++++++++++----------- drivers/mmc/atmel_mci.h | 6 +- include/mmc.h | 93 ++++++++++------- 7 files changed, 207 insertions(+), 98 deletions(-) create mode 100644 doc/README.atmel_mci diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index 77d49ab..9cef832 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -194,3 +194,23 @@ void at91_macb_hw_init(void) #endif } #endif + +#ifdef CONFIG_ATMEL_MCI +void at91_mci_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* MCCK */ +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* MCCDB */ + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* MCDB0 */ + at91_set_b_periph(AT91_PIO_PORTA, 5, 0); /* MCDB1 */ + at91_set_b_periph(AT91_PIO_PORTA, 4, 0); /* MCDB2 */ + at91_set_b_periph(AT91_PIO_PORTA, 3, 0); /* MCDB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* MCDA3 */ +#endif +} +#endif diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h index f642dd9..457e6c9 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/include/asm/arch-at91/clk.h @@ -59,5 +59,10 @@ static inline unsigned long get_twi_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_mck_clk_rate(); +} + int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index 4ddb315..224b285 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -23,6 +23,7 @@ #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP +#define MMCI_BASE AT91SAM9260_BASE_MCI #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) #include <asm/arch/at91sam9261.h> #define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci new file mode 100644 index 0000000..15b3cc0 --- /dev/null +++ b/doc/README.atmel_mci @@ -0,0 +1,68 @@ +How to use SD/MMC cards with Atmel SoCs having MCI hardware +----------------------------------------------------------- +2010-07-04 Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> + +The drivers/mmc/atmel_mci.c file which originally worked only +with the AVR32 architecture SoCs like AVR32AP700x has been +updated to also work with the AT91SAM9260 compatible architectures: + +- AT91SAM9XE512 (tested, will definitely work with XE128 and XE256) +- AT91SAM9260 (not tested, but MCI is to AT91SAM9XE) +- AT91SAM9G20 (not tested, should work) + +It should work with all other AT91SAM9<xxx> devices that have MCI +provided that a correct version of the following function is added +to their specific XXX_devices file: + +(this example is from at91sam9260_devices.c) + +#ifdef CONFIG_ATMEL_MCI +void at91_mci_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* MCCK */ +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* MCCDB */ + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* MCDB0 */ + at91_set_b_periph(AT91_PIO_PORTA, 5, 0); /* MCDB1 */ + at91_set_b_periph(AT91_PIO_PORTA, 4, 0); /* MCDB2 */ + at91_set_b_periph(AT91_PIO_PORTA, 3, 0); /* MCDB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* MCDA3 */ +#endif + +the board specific files need added: + +#ifdef CONFIG_ATMEL_MCI +static void mci_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + + at91_mci_hw_init(); +} +#endif + +int board_init(void) +{ + ... +#ifdef CONFIG_ATMEL_MCI + mci_hw_init(); +#endif + ... + return 0; +} + +and the board definition files needs: +/* for the driver itself */ +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 +#define CONFIG_ATMEL_MCI_PORTB 1 /* to use port B, undefine for port A */ +/* to use the cards */ +#define CONFIG_CMD_EXT2 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_MMC 1 + diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c index 3946ffe..9dfec68 100644 --- a/drivers/mmc/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2004-2006 Atmel Corporation - * + * Copyright (C) 2010 EMK Elektronik <reinhard.meyer(a)emk-elektronik.de> * See file CREDITS for list of people who contributed to this * project. * @@ -19,6 +19,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +/* + * Notes: + * - modified to work with AVR32 and ARM9 + * - this driver handles cards in 1 bit bus width only, + * which is enough to load a kernel or similiar file + */ #include <common.h> #include <part.h> @@ -70,13 +76,13 @@ static void mci_set_mode(unsigned long hz, unsigned long blklen) bus_hz = get_mci_clk_rate(); clkdiv = (bus_hz / hz) / 2 - 1; - pr_debug("mmc: setting clock %lu Hz, block size %lu\n", - hz, blklen); + pr_debug("mmc: bus_hz is %lu, setting clock %lu Hz, block size %lu\n", + bus_hz, hz, blklen); if (clkdiv & ~255UL) { clkdiv = 255; - printf("mmc: clock %lu too low; setting CLKDIV to 255\n", - hz); + printf("mmc: requested clock %lu is too low; changed to %lu\n", + hz, (bus_hz / (clkdiv+1)) / 2); } blklen &= 0xfffc; @@ -84,6 +90,10 @@ static void mci_set_mode(unsigned long hz, unsigned long blklen) | MMCI_BF(BLKLEN, blklen) | MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF))); +#if defined(CONFIG_ATMEL_MCI_PORTB) + mmci_writel(SDCR, (MMCI_BF(SCDSEL, 1) + | MMCI_BF(SCDBUS, 0))); +#endif } #define RESP_NO_CRC 1 @@ -203,7 +213,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); if (ret) goto out; - pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + pr_debug("MCI_DTOR = %08x\n", mmci_readl(DTOR)); for (i = 0; i < blkcnt; i++, start++) { ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, @@ -229,13 +239,14 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, } } while(wordcount < (mmc_blkdev.blksz / 4)); - pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); + pr_debug("mmc: read %lu words, waiting for BLKE\n", wordcount); do { status = mmci_readl(SR); } while (!(status & MMCI_BIT(BLKE))); - +#if DEBUG putc('.'); +#endif } out: @@ -294,39 +305,26 @@ static void mmc_dump_cid(const struct mmc_cid *cid) cid->mdt >> 4, cid->mdt & 0x0f); } -static void mmc_dump_csd(const struct mmc_csd *csd) +static void mmc_parse_csd(struct mmc_csd *csd, int verbose) { - unsigned long *csd_raw = (unsigned long *)csd; - printf("CSD data: %08lx %08lx %08lx %08lx\n", - csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); - printf("CSD structure version: 1.%u\n", csd->csd_structure); - printf("MMC System Spec version: %u\n", csd->spec_vers); - printf("Card command classes: %03x\n", csd->ccc); - printf("Read block length: %u\n", 1 << csd->read_bl_len); - if (csd->read_bl_partial) - puts("Supports partial reads\n"); - else - puts("Does not support partial reads\n"); - printf("Write block length: %u\n", 1 << csd->write_bl_len); - if (csd->write_bl_partial) - puts("Supports partial writes\n"); - else - puts("Does not support partial writes\n"); - if (csd->wp_grp_enable) - printf("Supports group WP: %u\n", csd->wp_grp_size + 1); - else - puts("Does not support group WP\n"); - printf("Card capacity: %u bytes\n", - (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) * - (1 << csd->read_bl_len)); - printf("File format: %u/%u\n", - csd->file_format_grp, csd->file_format); - puts("Write protection: "); - if (csd->perm_write_protect) - puts(" permanent"); - if (csd->tmp_write_protect) - puts(" temporary"); - putc('\n'); + csd->taac = (csd->raw[0] >> 16) & 0xff; + csd->nsac = (csd->raw[0] >> 8) & 0xff; + csd->read_bl_len = (csd->raw[1] >> 16) & 0x0f; + csd->read_bl_partial = (csd->raw[1] >> 15) & 0x01; + csd->c_size = ((csd->raw[1] << 2) & 0x0ffc) | ((csd->raw[2] >> 30) & 0x03); + csd->c_size_mult = (csd->raw[2] >> 15) & 0x07; + csd->blocks = (csd->c_size+1) * (1 << (csd->c_size_mult+2)); + csd->blocksize = 1 << csd->read_bl_len; + + if (verbose) { + printf("raw CSD data: %08x %08x %08x %08x\n", + csd->raw[0], csd->raw[1], csd->raw[2], csd->raw[3]); + printf("Read block length: %u\n", 1 << csd->read_bl_len); + if (csd->read_bl_partial) + puts(" (Supports partial reads)\n"); + printf("Card capacity: %u Mbytes\n", + (csd->blocks>>12) * (csd->blocksize>>8)); + } } static int mmc_idle_cards(void) @@ -409,7 +407,7 @@ static int mmc_init_card(struct mmc_cid *cid, int verbose) return ret; } -static void mci_set_data_timeout(struct mmc_csd *csd) +static void mci_set_data_timeout(const struct mmc_csd *csd) { static const unsigned int dtomul_to_shift[] = { 0, 4, 7, 8, 10, 12, 16, 20, @@ -467,7 +465,6 @@ int mmc_legacy_init(int verbose) { struct mmc_cid cid; struct mmc_csd csd; - unsigned int max_blksz; int ret; /* Initialize controller */ @@ -491,8 +488,7 @@ int mmc_legacy_init(int verbose) ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR); if (ret) return ret; - if (verbose) - mmc_dump_csd(&csd); + mmc_parse_csd(&csd, verbose); mci_set_data_timeout(&csd); @@ -508,26 +504,28 @@ int mmc_legacy_init(int verbose) sprintf((char *)mmc_blkdev.revision, "%x %x", cid.prv >> 4, cid.prv & 0x0f); - /* - * If we can't use 512 byte blocks, refuse to deal with the - * card. Tons of code elsewhere seems to depend on this. - */ - max_blksz = 1 << csd.read_bl_len; - if (max_blksz < 512 || (max_blksz > 512 && !csd.read_bl_partial)) { + mmc_blkdev.blksz = csd.blocksize; + mmc_blkdev.lba = csd.blocks; + + /* if the card supports partial reads, decrease the block size to 512 */ + while (mmc_blkdev.blksz > 512 && csd.read_bl_partial) { + mmc_blkdev.blksz >>= 1; + mmc_blkdev.lba <<= 1; + } + if (mmc_blkdev.blksz != csd.blocksize) { + printf ("mmc: blocksize reduced to %u, number of blocks: %u\n", + mmc_blkdev.blksz, mmc_blkdev.lba); + } + + /* fail if blocksize != 512 */ + if (mmc_blkdev.blksz != 512) { printf("Card does not support 512 byte reads, aborting.\n"); return -ENODEV; } - mmc_blkdev.blksz = 512; - mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); mci_set_mode(CONFIG_SYS_MMC_CLK_PP, mmc_blkdev.blksz); -#if 0 - if (fat_register_device(&mmc_blkdev, 1)) - printf("Could not register MMC fat device\n"); -#else init_part(&mmc_blkdev); -#endif return 0; } diff --git a/drivers/mmc/atmel_mci.h b/drivers/mmc/atmel_mci.h index 5b4f5c9..8632cb4 100644 --- a/drivers/mmc/atmel_mci.h +++ b/drivers/mmc/atmel_mci.h @@ -19,8 +19,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __CPU_AT32AP_ATMEL_MCI_H__ -#define __CPU_AT32AP_ATMEL_MCI_H__ +#ifndef __ATMEL_MCI_H__ +#define __ATMEL_MCI_H__ /* Atmel MultiMedia Card Interface (MCI) registers */ #define MMCI_CR 0x0000 @@ -198,4 +198,4 @@ #define mmci_writel(reg,value) \ writel((value), (void *)MMCI_BASE + MMCI_##reg) -#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */ +#endif /* __ATMEL_MCI_H__ */ diff --git a/include/mmc.h b/include/mmc.h index 8973bc7..af227cd 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -179,44 +179,61 @@ struct mmc_cid { char pnm[7]; }; -struct mmc_csd -{ - u8 csd_structure:2, - spec_vers:4, - rsvd1:2; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc:12, - read_bl_len:4; - u64 read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - sector_size:5, - erase_grp_size:5, - wp_grp_size:5, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:5; - u8 file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; - u8 crc:7; - u8 one:1; +/* + * CSD structure for SD/MMC cards upto 4GB + * + * Bitfields in the 128 Bit answer from the card + * (bit 127 is bit 31 of first u32 + * bit 0 is bit 0 of last u32) + * csd_structure:127..126 + * spec_vers:125..122 + * rsvd1:121..120 + * taac:119..112 + * nsac:111..104 + * tran_speed:103..96 + * ccc:95..84 + * read_bl_len:83..80 + * read_bl_partial:79 + * write_blk_misalign:78 + * read_blk_misalign:77 + * dsr_imp:76 + * rsvd2:75..74 + * c_size:73..62 - crosses u32 boundary! + * vdd_r_curr_min:61..59 + * vdd_r_curr_max:58..56 + * vdd_w_curr_min:55..53 + * vdd_w_curr_max:52..50 + * c_size_mult:49..47 + * sector_size:46..42 + * erase_grp_size:41..37 + * wp_grp_size:36..32 + * wp_grp_enable:31 + * default_ecc:30..29 + * r2w_factor:28..26 + * write_bl_len:25..22 + * write_bl_partial:21 + * rsvd3:20..16 + * file_format_grp:15 + * copy:14 + * perm_write_protect:13 + * tmp_write_protect:12 + * file_format:11..10 + * ecc:9..8 + * crc:7..1 + * one:0 + */ +struct mmc_csd { + /* raw data */ + u32 raw[4]; + /* parsed values we need to read a card */ + u8 taac; + u8 nsac; + u8 read_bl_len; + u8 read_bl_partial; + u32 c_size; + u8 c_size_mult; + u32 blocks; + u32 blocksize; }; struct mmc_cmd { -- 1.5.6.5

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[U-Boot] Beloved
by Zenab Justin 03 Sep '10

03 Sep '10

Beloved, Let me first introduce myself to you My name is Zenab Justin Yak, 24years old originated from Sudan. I really want to have a good relationship with you. My father Dr. Justin Yak Arop was the former Minister for SPLA Affairs and Special Adviser to President Salva Kiir of South Sudan for Decentralization. My father Dr. Justin Yak and my mother including other top Military officers and top government officials had been on board when the plane crashed on Friday May 02, 2008.. You can read more about the crash through the below site:http://news.bbc.co.uk/2/hi/africa/7380412.stm After the burial of my father, my uncles conspired and sold my father’s properties to a Chinese Expatriate and live nothing for me. On a faithful morning, I opened my father's briefcase and found out the documents which he have deposited huge amount of money in one bank in Burkina Faso with my name as the next of kin. I travelled to Burkina Faso to withdraw the money so that I can start a better life and take care of myself. On my arrival, the Branch manager of the Bank whom I met in person told me that my father's instruction to the bank was the money be release to me only when I am married or present a trustee who will help me and invest the money overseas. I have chosen to contact you after my prayers and I believe that you will not betray my trust. But rather take me as your own sister. Though you may wonder why I am so soon revealing myself to you without knowing you, well, I will say that my mind convinced me that you are the true person to help me. More so, I will like to disclose much to you if you can help me to relocate to your country because my uncle has threatened to assassinate me. The amount is $8.4 Million and I have confirmed from the bank in Burkina Faso. You will also help me to place the money in a more profitable business venture in your Country. However, you will help by recommending a nice University in your country so that I can complete my studies. It is my intention to compensate you with 10% of the total money for your services and the balance shall be my capital in your establishment. As soon as I receive your interest in helping me, I will put things into action immediately. In the light of the above, I shall appreciate an urgent message indicating your ability and willingness to handle this transaction sincerely. Please do keep this only to your self. I beg you not to disclose it till i come over because I am afraid of my wicked uncle who has threatened to kill me. Sincerely yours, Zenab Justin Yak.

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