August 2010 - U-Boot

[U-Boot] Make preparatory patches that initially have no effect?
by Reinhard Meyer 17 Aug '10

17 Aug '10

Hello, my current work in the AT91 SoCs will add several new drivers. Some of them require new header files in arch-at91 or amendments to existing header files there. Same for some at91 specific header files in driver/*. In existing header files it is adding adresses for going-to-be-used devices and proper struct SoC defines for them, the new header files will only allow struct SoC access anyway. If I add those discrete changes to each driver patch (where it might actually belong), the incremental changes to some of those files would require all those driver patches to be applied in the right order to avoid conflicts. Therefore I would like to put all new header files and all changes to header files in one patch which would need to be applied before the driver patches. That patch would essentially cause no change to existing code. Anyone find this idea bad? Reinhard

4 15

[U-Boot] [PATCH 2/7] powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined
by Haiying Wang 17 Aug '10

17 Aug '10

This fixes the compiling error for the board which doesn't have NOR flash (so CONFIG_FLASH_BASE is not defined) Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2c3be6d..1fbc0cc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -327,7 +327,7 @@ int cpu_init_r(void) if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); l2srbar = l2cache->l2srbar0; -#ifdef CONFIG_SYS_INIT_L2_ADDR +#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; -- 1.7.0

2 3

[U-Boot] [PATCH 1/7] nand_spl: remove static for nand_load
by Haiying Wang 17 Aug '10

17 Aug '10

so it can be called in other file. Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- nand_spl/nand_boot_fsl_elbc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c index 9547d44..efac293 100644 --- a/nand_spl/nand_boot_fsl_elbc.c +++ b/nand_spl/nand_boot_fsl_elbc.c @@ -47,7 +47,7 @@ static void nand_wait(void) } } -static void nand_load(unsigned int offs, int uboot_size, uchar *dst) +void nand_load(unsigned int offs, int uboot_size, uchar *dst) { fsl_lbc_t *regs = LBC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; -- 1.7.0

2 2

[U-Boot] [PATCH] S5P: Use accessor functions instead of SoC specific defines to access the base address
by Minkyu Kang 17 Aug '10

17 Aug '10

This patch is intended to prepare the other S5P SoC. (s5pc210) If use SoC specific defines then can't share with other SoC. So, make the accessor functions for access the base address by common way. Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- arch/arm/cpu/armv7/s5pc1xx/clock.c | 24 ++++++++++++++++-------- arch/arm/cpu/armv7/s5pc1xx/cpu_info.c | 2 +- arch/arm/cpu/armv7/s5pc1xx/reset.S | 2 +- arch/arm/cpu/armv7/s5pc1xx/sromc.c | 8 ++------ arch/arm/cpu/armv7/s5pc1xx/timer.c | 5 +---- arch/arm/include/asm/arch-s5pc1xx/cpu.h | 28 +++++++++++++++++++++++----- arch/arm/include/asm/arch-s5pc1xx/pwm.h | 4 ---- board/samsung/goni/lowlevel_init.S | 6 +++--- board/samsung/smdkc100/lowlevel_init.S | 2 +- board/samsung/smdkc100/onenand.c | 3 ++- board/samsung/smdkc100/smdkc100.c | 2 +- drivers/mmc/s5p_mmc.c | 6 +----- drivers/serial/serial_s5p.c | 6 +----- 13 files changed, 53 insertions(+), 45 deletions(-) diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c index 19619f9..67af84a 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/clock.c +++ b/arch/arm/cpu/armv7/s5pc1xx/clock.c @@ -45,7 +45,8 @@ unsigned long (*get_pll_clk)(int); /* s5pc110: return pll clock frequency */ static unsigned long s5pc100_get_pll_clk(int pllreg) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, mask, fout; unsigned int freq; @@ -95,7 +96,8 @@ static unsigned long s5pc100_get_pll_clk(int pllreg) /* s5pc100: return pll clock frequency */ static unsigned long s5pc110_get_pll_clk(int pllreg) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, mask, fout; unsigned int freq; @@ -151,7 +153,8 @@ static unsigned long s5pc110_get_pll_clk(int pllreg) /* s5pc110: return ARM clock frequency */ static unsigned long s5pc110_get_arm_clk(void) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long div; unsigned long dout_apll, armclk; unsigned int apll_ratio; @@ -170,7 +173,8 @@ static unsigned long s5pc110_get_arm_clk(void) /* s5pc100: return ARM clock frequency */ static unsigned long s5pc100_get_arm_clk(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long div; unsigned long dout_apll, armclk; unsigned int apll_ratio, arm_ratio; @@ -191,7 +195,8 @@ static unsigned long s5pc100_get_arm_clk(void) /* s5pc100: return HCLKD0 frequency */ static unsigned long get_hclk(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long hclkd0; uint div, d0_bus_ratio; @@ -207,7 +212,8 @@ static unsigned long get_hclk(void) /* s5pc100: return PCLKD1 frequency */ static unsigned long get_pclkd1(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long d1_bus, pclkd1; uint div, d1_bus_ratio, pclkd1_ratio; @@ -227,7 +233,8 @@ static unsigned long get_pclkd1(void) /* s5pc110: return HCLKs frequency */ static unsigned long get_hclk_sys(int dom) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long hclk; unsigned int div; unsigned int offset; @@ -255,7 +262,8 @@ static unsigned long get_hclk_sys(int dom) /* s5pc110: return PCLKs frequency */ static unsigned long get_pclk_sys(int dom) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long pclk; unsigned int div; unsigned int offset; diff --git a/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c b/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c index f16c0ff..454175c 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c +++ b/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c @@ -30,7 +30,7 @@ unsigned int s5pc1xx_cpu_id = 0xC100; #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { - s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID); + s5pc1xx_cpu_id = readl(samsung_get_base_pro_id()); s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12); s5pc1xx_clock_init(); diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S index 7f6ff9c..70fa146 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/reset.S +++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S @@ -28,7 +28,7 @@ .globl reset_cpu reset_cpu: - ldr r1, =S5PC1XX_PRO_ID + ldr r1, =S5PC100_PRO_ID ldr r2, [r1] ldr r4, =0x00010000 and r4, r2, r4 diff --git a/arch/arm/cpu/armv7/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c index 380be81..044d122 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/sromc.c +++ b/arch/arm/cpu/armv7/s5pc1xx/sromc.c @@ -35,12 +35,8 @@ void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) { u32 tmp; - struct s5pc1xx_smc *srom; - - if (cpu_is_s5pc100()) - srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; - else - srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; + struct s5pc1xx_smc *srom = + (struct s5pc1xx_smc *)samsung_get_base_sromc(); /* Configure SMC_BW register to handle proper SROMC bank */ tmp = srom->bw; diff --git a/arch/arm/cpu/armv7/s5pc1xx/timer.c b/arch/arm/cpu/armv7/s5pc1xx/timer.c index c5df5c5..6487c0f 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/timer.c +++ b/arch/arm/cpu/armv7/s5pc1xx/timer.c @@ -46,10 +46,7 @@ static unsigned long lastdec; /* Last decremneter snapshot */ /* macro to read the 16 bit timer */ static inline struct s5pc1xx_timer *s5pc1xx_get_base_timer(void) { - if (cpu_is_s5pc110()) - return (struct s5pc1xx_timer *)S5PC110_TIMER_BASE; - else - return (struct s5pc1xx_timer *)S5PC100_TIMER_BASE; + return (struct s5pc1xx_timer *)samsung_get_base_timer(); } int timer_init(void) diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index b3af8cc..bcb8f5c 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -25,9 +25,9 @@ #define S5PC1XX_ADDR_BASE 0xE0000000 -#define S5PC1XX_CLOCK_BASE 0xE0100000 - /* S5PC100 */ +#define S5PC100_PRO_ID 0xE0000000 +#define S5PC100_CLOCK_BASE 0xE0100000 #define S5PC100_GPIO_BASE 0xE0300000 #define S5PC100_VIC0_BASE 0xE4000000 #define S5PC100_VIC1_BASE 0xE4100000 @@ -41,6 +41,8 @@ #define S5PC100_MMC_BASE 0xED800000 /* S5PC110 */ +#define S5PC110_PRO_ID 0xE0000000 +#define S5PC110_CLOCK_BASE 0xE0100000 #define S5PC110_GPIO_BASE 0xE0200000 #define S5PC110_PWMTIMER_BASE 0xE2500000 #define S5PC110_WATCHDOG_BASE 0xE2700000 @@ -54,9 +56,6 @@ #define S5PC110_VIC2_BASE 0xF2200000 #define S5PC110_VIC3_BASE 0xF2300000 -/* Chip ID */ -#define S5PC1XX_PRO_ID 0xE0000000 - #ifndef __ASSEMBLY__ /* CPU detection macros */ extern unsigned int s5pc1xx_cpu_id; @@ -69,6 +68,25 @@ static inline int cpu_is_##type(void) \ IS_SAMSUNG_TYPE(s5pc100, 0xc100) IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +#define SAMSUNG_BASE(device, base) \ +static inline unsigned int samsung_get_base_##device(void) \ +{ \ + if (cpu_is_s5pc100()) \ + return S5PC100_##base; \ + else if (cpu_is_s5pc110()) \ + return S5PC110_##base; \ + else \ + return 0; \ +} \ + +SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(gpio, GPIO_BASE) +SAMSUNG_BASE(pro_id, PRO_ID) +SAMSUNG_BASE(mmc, MMC_BASE) +SAMSUNG_BASE(sromc, SROMC_BASE) +SAMSUNG_BASE(timer, PWMTIMER_BASE) +SAMSUNG_BASE(uart, UART_BASE) #endif #endif /* _S5PC1XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h index e02a8d8..518f6ae 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ b/arch/arm/include/asm/arch-s5pc1xx/pwm.h @@ -22,10 +22,6 @@ #ifndef __ASM_ARM_ARCH_PWM_H_ #define __ASM_ARM_ARCH_PWM_H_ -/* PWM timer addressing */ -#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE -#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE - /* Interval mode(Auto Reload) of PWM Timer 4 */ #define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) /* Update TCNTB4 */ diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 4b72992..62737ab 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -51,7 +51,7 @@ lowlevel_init: ldr r7, =S5PC100_GPIO_BASE ldr r8, =S5PC100_GPIO_BASE /* Read CPU ID */ - ldr r2, =S5PC1XX_PRO_ID + ldr r2, =S5PC110_PRO_ID ldr r0, [r2] mov r1, #0x00010000 and r0, r0, r1 @@ -377,7 +377,7 @@ lockloop: * void system_clock_init(void) */ system_clock_init: - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Check S5PC100 */ cmp r7, r8 @@ -437,7 +437,7 @@ system_clock_init: ldr r1, =0x3ff03ff str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 32572c5..30d0d06 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -131,7 +131,7 @@ wakeup_reset: * void system_clock_init(void) */ system_clock_init: - ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x00011110 diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index c25869e..501855e 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -35,7 +35,8 @@ void onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); struct samsung_onenand *onenand; int value; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index fb466c6..bb72fd1 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -38,7 +38,7 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c index 872f0bb..1fd425c 100644 --- a/drivers/mmc/s5p_mmc.c +++ b/drivers/mmc/s5p_mmc.c @@ -30,11 +30,7 @@ struct mmc_host mmc_host[4]; static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index) { unsigned long offset = dev_index * sizeof(struct s5p_mmc); - - if (cpu_is_s5pc100()) - return (struct s5p_mmc *)(S5PC100_MMC_BASE + offset); - else - return (struct s5p_mmc *)(S5PC110_MMC_BASE + offset); + return (struct s5p_mmc *)(samsung_get_base_mmc() + offset); } static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index e0d4e80..6a61b4f 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -30,11 +30,7 @@ static inline struct s5p_uart *s5p_get_base_uart(int dev_index) { u32 offset = dev_index * sizeof(struct s5p_uart); - - if (cpu_is_s5pc100()) - return (struct s5p_uart *)(S5PC100_UART_BASE + offset); - else - return (struct s5p_uart *)(S5PC110_UART_BASE + offset); + return (struct s5p_uart *)(samsung_get_base_uart() + offset); } /* -- 1.7.0.4

2 1

[U-Boot] [PATCH - RFC] env_nand.c: fail gracefully if no nand is present
by Steve Sakoman 17 Aug '10

17 Aug '10

Rationale: The upcoming Beagle xM, unlike previous Beagles, has no on-board NAND. I'd like to continue to have a single version of u-boot that works for all version of Beagles. Therefore I need to have env_nand fail gracefully when it runs on the xM. The patch below does the job, but I am not sure that my method of checking for the existence of nand (nand_info[0].type = 0 when no nand detected) is "correct"? Any opinions or advice? Steve --- diff --git a/common/env_nand.c b/common/env_nand.c index a15a950..325f112 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -268,6 +268,10 @@ int readenv (size_t offset, u_char * buf) u_char *char_ptr; + /* fail if no nand detected */ + if (nand_info[0].type == 0) + return 1; + blocksize = nand_info[0].erasesize; len = min(blocksize, CONFIG_ENV_SIZE);

2 2

[U-Boot] handling of bad blocks in nand
by Arno Steffen 16 Aug '10

16 Aug '10

A short question to handling of bad blocks: My nand shows a few bad blocks (example 100000) What is happen when I write / read from that block via nand write / read. Is content than ok (by mapping good blocks do that address)? Other way around - if I have commands like "get_kn=nand read.i 0x80000000 c0000 200000" do I have to care for bad blocks in that range ? Di I have to make the part bigger to have some extra blocks, if one is skipped while write/read as it is bad? Best regards Arno

5 14

[U-Boot] Information request about Generic MMC
by Gérald Kerma 16 Aug '10

16 Aug '10

Hi all developers, I would like to backport the Marvell SDIO driver to u-boot. I have complete the 'port' of the Marvell's uboot sources code for a legacy like driver. It will be better to make a "new" driver and I look for informations about the generic MMC driver coding style. Can anyone tell me the needed features or point me to technical references ? Many thanks. -- Gérald

2 1

[U-Boot] [PATCH] common/cmd_mmc.c: fix a bug
by Haiying Wang 16 Aug '10

16 Aug '10

introduced by commit cc9f607beb49d4d3556c326efb83a0a51784e484, it causes: " cmd_mmc.c:136:2: warning: missing terminating " character cmd_mmc.c:133: error: missing terminating " character make[1]: *** [cmd_mmc.o] Error 1 " Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- common/cmd_mmc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index a6ed6a8..c0b30d8 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -133,7 +133,7 @@ int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( mmcinfo, 2, 0, do_mmcinfo, "display MMC info", - "<dev num>\n + "<dev num>\n" " - device number of the device to dislay info of\n" "" ); -- 1.7.0

2 1

[U-Boot] BDI3000 for MIPS64
by Andreas Bießmann 16 Aug '10

16 Aug '10

Has anyone configuration file for BDI3000 targeting CN50xx Cavium MIPS64 CPU and is willing to share it? regards Andreas Bießmann

2 1

[U-Boot] [PATCH 7/7] powerpc/p1021mds: add QE and UEC support
by Haiying Wang 16 Aug '10

16 Aug '10

P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++ arch/powerpc/include/asm/immap_85xx.h | 13 ++++++++ board/freescale/p1021mds/p1021mds.c | 54 +++++++++++++++++++++++++++++++++ drivers/qe/uec.c | 36 ++++++++++++++++++++++ include/configs/P1021MDS.h | 44 ++++++++++++++++++++++++++ 5 files changed, 151 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index dd4c6b3..6f1aa7b 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -163,10 +163,14 @@ void get_sys_info (sys_info_t * sysInfo) #endif #ifdef CONFIG_QE +#ifdef CONFIG_P1021 + sysInfo->freqQE = sysInfo->freqSystemBus; +#else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#endif #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5eeb93a..896014b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1923,6 +1923,19 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 +#define MPC85xx_PMUXCR_QE0 0x00008000 +#define MPC85xx_PMUXCR_QE1 0x00004000 +#define MPC85xx_PMUXCR_QE2 0x00002000 +#define MPC85xx_PMUXCR_QE3 0x00001000 +#define MPC85xx_PMUXCR_QE4 0x00000800 +#define MPC85xx_PMUXCR_QE5 0x00000400 +#define MPC85xx_PMUXCR_QE6 0x00000200 +#define MPC85xx_PMUXCR_QE7 0x00000100 +#define MPC85xx_PMUXCR_QE8 0x00000080 +#define MPC85xx_PMUXCR_QE9 0x00000040 +#define MPC85xx_PMUXCR_QE10 0x00000020 +#define MPC85xx_PMUXCR_QE11 0x00000010 +#define MPC85xx_PMUXCR_QE12 0x00000008 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ u8 res6[8]; u32 devdisr; /* Device disable control */ diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c index c61c902..9297d0c 100644 --- a/board/freescale/p1021mds/p1021mds.c +++ b/board/freescale/p1021mds/p1021mds.c @@ -24,6 +24,48 @@ #include <tsec.h> #include <netdev.h> +#include "bcsr.h" + +#ifdef CONFIG_QE +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* QE_MUX_MDC */ + {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ + + /* QE_MUX_MDIO */ + {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ + + /* UCC_1_MII */ + {0, 23, 2, 0, 2}, /* CLK12 */ + {0, 24, 2, 0, 1}, /* CLK9 */ + {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ + {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ + {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ + {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ + {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ + {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ + {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ + {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ + {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ + {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ + {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ + {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ + {0, 17, 2, 0, 2}, /* ENET1_CRS */ + {0, 16, 2, 0, 2}, /* ENET1_COL */ + + /* UCC_5_RMII */ + {1, 11, 2, 0, 1}, /* CLK13 */ + {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ + {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ + {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ + {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ + {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ + {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ + {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ + + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ +}; +#endif + const char *board_hwconfig = "foo:bar=baz"; const char *cpu_hwconfig = "foo:bar=baz"; @@ -88,6 +130,14 @@ int board_eth_init(bd_t *bis) tsec_eth_init(bis, tsec_info, num); +#if defined(CONFIG_UEC_ETH) + /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); + + uec_standard_init(bis); +#endif + return pci_eth_init(bis); } #endif @@ -109,6 +159,10 @@ void ft_board_setup(void *blob, bd_t *bd) ft_pci_board_setup(blob); +#ifdef CONFIG_QE + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", + sizeof("okay"), 0); +#endif } #endif ; diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index ccbf27d..e434564 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -30,6 +30,9 @@ #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#ifdef CONFIG_P1021 +#include "../../board/freescale/p1021mds/bcsr.h" +#endif /* Default UTBIPAR SMI address */ #ifndef CONFIG_UTBIPAR_INIT_TBIPA @@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); +#ifdef CONFIG_P1021 + /* + * QE12 is muxed with LBCTL, it needs to be released for enabling + * LBCTL signal for LBC usage. + */ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Adjust the interface according to speed */ adjust_link(dev); } @@ -1198,10 +1217,22 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { +#ifdef CONFIG_P1021 + /* reset micrel phy for each UEC */ + reset_p1021mds_micrel_phy(); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + err = init_phy(dev); if (err) { printf("%s: Cannot initialize PHY, aborting.\n", @@ -1226,6 +1257,11 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (((i-- > 0) && !uec->mii_info->link) || err); +#ifdef CONFIG_P1021 + /* QE12 needs to be released for enabling LBCTL signal*/ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name); diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h index 6f63aac..1d51852 100644 --- a/include/configs/P1021MDS.h +++ b/include/configs/P1021MDS.h @@ -342,6 +342,50 @@ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif /* CONFIG_TSEC_ENET */ +#define CONFIG_QE + +#ifdef CONFIG_QE +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 +#define CONFIG_SYS_QE_FW_ADDR 0x10000000 +#define CONFIG_SYS_QE_FW_LENGTH 0x10000 + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) + +#define CONFIG_UEC_ETH +#define CONFIG_PHY_MODE_NEED_CHANGE + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define CONFIG_HAS_ETH0 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ +#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH1 */ + +#define CONFIG_UEC_ETH5 /* GETH5 */ +#define CONFIG_HAS_ETH1 + +#ifdef CONFIG_UEC_ETH5 +#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ +#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ +#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ +#define CONFIG_SYS_UEC5_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH2 */ + +#endif /* CONFIG_QE */ + /* * I2C */ -- 1.7.0

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