August 2010 - U-Boot

[U-Boot] Pull request: nand flash
by Scott Wood 17 Aug '10

17 Aug '10

The following changes since commit 668a6b45915d10d75357f5b93f569bbf49ea2b06: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-usb are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git master Mike Frysinger (1): env_nand: return error when no device is found common/env_nand.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)

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[U-Boot] Dünyanın Heryerine Hızlı ve Ekonomik Hava Kargo & Kurye Taşımacılığı
by Mps Rusya & Türki Cumhuriyetler Hızlı Paket Taşıma cılığı A.Ş 17 Aug '10

17 Aug '10

MPS Express Dev Kampanya.... MPS Gift Hediye Kampanyasından Sizde Yararlanın... Dünyanın 220 Ülkesinde Faliyet gösteren MPS Express Türkiyeden Dünyanın Heryerine Döküman Paket Koli ve İhracat Kargolarınızı en hızlı en ekonomik ve en güvenli şekilde taşıma hizmetini bir yenisini daha ekledi.Türkiyeden Rusya ve Ukrayna Ülkelerine göndereceğiniz her türlü kargolarınızı kg gözetmeksizin KAPIDAN - KAPIYA İmza karşılığı teslim ederek rakipsiz bir hizmet başlatmıştır. Rusya & Ukrayna Paket Taşımacılığı Varış ülkesinde gümrüğe tabi olsun olmasın numunelerinizi Rusya ve Ukrayna Ülkelerinde Rakipleri Gümrüğe bırakırken,MPS Express Müşterinizin kapısına teslim etmeyi taahüt ediyor. Rusya ve Ukrayna Fuar Taşıma Hizmeti MPS Express Fuar Taşıma hizmeti ile katılacağınız fuarlarda organizasyonlarınızın başarı ile sonuçlandırmanıza yardımcı olmak için sizi sadece satış odaklı kılabilmek ve katılacağınız etkinlik nerede olursa olsun MPS Express KALİTE VE DENEYİMİ VE HIZLI. Sizlere tam zamanlı organizasyonlarınızın her aşamasında üstlenerek müşterileriniz ile 10.yılında buluşturma devam ediyor... Dünyanın Heryerine Hızlı ve Ekonomik Hava Kargo & Kurye Taşımacılığı MPS Express Yurtdışına göndereceğiniz Tüm Kargolarınızda Dünyanın 220 Ülkesine Hızlı & Ekonomik güvenilir bir şekilde taşıma hizmeti sağlamaktadır.Dünya Çapında bir çok güçlü kuruluş ile işbirliği yapan MPS Express Türkiye genelinde Müşterilerine sunduğu kaliteli hizmet sayesinde 220 ülke ve özerk bölgede konumunu sürdürmektedir.MPS Express çeşitli ülkeler de en yaygın kuruluşlar işbirliği yapmayı tercih ederek müşterilerine lokal dağıtımda en dağıtım firmaları ile çalışma avantajları sağlamaktadır. Hava Kargo Türkiyeden Dünyanın her yerine ,Dünyanın her yerinden Havalimanı yada kapıdan kapıya havayolu taşımacılığı hizmetleri veren MPS Express Seçkin havayolu şirketleri ile Yapılan anlaşmalar sayesinde taşımalarda yer ve fiyat avantajları sağlamaktadır.MPS Express Sektöründe deneyimi ve çalışma anlayışı ile havayolu taşımacılığında Türkiyede öncü bir marka haline gelmiştir.İhracatta artan dış rekabetin ve uluslararası arenadaki alıcıların daha hızlı termin isteklerinin sonucu olarak oluşan kalite hizmet ve ekonomik çözümler ile talebini karşılayarak yatırımlarını tamamlamıştır. Dünyanın Heryerine Hava Kargo Ürün ve Hizmetlerimiz Müşteri Hizmetleri .:+ 90 212 444 0 108 Havalimanından Havalimanı Taşıma Çözümleri sales(a)mpsglobalexpress.com www.mpsglobalexpress.com Havalimanından Kapıya Taşıma Çözümleri info(a)mpsglobalexpress.com Tehlikeli Madde Taşıma Çözümleri Kapıdan Havalimanına Taşıma Çözümleri Kapıdan Kapıya Taşıma Çözümleri Gümrüklü & Gümrüksüz Kapı Teslimi Yolcu beraberinde Kargo Teslim Çözümleri Rusya ve Ukrayna Acil Kargo Çözümleri -

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[U-Boot] [PATCH 3/7] Add support for SRAM Boot
by Haiying Wang 17 Aug '10

17 Aug '10

Once CONFIG_MIDDLE_STAGE_SRAM_BOOT is defined, CONFIG_SRAM_BOOT is enabled to generate u-boot-sram.bin which will run in the l2/l3 sram. This middle stage uboot will init ddr sdram with ddr spd code and load the final uboot image to ddr and start from there. It is useful for the silicons which have small l2/l3 size under the two scenarios: 1. NAND boot. The 4k NAND SPL uboot can not enable the spd ddr code to initialize the ddr because of the 4k size limitation, and the l2/l3 as SRAM also is not large enough to acoommodate the final uboot image. 2. SD/eSPI boot. we don't want to statically init ddr in SD/eSPI's configuration part, but l2/l3 as SRAM is small for final uboot. This patch has nand boot support, SD/eSPI support will be submited later. Because ddr spd code calls some functions defined the files in common/ and lib/,#ifndef CONFIG_SRAM_BOOT is used in those files to keep the sram uboot size as small as possible. Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- Makefile | 18 ++- arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 31 +++- arch/powerpc/cpu/mpc85xx/sram_boot/Makefile | 190 ++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c | 76 ++++++++ .../cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds | 101 +++++++++++ arch/powerpc/cpu/mpc85xx/start.S | 8 +- common/cmd_nvedit.c | 8 +- common/console.c | 4 + common/env_common.c | 4 + common/env_nand.c | 3 +- lib/display_options.c | 2 + lib/string.c | 10 + lib/vsprintf.c | 2 + 13 files changed, 450 insertions(+), 7 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/sram_boot/Makefile create mode 100644 arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c create mode 100644 arch/powerpc/cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds diff --git a/Makefile b/Makefile index 4f1cb1b..b1d92b7 100644 --- a/Makefile +++ b/Makefile @@ -280,10 +280,18 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version $[0-9][0-9]*$\.$[0-9][0-9]*$.*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') +ifeq ($(CONFIG_MIDDLE_STAGE_SRAM_BOOT),y) +SRAM_BOOT = sram_boot +endif + ifeq ($(CONFIG_NAND_U_BOOT),y) NAND_SPL = nand_spl +ifeq ($(CONFIG_MIDDLE_STAGE_SRAM_BOOT),y) +U_BOOT_NAND_SRAM = $(obj)u-boot-nand.bin +else U_BOOT_NAND = $(obj)u-boot-nand.bin endif +endif ifeq ($(CONFIG_ONENAND_U_BOOT),y) ONENAND_IPL = onenand_ipl @@ -298,7 +306,7 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) ######################################################################### # Always append ALL so that arch config.mk's can add custom ones -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) +ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) $(U_BOOT_NAND_SRAM) all: $(ALL) @@ -382,6 +390,12 @@ $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin +$(SRAM_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk + $(MAKE) -C $(CPUDIR)/sram_boot all + +$(U_BOOT_NAND_SRAM): $(NAND_SPL) $(SRAM_BOOT) $(obj)u-boot.bin + cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)$(CPUDIR)/u-boot-sram.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin + $(ONENAND_IPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all @@ -2459,6 +2473,7 @@ clean: @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map} @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} + @rm -f $(obj)$(CPUDIR)/{u-boot-sram,u-boot-sram.map} @rm -f $(ONENAND_BIN) @rm -f $(obj)onenand_ipl/u-boot.lds @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) @@ -2482,6 +2497,7 @@ clobber: clean @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f + @[ ! -d $(obj)board/freescale ] || find $(obj)board/freescale -name "*" -type l -print | xargs rm -f ifeq ($(OBJTREE),$(SRCTREE)) mrproper \ diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 8fb27ab..ff09bea 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -40,7 +40,8 @@ void cpu_init_f(void) #error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined #endif -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) \ + && !defined(CONFIG_SRAM_BOOT) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; char *l2srbar; int i; @@ -60,4 +61,32 @@ void cpu_init_f(void) for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) l2srbar[i] = 0; #endif +#ifdef CONFIG_SRAM_BOOT + init_used_tlb_cams(); +#endif +} + +#ifdef CONFIG_SRAM_BOOT +/* Because the primary cpu's info is enough in SRAM BOOT stage we define the + * cpu number to 1 so as to keep code size for sram boot uboot as small as + * possible. + */ +int cpu_numcores() +{ + return 1; +} + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk(void) +{ +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else + return (gd->bus_clk + 4UL)/8UL; +#endif } +#endif /* CONFIG_SRAM_BOOT */ diff --git a/arch/powerpc/cpu/mpc85xx/sram_boot/Makefile b/arch/powerpc/cpu/mpc85xx/sram_boot/Makefile new file mode 100644 index 0000000..7c86095 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/sram_boot/Makefile @@ -0,0 +1,190 @@ +# +# Copyright (C) 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +SRAM_BOOT := y + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/sram_boot/u-boot-sram-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_SRAM_BOOT +CFLAGS += -DCONFIG_SRAM_BOOT + +SOBJS = start.o ticks.o ppcstring.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o speed.o \ + sram_boot.o ns16550.o tlb.o tlb_table.o string.o hwconfig.o ddr.o \ + time.o time_lib.o ddr-gen3.o ddr_spd.o ctype.o div64.o console.o \ + cmd_nvedit.o env_common.o env_nand.o vsprintf.o display_options.o + +ifdef CONFIG_RAMBOOT_NAND +COBJS += nand_boot_fsl_elbc.o +endif + +LIBS = $(TOPDIR)/arch/powerpc/cpu/mpc8xxx/ddr/libddr.a +LIBS += $(TOPDIR)/drivers/i2c/libi2c.a + + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/$(CPUDIR)/sram_boot + +sramobj := $(OBJTREE)/$(CPUDIR)/ + +ALL = $(sramobj)u-boot-sram $(sramobj)u-boot-sram.bin + +all: $(obj).depend $(ALL) + +$(sramobj)u-boot-sram.bin: $(sramobj)u-boot-sram + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(sramobj)u-boot-sram: $(OBJS) $(LIBS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(LIBS) $(PLATFORM_LIBS) \ + -Map $(sramobj)u-boot-sram.map \ + -o $(sramobj)u-boot-sram + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)speed.c: + @rm -f $(obj)speed.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/speed.c $(obj)speed.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)ticks.S: + @rm -f $(obj)ticks.S + ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +$(obj)ddr.c: + @rm -f $(obj)ddr.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/ddr.c $(obj)ddr.c + +$(obj)time.c: + @rm -f $(obj)time.o + ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c + +$(obj)time_lib.c: + @rm -f $(obj)time_lib.o + ln -sf $(SRCTREE)/lib/time.c $(obj)time_lib.c + +$(obj)ppcstring.S: + @rm -f $(obj)ppcstring.S + ln -sf $(SRCTREE)/arch/powerpc/lib/ppcstring.S $(obj)ppcstring.S + +$(obj)ddr-gen3.c: + @rm -f $(obj)ddr-gen3.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c + +$(obj)ddr_spd.c: + @rm -f $(obj)ddr_spd.c + ln -sf $(SRCTREE)/common/ddr_spd.c $(obj)ddr_spd.c + +$(obj)ctype.c: + @rm -f $(obj)ctype.c + ln -sf $(SRCTREE)/lib/ctype.c $(obj)ctype.c + +$(obj)div64.c: + @rm -f $(obj)div64.c + ln -sf $(SRCTREE)/lib/div64.c $(obj)div64.c + +$(obj)env_common.c: + @rm -f $(obj)env_common.c + ln -sf $(SRCTREE)/common/env_common.c $(obj)env_common.c + +$(obj)env_nand.c: + @rm -f $(obj)env_nand.c + ln -sf $(SRCTREE)/common/env_nand.c $(obj)env_nand.c + +$(obj)cmd_nvedit.c: + @rm -f $(obj)cmd_nvedit.c + ln -sf $(SRCTREE)/common/cmd_nvedit.c $(obj)cmd_nvedit.c + +$(obj)console.c: + @rm -f $(obj)console.c + ln -sf $(SRCTREE)/common/console.c $(obj)console.c + +$(obj)hwconfig.c: + @rm -f $(obj)hwconfig.c + ln -sf $(SRCTREE)/common/hwconfig.c $(obj)hwconfig.c + +$(obj)string.c: + @rm -f $(obj)string.c + ln -sf $(SRCTREE)/lib/string.c $(obj)string.c + +$(obj)vsprintf.c: + @rm -f $(obj)vsprintf.c + ln -sf $(SRCTREE)/lib/vsprintf.c $(obj)vsprintf.c + +$(obj)display_options.c: + @rm -f $(obj)display_options.c + ln -sf $(SRCTREE)/lib/display_options.c $(obj)display_options.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)sram_boot.c: + @rm -f $(obj)sram_boot.c + ln -s $(SRCTREE)/board/freescale/common/sram_boot/sram_boot.c $(obj)sram_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c b/arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c new file mode 100644 index 0000000..7b90eee --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include <common.h> +#include <mpc85xx.h> +#include <asm/io.h> +#include <ns16550.h> +#include <nand.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +const char *board_hwconfig = "foo:bar=baz"; +const char *cpu_hwconfig = "foo:bar=baz"; + +void board_init_f(ulong bootflag) +{ + uint plat_ratio, bus_clk, sys_clk = 0; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + sys_clk = CONFIG_SYS_CLK_FREQ; + + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = plat_ratio * sys_clk; + get_clocks(); + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + /* load environment */ +#ifdef CONFIG_NAND_U_BOOT + nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + /* board specific DDR initialization */ + gd->ram_size = init_ddr_dram(); + puts("DRAM:"); + print_size(gd->ram_size, ""); + + puts("\nSRAM boot (middle stage uboot in sram)... "); + + /* + * Load final image to DDR and let it run from there. + */ +#ifdef CONFIG_NAND_U_BOOT + nand_boot(); +#endif +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/arch/powerpc/cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds b/arch/powerpc/cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds new file mode 100644 index 0000000..ddccfef --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds @@ -0,0 +1,101 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + start.o (.bootpg) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 3278b10..0b59b58 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -54,6 +54,7 @@ * Use r12 to access the GOT */ START_GOT +#ifndef CONFIG_SRAM_BOOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) @@ -63,6 +64,7 @@ GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) #endif +#endif /* !CONFIG_SRAM_BOOT */ GOT_ENTRY(__init_end) GOT_ENTRY(_end) @@ -432,7 +434,7 @@ _start_cont: bl board_init_f isync -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SRAM_BOOT) . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: @@ -874,7 +876,7 @@ in32: in32r: lwbrx r3,r0,r3 blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !CONFIG_NAND_SPL || !CONFIG_SRAM_BOOT*/ /*------------------------------------------------------------------------------*/ @@ -900,6 +902,7 @@ write_tlb: isync blr +#ifndef CONFIG_SRAM_BOOT /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -1203,3 +1206,4 @@ setup_ivors: #include "fixed_ivor.S" blr #endif /* !CONFIG_NAND_SPL */ +#endif /* !CONFIG_SRAM_BOOT */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index fd5320d..af24491 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -80,6 +80,7 @@ SPI_FLASH|MG_DISK|NVRAM|NOWHERE} static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; #define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) +#ifndef CONFIG_SRAM_BOOT /* * This variable is incremented on each do_setenv (), so it can * be used via get_env_id() as an indication, if the environment @@ -514,6 +515,7 @@ int do_editenv(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return setenv(argv[1], buffer); } #endif /* CONFIG_CMD_EDITENV */ +#endif /* !CONFIG_SRAM_BOOT */ /************************************************************************ * Look up variable from environment, @@ -543,6 +545,7 @@ char *getenv (char *name) return (NULL); } +#ifndef CONFIG_SRAM_BOOT int getenv_f(char *name, char *buf, unsigned len) { int i, nxt; @@ -592,7 +595,7 @@ U_BOOT_CMD( ); #endif - +#endif /* !CONFIG_SRAM_BOOT */ /************************************************************************ * Match a name / name=value pair @@ -613,7 +616,7 @@ int envmatch (uchar *s1, int i2) return(-1); } - +#ifndef CONFIG_SRAM_BOOT /**************************************************/ #if defined(CONFIG_CMD_EDITENV) @@ -668,3 +671,4 @@ U_BOOT_CMD( " - run the commands in the environment variable(s) 'var'" ); #endif +#endif /* !CONFIG_SRAM_BOOT */ diff --git a/common/console.c b/common/console.c index 7e01886..3dfc8e8 100644 --- a/common/console.c +++ b/common/console.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SRAM_BOOT #ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV /* * if overwrite_console returns 1, the stdin, stderr and stdout @@ -364,6 +365,7 @@ void puts(const char *s) serial_puts(s); } } +#endif /* !CONFIG_SRAM_BOOT */ int printf(const char *fmt, ...) { @@ -384,6 +386,7 @@ int printf(const char *fmt, ...) return i; } +#ifndef CONFIG_SRAM_BOOT int vprintf(const char *fmt, va_list args) { uint i; @@ -720,3 +723,4 @@ int console_init_r(void) } #endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */ +#endif /* !CONFIG_SRAM_BOOT */ diff --git a/common/env_common.c b/common/env_common.c index 460309b..e04a985 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -134,10 +134,12 @@ uchar default_environment[] = { "\0" }; +#ifndef CONFIG_SRAM_BOOT void env_crc_update (void) { env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); } +#endif /* !CONFIG_SRAM_BOOT */ static uchar env_get_char_init (int index) { @@ -185,6 +187,7 @@ uchar *env_get_addr (int index) } } +#ifndef CONFIG_SRAM_BOOT void set_default_env(void) { if (sizeof(default_environment) > ENV_SIZE) { @@ -281,3 +284,4 @@ int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) return found; } #endif +#endif /* !CONFIG_SRAM_BOOT */ diff --git a/common/env_nand.c b/common/env_nand.c index a5e1038..0f7b83c 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -82,7 +82,7 @@ uchar env_get_char_spec (int index) return ( *((uchar *)(gd->env_addr + index)) ); } - +#ifndef CONFIG_SRAM_BOOT /* this is called before nand_init() * so we can't read Nand to validate env data. * Mark it OK for now. env_relocate() in env_common.c @@ -414,3 +414,4 @@ static void use_default() set_default_env(); } #endif +#endif /* !CONFIG_SRAM_BOOT */ diff --git a/lib/display_options.c b/lib/display_options.c index 20319e6..240ad62 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -84,6 +84,7 @@ void print_size(unsigned long long size, const char *s) printf (" %ciB%s", c, s); } +#ifndef CONFIG_SRAM_BOOT /* * Print data buffer in hex and ascii form to the terminal. * @@ -149,3 +150,4 @@ int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen) return 0; } +#endif /* !CONFIG_SRAM_BOOT */ diff --git a/lib/string.c b/lib/string.c index b375b81..255496a 100644 --- a/lib/string.c +++ b/lib/string.c @@ -54,6 +54,7 @@ int strnicmp(const char *s1, const char *s2, size_t len) } #endif +#ifndef CONFIG_SRAM_BOOT char * ___strtok; #ifndef __HAVE_ARCH_STRCPY @@ -160,6 +161,7 @@ int strcmp(const char * cs,const char * ct) return __res; } #endif +#endif /* !CONFIG_SRAM_BOOT */ #ifndef __HAVE_ARCH_STRNCMP /** @@ -182,6 +184,7 @@ int strncmp(const char * cs,const char * ct,size_t count) } #endif +#ifndef CONFIG_SRAM_BOOT #ifndef __HAVE_ARCH_STRCHR /** * strchr - Find the first occurrence of a character in a string @@ -228,6 +231,7 @@ size_t strlen(const char * s) return sc - s; } #endif +#endif /* !CONFIG_SRAM_BOOT */ #ifndef __HAVE_ARCH_STRNLEN /** @@ -245,6 +249,7 @@ size_t strnlen(const char * s, size_t count) } #endif +#ifndef CONFIG_SRAM_BOOT #ifndef __HAVE_ARCH_STRDUP char * strdup(const char *s) { @@ -286,6 +291,7 @@ size_t strspn(const char *s, const char *accept) return count; } #endif +#endif /* !CONFIG_SRAM_BOOT */ #ifndef __HAVE_ARCH_STRPBRK /** @@ -307,6 +313,7 @@ char * strpbrk(const char * cs,const char * ct) } #endif +#ifndef CONFIG_SRAM_BOOT #ifndef __HAVE_ARCH_STRTOK /** * strtok - Split a string into tokens @@ -556,6 +563,7 @@ void * memscan(void * addr, int c, size_t size) return (void *) p; } #endif +#endif /* CONFIG_SRAM_BOOT */ #ifndef __HAVE_ARCH_STRSTR /** @@ -581,6 +589,7 @@ char * strstr(const char * s1,const char * s2) } #endif +#ifndef CONFIG_SRAM_BOOT #ifndef __HAVE_ARCH_MEMCHR /** * memchr - Find a character in an area of memory. @@ -603,3 +612,4 @@ void *memchr(const void *s, int c, size_t n) } #endif +#endif /* !CONFIG_SRAM_BOOT */ diff --git a/lib/vsprintf.c b/lib/vsprintf.c index aa214dd..f28ee5b 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -665,6 +665,7 @@ int sprintf(char * buf, const char *fmt, ...) return i; } +#ifndef CONFIG_SRAM_BOOT void panic(const char *fmt, ...) { va_list args; @@ -679,3 +680,4 @@ void panic(const char *fmt, ...) do_reset (NULL, 0, 0, NULL); #endif } +#endif /* !CONFIG_SRAM_BOOT */ -- 1.7.0

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[U-Boot] Grant Notification
by UNESCO 17 Aug '10

17 Aug '10

-- United Nations Joint Programme. Division for the Promotion of basic Education Sector UNESCO 7, place de Fontenoy, F-75352 Paris 07 SP,France. Fax: +33 1 45 68 56 26/27 www.unesco.org Qualification numbers (154/4456/011). It is obvious that this notification will come to you as a surprise, Please find time to read it carefully as we congratulate you following our official publication of results of an exclusive list of 47,000,000 e-mail addresses of individual and corporate bodies picked by an advanced automated random computer ballot search from the internet as part of our international information technology enhancement programme. No tickets were sold and Applications were also made by national governments or international non-governmental organizations,maintaining formal consultative relations with UNESCO in your country. This was held on today mondayday 16th of August 2010 in Paris France. A Draft of 500,000,00(Five Hundred Thousand Great British Pounds) will be issued in your name. For Validation Purpose , Please Forward The Following Information as Listed Below to our Information and Payment bureau Officer in United Kingdom. Required Info Full Names:. Residential address:. Tel(Mobile):. Nationality/Country:. Age/Sex:.Occupation/Position: SEND DETAILS FOR VALIDATION TO: Dr Mariana Patru on:unescopayout@hotmail.com or call Tel: +447 045 726 869 Best Regards, Isabelle Le Fournis, (Press Relations Section UNESCO)

1 0

[U-Boot] [PATCHv4 CFI flash] Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips.
by Philippe De Muyter 17 Aug '10

17 Aug '10

I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30 256-Mbit 65nm flash chips. After some time :( searching for bugs in our board or soft, we have discovered that those chips have a small but annoying bug, documented in "Numonyx Axcell P33/P30 256-Mbit Specification Update" It states : When customer uses [...] block unlock, the block lock status might be altered inadvertently. Lock status might be set to either 01h or 03h unexpectedly (00h as expected data), which leads to program/erase failure on certain blocks. A working workaround is given, which I have applied and tested with success : Workaround: If the interval between 60h and its subsequent command can be guaranteed within 20μs, Option I is recommended, otherwise Option II (involves hardware) should be selected. Option I: The table below lists the detail command sequences: Command Data bus Address bus Remarks Sequence 1 90h Block Address Read Lock Status 2 Read Block Address + 02h (2)(3) (1) 3 60h Block Address (2)(3) (1) Lock/Unlock/RCR Configuration 4 D0h/01h/03h Block Address Notes: (1) Block Address refers to RCR configuration data only when the 60h command sequence is used to set RCR register combined with 03h subsequent command. (2) For the third and fourth command sequences, the Block Address must be the same. (3) The interval between 60h command and its subsequent D0h/01h/2Fh/03h commands should be less than 20μs. And here is a log comparison of a simple (destructive) flash test without and with the workaround. diff -U 50 without-numonyx-workaround.log with-numonyx-workaround.log -U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:07:47) +U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:25:19) CPU: Freescale MCF5484 CPU CLK 200 MHz BUS CLK 100 MHz Board: Macq Electronique ME2060 I2C: ready DRAM: 64 MiB FLASH: 32 MiB In: serial Out: serial Err: serial Net: FEC0, FEC1 -> flinfo Bank # 1: CFI conformant FLASH (16 x 16) Size: 32 MB in 259 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x8922 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Sector Start Addresses: FE000000 RO FE008000 RO FE010000 RO FE018000 RO FE020000 RO FE040000 RO FE060000 RO FE080000 RO FE0A0000 RO FE0C0000 RO ... FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 RO -> protect off all Un-Protect Flash Bank # 1 ................................................................................................................................................................................................................................................................... done -> erase all Erase Flash Bank # 1 ................................................................................................................................................................................................................................................................... done -> cp.b 1000000 fe000000 2000000 -Copy to Flash... Flash not Erased +Copy to Flash... done -> Signed-off-by: Philippe De Muyter <phdm(a)macqel.be> --- diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 2d09caf..809ff0e 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1348,15 +1350,32 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: - flash_write_cmd (info, sector, 0, - FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_SET); - else + /* + * see errata called + * "Numonyx Axcell P33/P30 Specification Update" :) + */ + flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID); + if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT, + prot)) { + /* + * cmd must come before FLASH_CMD_PROTECT + 20us + * Disable interrupts which might cause a timeout here. + */ + int flag = disable_interrupts (); + unsigned short cmd; + + if (prot) + cmd = FLASH_CMD_PROTECT_SET; + else + cmd = FLASH_CMD_PROTECT_CLEAR; + flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_CLEAR); + FLASH_CMD_PROTECT); + flash_write_cmd (info, sector, 0, cmd); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + } break; case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: -- Philippe De Muyter phdm at macqel dot be Tel +32 27029044 Macq Electronique SA rue de l'Aeronef 2 B-1140 Bruxelles Fax +32 27029077

2 4

[U-Boot] [u-Boot] USB EHCI for mpc512x crashes Uboot
by Einar Már Björgvinsson 17 Aug '10

17 Aug '10

Hi I'm new to this list so I hope that this is the right place for my question. I have a board with mpc5121e cpu on it and I'm been patching my Uboot (U-Boot v2009.11) with the patch given initially by Francesco Rendine: http://lists.denx.de/pipermail/u-boot/2009-June/055022.html It seems like that every time I run 'usb start' from the Uboot prompt it crashes the Uboot like: ------------ Hit any key to stop autoboot: 0 => usb start (Re)start USB... USB: U-Boot 2009.11.1-svn813 (Aug 16 2010 - 15:07:33) MPC512X CPU: MPC5121e rev. 3.0, Core e300c4 at 396 MHz, CSB at 198 MHz Board: V39 Revision B I2C: ready . . . ------------------- After some debugging it seems to be in the ehci_hcd_init(): - hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); this line makes it crash. Regards Einar

3 3

[U-Boot] [PATCH] net: Change the NFS_TIMEOUT to 20s for using nfs load image.
by Li Yang 17 Aug '10

17 Aug '10

From: Jin Qing <b24347(a)freescale.com> The NFS_TIMEOUT is 2s before. It is too short for some nfs server to respond. Signed-off-by: Jin Qing <b24347(a)freescale.com> --- We are not sure what is the expected timeout period. Using 20s to make sure the mount works. net/nfs.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/net/nfs.c b/net/nfs.c index 4017c3e..cabadfe 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -33,7 +33,7 @@ #define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ #define NFS_RETRY_COUNT 30 -#define NFS_TIMEOUT 2000UL +#define NFS_TIMEOUT 20000UL static int fs_mounted = 0; static unsigned long rpc_id = 0; -- 1.6.6-rc1.GIT

3 6

[U-Boot] [PATCH 6/7] powerpc/qe: supports loading QE firmware from nand flash
by Haiying Wang 17 Aug '10

17 Aug '10

and because some platforms need to load QE firmware from NAND flash(no NOR flash), it makes qe_init to be called after nand_init. Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- arch/powerpc/cpu/mpc83xx/cpu_init.c | 8 -------- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 -------- arch/powerpc/lib/board.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 16 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 83cba93..6d40037 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -34,8 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); -extern void qe_init(uint qe_base); -extern void qe_reset(void); static void config_qe_ioports(void) { @@ -333,12 +331,6 @@ void cpu_init_f (volatile immap_t * im) int cpu_init_r (void) { -#ifdef CONFIG_QE - uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ - - qe_init(qe_base); - qe_reset(); -#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 1fbc0cc..f799773 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -44,8 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); -extern void qe_init(uint qe_base); -extern void qe_reset(void); static void config_qe_ioports(void) { @@ -369,12 +367,6 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE - uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ - qe_init(qe_base); - qe_reset(); -#endif - #if defined(CONFIG_SYS_HAS_SERDES) /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 0e00d86..3fa865d 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -87,6 +87,15 @@ #include <miiphy.h> #endif +#ifdef CONFIG_QE +#ifdef CONFIG_SYS_QE_FW_IN_NAND +#include <nand.h> +#include <asm/errno.h> +#endif +extern void qe_init(uint qe_base); +extern void qe_reset(void); +#endif + #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE extern int update_flash_size (int flash_size); #endif @@ -631,6 +640,10 @@ void board_init_r (gd_t *id, ulong dest_addr) char *s; bd_t *bd; ulong malloc_start; +#ifdef CONFIG_SYS_QE_FW_IN_NAND + int ret; + size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; +#endif #ifndef CONFIG_SYS_NO_FLASH ulong flash_size; @@ -783,6 +796,24 @@ void board_init_r (gd_t *id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif + /* QE needs to be initialized after nand_init because some boards have + * to save QE firmware in NAND flash. + */ +#ifdef CONFIG_QE +#ifdef CONFIG_SYS_QE_FW_IN_NAND + /* load QE firmware from NAND flash to DDR first */ + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + + if (ret && ret == -EUCLEAN) { + printf ("NAND read for QE firmware at offset %x failed %d\n", + (loff_t)CONFIG_SYS_QE_FW_IN_NAND, ret); + } +#endif /* CONFIG_SYS_QE_FW_IN_NAND */ + qe_init(CONFIG_SYS_IMMR + 0x00080000); + qe_reset(); +#endif /* CONFIG_QE */ + /* relocate environment function pointers etc. */ env_relocate (); -- 1.7.0

2 3

[U-Boot] [PATCH 4/7] powerpc/p1021: Add P1021MDS board support
by Haiying Wang 17 Aug '10

17 Aug '10

This patch supports P1021MDS NAND boot with the following features: * Boot from NAND flash with SRAM BOOT support.(No NOR flash on this board) * SPD DDR Initialization Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> Signed-off-by: Mohit Kumar <Mohit.Kumar(a)freescale.com> Signed-off-by: Yu.Liu <Yu.Liu(a)freescale.com> --- MAKEALL | 1 + Makefile | 4 + board/freescale/p1021mds/Makefile | 38 ++ board/freescale/p1021mds/bcsr.c | 22 + board/freescale/p1021mds/bcsr.h | 18 + board/freescale/p1021mds/config.mk | 24 ++ board/freescale/p1021mds/ddr.c | 148 +++++++ board/freescale/p1021mds/law.c | 24 ++ board/freescale/p1021mds/p1021mds.c | 122 ++++++ board/freescale/p1021mds/pci.c | 91 +++++ board/freescale/p1021mds/tlb.c | 72 ++++ include/configs/P1021MDS.h | 536 +++++++++++++++++++++++++ nand_spl/board/freescale/p1021mds/Makefile | 117 ++++++ nand_spl/board/freescale/p1021mds/nand_boot.c | 59 +++ 14 files changed, 1276 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p1021mds/Makefile create mode 100644 board/freescale/p1021mds/bcsr.c create mode 100644 board/freescale/p1021mds/bcsr.h create mode 100644 board/freescale/p1021mds/config.mk create mode 100644 board/freescale/p1021mds/ddr.c create mode 100644 board/freescale/p1021mds/law.c create mode 100644 board/freescale/p1021mds/p1021mds.c create mode 100644 board/freescale/p1021mds/pci.c create mode 100644 board/freescale/p1021mds/tlb.c create mode 100644 include/configs/P1021MDS.h create mode 100644 nand_spl/board/freescale/p1021mds/Makefile create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c diff --git a/MAKEALL b/MAKEALL index b34ae33..f14c955 100755 --- a/MAKEALL +++ b/MAKEALL @@ -428,6 +428,7 @@ LIST_85xx=" \ P2020RDB_NAND \ P2020RDB_SDCARD \ P2020RDB_SPIFLASH \ + P1021MDS_NAND \ P4080DS \ PM854 \ PM856 \ diff --git a/Makefile b/Makefile index b1d92b7..7bfa733 100644 --- a/Makefile +++ b/Makefile @@ -1809,6 +1809,10 @@ P2020RDB_SDCARD_config \ P2020RDB_SPIFLASH_config: unconfig @$(MKCONFIG) -n $@ -t $@ P1_P2_RDB powerpc mpc85xx p1_p2_rdb freescale +P1021MDS_config \ +P1021MDS_NAND_config: unconfig + @$(MKCONFIG) -n $@ -t $@ P1021MDS powerpc mpc85xx p1021mds freescale + sbc8540_config \ sbc8540_33_config \ sbc8540_66_config: unconfig diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile new file mode 100644 index 0000000..bb744f0 --- /dev/null +++ b/board/freescale/p1021mds/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2010 Freescale Semiconductor, Inc. +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += bcsr.o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-y += pci.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1021mds/bcsr.c b/board/freescale/p1021mds/bcsr.c new file mode 100644 index 0000000..6daf690 --- /dev/null +++ b/board/freescale/p1021mds/bcsr.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#include <common.h> +#include <asm/io.h> + +#include "bcsr.h" + +#define BCSR11_ENET_MICRST 0x20 + +void reset_p1021mds_micrel_phy(void) +{ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); +} diff --git a/board/freescale/p1021mds/bcsr.h b/board/freescale/p1021mds/bcsr.h new file mode 100644 index 0000000..f3e47d4 --- /dev/null +++ b/board/freescale/p1021mds/bcsr.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#ifndef __BCSR_H_ +#define __BCSR_H_ + +#include <common.h> + +/*BCSR Utils functions*/ +void reset_p1021mds_micrel_phy(void); +#endif /* __BCSR_H_ */ diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk new file mode 100644 index 0000000..b2019d3 --- /dev/null +++ b/board/freescale/p1021mds/config.mk @@ -0,0 +1,24 @@ +# +# Copyright (C) 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# p1021mds board +# + +ifdef SRAM_BOOT +TEXT_BASE := 0xf8f81000 +PAD_TO := 0xf8f8c000 +endif + +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +ifndef SRAM_BOOT +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +endif +endif +endif diff --git a/board/freescale/p1021mds/ddr.c b/board/freescale/p1021mds/ddr.c new file mode 100644 index 0000000..0efa9bb --- /dev/null +++ b/board/freescale/p1021mds/ddr.c @@ -0,0 +1,148 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) +{ + int ret; + + /* + * The P1021 only has one DDR controller, and the P1021MDS board has + * only one DIMM slot. + */ + + ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd, + sizeof(ddr3_spd_eeprom_t)); + + if (ret) { + debug("DDR: failed to read SPD from address %u\n", + SPD_EEPROM_ADDRESS1); + memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t)); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + */ + popts->clk_adjust = 6; + + /* + * Factors to consider for CPO: + */ + popts->cpo_override = 0x1f; + + /* + * Factors to consider for write data delay: + */ + popts->write_data_delay = 2; + + /* + * Factors to consider for half-strength driver enable: + */ + popts->half_strength_driver_enable = 1; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_40_OHM; /* 40 Ohm rtt */ + popts->rtt_wr_override_value = 2; /* Rtt_WR */ + + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x8; + /* + * P1021 supports max 32-bit DDR width + */ + popts->data_bus_width = 1; + + /* + * disable on-the-fly burst chop mode for 32 bit data bus + */ + popts->OTF_burst_chop_en = 0; + + /* + * Set fixed 8 beat burst for 32 bit data bus + */ + popts->burst_length = DDR_BL8; +} + +phys_size_t fixed_sdram(void) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + u32 temp_sdram_cfg; + + set_next_law(0 , LAW_SIZE_512M , LAW_TRGT_IF_DDR_1); + + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&ddr->cs0_config_2, CONFIG_SYS_DDR_CS0_CONFIG_2); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); + out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); + out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_1); + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); + + sync(); + isync(); + + udelay(500); + + /* Let the controller go */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + + return 512 * 1024 * 1024; +} + +phys_size_t init_ddr_dram(void) +{ + phys_size_t dram_size = 0; +#ifdef CONFIG_SPD_EEPROM + dram_size = fsl_ddr_sdram(); +#else + dram_size = fixed_sdram(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts("\n DDR: "); + return dram_size; +} diff --git a/board/freescale/p1021mds/law.c b/board/freescale/p1021mds/law.c new file mode 100644 index 0000000..bb9d92e --- /dev/null +++ b/board/freescale/p1021mds/law.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c new file mode 100644 index 0000000..c61c902 --- /dev/null +++ b/board/freescale/p1021mds/p1021mds.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <hwconfig.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/io.h> +#include <asm/mp.h> +#include <i2c.h> +#include <ioports.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <tsec.h> +#include <netdev.h> + +const char *board_hwconfig = "foo:bar=baz"; +const char *cpu_hwconfig = "foo:bar=baz"; + +int board_early_init_f(void) +{ + + fsl_lbc_t *lbc = LBC_BASE_ADDR; + +#ifdef CONFIG_MMC + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); +#endif + + /* Set ABSWP to implement conversion of addresses in the LBC */ + setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + + return 0; +} + +int checkboard(void) +{ + printf("Board: P1021 MDS\n"); + + return 0; +} + +phys_size_t initdram(int board_type) +{ + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[3]; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif + +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII3_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_pci_board_setup(void *blob); + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, base, size); + + ft_pci_board_setup(blob); + +} +#endif +; +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/p1021mds/pci.c b/board/freescale/p1021mds/pci.c new file mode 100644 index 0000000..2a19ae5 --- /dev/null +++ b/board/freescale/p1021mds/pci.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <hwconfig.h> +#include <pci.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif /* CONFIG_PCIE2 */ + +void pci_init_board(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + printf(" eTSEC2 is in sgmii mode.\n"); + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf(" eTSEC3 is in sgmii mode.\n"); + + puts("\n"); +#ifdef CONFIG_PCIE1 + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf(" PCIE1: disabled\n"); + } + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ +#endif /* CONFIG_PCIE1 */ + +#ifdef CONFIG_PCIE2 + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + + } else { + printf(" PCIE2: disabled\n"); + } + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ +#endif /* CONFIG_PCIE2 */ +} + +void ft_pci_board_setup(void *blob) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c new file mode 100644 index 0000000..66ec22a --- /dev/null +++ b/board/freescale/p1021mds/tlb.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - PCIE */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCIE I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1M, 1), + + /* + * *I*G BCSR/PMC0/PMC1 + */ + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), + +#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SRAM_BOOT) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h new file mode 100644 index 0000000..6f63aac --- /dev/null +++ b/include/configs/P1021MDS.h @@ -0,0 +1,536 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +/* + * p1021mds board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/68/P1021 */ +#define CONFIG_P1021 /* P1021 silicon support */ +#define CONFIG_P1021MDS /* P1021MDS board specific */ +#define CONFIG_MP /* Multiprocessor support */ + +#define CONFIG_FSL_ELBC /* Has Enhance localbus controller */ + +#define CONFIG_PCI /* Disable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controller */ +#define CONFIG_PCIE2 /* PCIE controller */ +#define CONFIG_FSL_PCI_INIT /* use common fsl pci init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_TSEC_ENET /* tsec ethernet support */ + +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT +#define CONFIG_MIDDLE_STAGE_SRAM_BOOT +#define CONFIG_RAMBOOT_NAND +#define CONFIG_RAMBOOT_TEXT_BASE 0x01001000 +#endif + +/* Replace a call to get_clock_freq (after it is implemented)*/ +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff + +#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of + addresses in the LBC */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR + /* physical addr of CCSRBAR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + /* PQII uses CONFIG_SYS_IMMR */ + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 + /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ + +/* These are used when DDR doesn't use SPD. */ +#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 +#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x86559608 +#define CONFIG_SYS_DDR_CDR_1 0x000eaa00 +#define CONFIG_SYS_DDR_CDR_2 0x00000000 +#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 +#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0x470c0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 +#define CONFIG_SYS_DDR_DATA_INIT 0x1021babe +#define CONFIG_SYS_DDR_TIMING_3 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1 0x5d5bd746 +#define CONFIG_SYS_DDR_TIMING_2 0x0fa8c8cd +#define CONFIG_SYS_DDR_SDRAM_MODE 0x40461320 +#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 +#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x0a280000 +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00010000 + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + + +/* + * Memory map + * + * 0x0000_0000 0x1fff_ffff DDR3 512MB cacheable + * 0xa000_0000 0xbfff_ffff PCIE2 Mem 512MB non-cacheable + * 0xc000_0000 0xdfff_ffff PCIE1 Mem 512MB non-cacheable + * 0xffc1_0000 0xffc1_ffff PCIE2 IO range 64K non-cacheable + * 0xffc2_0000 0xffc2_ffff PCIE1 IO range 64K non-cacheable + * 0xf800_0000 0xf800_7fff BCSR on CS1 32KB non-cacheable + * 0xf801_0000 0xf801_ffff PMC1 on CS2 64KB non-cacheable + * 0xf802_0000 0xf802_ffff PMC0 on CS3 64KB non-cacheable + * 0xfc00_0000 0xfdff_ffff NAND on CS0 32MB non-cacheable + * 0xffe0_0000 0xffef_ffff CCSRBAR 1M + */ + + +/* + * Local Bus Definitions + */ + +#define CONFIG_SYS_BCSR_BASE 0xf8000000 +#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE + +#define CONFIG_SYS_PIB_PMC1_BASE 0xf8010000 + /* start of PIB-QOC3(PMC1) 64K */ +#define CONFIG_SYS_PIB_PMC1_BASE_PHYS CONFIG_SYS_PIB_PMC1_BASE + +#define CONFIG_SYS_PIB_PMC0_BASE 0xf8020000 + /* start of PIB-T1/E1(PMC0) 64K */ +#define CONFIG_SYS_PIB_PMC0_BASE_PHYS CONFIG_SYS_PIB_PMC0_BASE + +/* chip select 1 - BCSR*/ +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \ + | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \ + | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + +/* chip select 2 - PIB(QOC3-PMC1)*/ +#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC1_BASE_PHYS) \ + | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \ + | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + +/* chip select 3 - PIB(T1/E1-PMC0)*/ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC0_BASE_PHYS) \ + | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \ + | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_NO_FLASH + +#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) \ + || defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xFC000000 +#endif +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +/* NAND boot: 4K NAND loader config */ +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (48 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#ifdef CONFIG_SRAM_BOOT +/* Sram boot: 48K middle stage uboot config*/ +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x01000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x01000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (64 << 10) +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + \ + (128 << 10)) +#endif + +/* NAND FLASH CONFIG */ +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) +/* chip select 0 - NAND */ +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL_MULTI +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +/* Use the HUSH parser*/ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_64BIT_STRTOUL + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* TSEC support */ +#if defined(CONFIG_TSEC_ENET) + +/* TSECV2 */ +#define CONFIG_TSECV2 + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHYIDX 0 + +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_SGMII) +#define TSEC2_PHYIDX 0 + +#ifdef CONFIG_TSEC3_IN_SGMII /* Need to set SW8.6 to 0 */ +#define TSEC3_PHY_ADDR 6 +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_SGMII) +#else +#define TSEC3_PHY_ADDR 1 +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#endif +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 + +#define PLPPAR1_I2C_BIT_MASK 0x0000000F +#define PLPPAR1_I2C2_VAL 0x00000000 +#define PLPPAR1_ESDHC_VAL 0x0000000A +#define PLPDIR1_I2C_BIT_MASK 0x0000000F +#define PLPDIR1_I2C2_VAL 0x0000000F +#define PLPDIR1_ESDHC_VAL 0x00000006 + +/* + * General PCI + * Memory Addresses are mapped 1-1. I/O is mapped from 0 + */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64K */ + +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ + +#if defined(CONFIG_PCI) +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (576 * 1024) +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) + /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_HOSTNAME p1021mds +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=your.fdt.dtb\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "run nfsargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "run ramargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/freescale/p1021mds/Makefile b/nand_spl/board/freescale/p1021mds/Makefile new file mode 100644 index 0000000..2e88d72 --- /dev/null +++ b/nand_spl/board/freescale/p1021mds/Makefile @@ -0,0 +1,117 @@ +# +# Copyright (C) 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff04000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/arch/powerpc/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/p1021mds/nand_boot.c b/nand_spl/board/freescale/p1021mds/nand_boot.c new file mode 100644 index 0000000..18898a9 --- /dev/null +++ b/nand_spl/board/freescale/p1021mds/nand_boot.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include <common.h> +#include <mpc85xx.h> +#include <asm/io.h> +#include <ns16550.h> +#include <nand.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + uint plat_ratio, bus_clk, sys_clk = 0; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + sys_clk = CONFIG_SYS_CLK_FREQ; + + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = plat_ratio * sys_clk; + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + /* copy code to DDR and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} -- 1.7.0

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[U-Boot] [PATCHv3 CFI flash] Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips.
by Philippe De Muyter 17 Aug '10

17 Aug '10

I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30 256-Mbit 65nm flash chips. After some time :( searching for bugs in our board or soft, we have discovered that those chips have a small but annoying bug, documented in "Numonyx Axcell P33/P30 256-Mbit Specification Update" It states : When customer uses [...] block unlock, the block lock status might be altered inadvertently. Lock status might be set to either 01h or 03h unexpectedly (00h as expected data), which leads to program/erase failure on certain blocks. A working workaround is given, which I have applied and tested with success : Workaround: If the interval between 60h and its subsequent command can be guaranteed within 20μs, Option I is recommended, otherwise Option II (involves hardware) should be selected. Option I: The table below lists the detail command sequences: Command Data bus Address bus Remarks Sequence 1 90h Block Address Read Lock Status 2 Read Block Address + 02h (2)(3) (1) 3 60h Block Address (2)(3) (1) Lock/Unlock/RCR Configuration 4 D0h/01h/03h Block Address Notes: (1) Block Address refers to RCR configuration data only when the 60h command sequence is used to set RCR register combined with 03h subsequent command. (2) For the third and fourth command sequences, the Block Address must be the same. (3) The interval between 60h command and its subsequent D0h/01h/2Fh/03h commands should be less than 20μs. And here is a log comparison of a simple (destructive) flash test without and with the workaround. diff -U 50 without-numonyx-workaround.log with-numonyx-workaround.log --- without-numonyx-workaround.log 2010-08-16 15:32:34.000000000 +0200 +++ with-numonyx-workaround.log 2010-08-16 15:32:55.000000000 +0200 @@ -1,33 +1,33 @@ -U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:07:47) +U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:25:19) CPU: Freescale MCF5484 CPU CLK 200 MHz BUS CLK 100 MHz Board: Macq Electronique ME2060 I2C: ready DRAM: 64 MiB FLASH: 32 MiB In: serial Out: serial Err: serial Net: FEC0, FEC1 -> flinfo Bank # 1: CFI conformant FLASH (16 x 16) Size: 32 MB in 259 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x8922 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Sector Start Addresses: FE000000 RO FE008000 RO FE010000 RO FE018000 RO FE020000 RO FE040000 RO FE060000 RO FE080000 RO FE0A0000 RO FE0C0000 RO ... FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 RO -> protect off all Un-Protect Flash Bank # 1 ................................................................................................................................................................................................................................................................... done -> erase all Erase Flash Bank # 1 ................................................................................................................................................................................................................................................................... done -> cp.b 1000000 fe000000 2000000 -Copy to Flash... Flash not Erased +Copy to Flash... done -> Signed-off-by: Philippe De Muyter <phdm(a)macqel.be> --- diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 2d09caf..809ff0e 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1348,15 +1350,32 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: case CFI_CMDSET_INTEL_EXTENDED: - flash_write_cmd (info, sector, 0, - FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_SET); - else + /* + * see errata called + * "Numonyx Axcell P33/P30 Specification Update" :) + */ + flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID); + if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT, + prot)) { + /* + * cmd must come before FLASH_CMD_PROTECT + 20us + * Disable interrupts which might cause a timeout here. + */ + int flag = disable_interrupts (); + unsigned short cmd; + + if (prot) + cmd = FLASH_CMD_PROTECT_SET; + else + cmd = FLASH_CMD_PROTECT_CLEAR; + flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_CLEAR); + FLASH_CMD_PROTECT); + flash_write_cmd (info, sector, 0, cmd); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + } break; case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: -- Philippe De Muyter phdm at macqel dot be Tel +32 27029044 Macq Electronique SA rue de l'Aeronef 2 B-1140 Bruxelles Fax +32 27029077

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