August 2010 - U-Boot

[U-Boot] Persönliche Informationen für Sie
by gilberttalaki1＠terra.es 19 Aug '10

19 Aug '10

Lieber Freund, Ich bin Barrister Talaki Gilbert, einem Rechtsanwalt und ich würde gerne mit Ihnen teilen, ein sehr wichtiges Geschäft Satz, daß der gegenseitige Nutzen für beide von uns werden. Ein verstorbener Klient von mir, dass die Aktien den gleichen Nachnamen wie Sie, der hier nach, wird als mein verstorbener Client bezeichnet werden, auf den 1. Oktober 2006 starb, er und seine Frau und seine einzige Tochter war in einen Autounfall verwickelt, während Reise in ein benachbartes Land auf Urlaub. Um das Beste aus meinem Wissen, vor seinem Tod hatte er eine Investition Anzahlung in Höhe von insgesamt mehr als US9.4M (9,4 Millionen US-Dollar) mit der Großbank hier und jetzt haben sie mich gebeten, einen nächsten Angehörigen, wenn oder gibt es das Weingut wird dann wieder an die Regierung und so verloren gehen würde. Mein Vorschlag ist, dass man für diese Rolle vorgestellt werden können, so dass Unterlagen können bearbeitet werden und die Zahlung zu Ihren Gunsten aus. Bitte beachten Sie meine persönliche E-Mail hinzuzufügen Antwort: gilberttalaki(a)hotmail.fr Mit freundlichen Grüßen, Barrister Gilbert Talaki Principal Attorney

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[U-Boot] [PATCH] coldfire m68k/mcf547x_8x : Fix relocation errors in start.S
by Philippe De Muyter 19 Aug '10

19 Aug '10

When the environment sectors in the flash are big, one get those errors : mcf547x_8x/start.S:173: relocation truncated to fit: R_68K_PC16 against symbol `cpu_init_f' defined in .text section in libmcf547x_8x.a(cpu_init.o) mcf547x_8x/start.S:174: relocation truncated to fit: R_68K_PC16 against symbol `board_init_f' defined in .text section in libm68k.a(board.o) Fix that. Signed-off-by: Philippe De Muyter <phdm(a)macqel.be> --- arch/m68k/cpu/mcf547x_8x/start.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index 8411862..80905ed 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -164,8 +164,8 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ + jbsr cpu_init_f /* run low-level CPU init code (from flash) */ + jbsr board_init_f /* run low-level board init code (from flash) */ /* board_init_f() does not return */ -- 1.6.3.3

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[U-Boot] [PATCH v3 2/2] TI: DaVinci DA850 EVM: support passing maximum allowed cpu clock rate information to kernel
by Sekhar Nori 19 Aug '10

19 Aug '10

The TI DA850/OMAP-L138/AM18x EVM can be populated with devices having different maximum allowed CPU clock rating. The maximum clock the chip can support can only be determined from the label on the package (not software readable). Introduce a method to pass the maximum allowed clock rate information to kernel using ATAG_REVISION. The kernel uses this information to determine the maximum cpu clock rate reachable using cpufreq. Note that U-Boot itself does not set the CPU clock rate. The CPU clock is setup by a primary bootloader ("UBL"). The rate setup by UBL could be different from the maximum clock rate supported by the device. Signed-off-by: Sekhar Nori <nsekhar(a)ti.com> --- Changes in v3: a) renamed maxspeed to maxcpuclk b) add information regarding the new environment variable in README.davinci c) use if-else instead of switch to check for value range rather than specific values of maxcpuclk d) change comment to document values returned in bit[0-3] by get_board_rev() in binary board/davinci/da8xxevm/da850evm.c | 33 +++++++++++++++++++++++++++++++++ doc/README.davinci | 13 +++++++++++++ include/configs/da850evm.h | 1 + 3 files changed, 47 insertions(+), 0 deletions(-) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index eeb456c..266c4d8 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -70,6 +70,39 @@ static const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_GPIO }, }; +#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK +#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 +#endif + +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] Maximum cpu clock rate supported by onboard SoC + * 0000b - 300 MHz + * 0001b - 372 MHz + * 0010b - 408 MHz + * 0011b - 456 MHz + */ +u32 get_board_rev(void) +{ + char *s; + u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; + u32 rev = 0; + + s = getenv("maxcpuclk"); + if (s) + maxcpuclk = simple_strtoul(s, NULL, 10); + + if (maxcpuclk >= 456000000) + rev = 3; + else if (maxcpuclk >= 408000000) + rev = 2; + else if (maxcpuclk >= 372000000) + rev = 1; + + return rev; +} + int board_init(void) { #ifndef CONFIG_USE_IRQ diff --git a/doc/README.davinci b/doc/README.davinci index a2e96a5..3e624ee 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -95,6 +95,19 @@ into the RAM. The programmers and UBL are always released as part of any standard TI software release associated with an SOC. +Environment Variables +===================== + +The DA850 EVM allows the user to specify the maximum cpu clock allowed by the +silicon, in Hz, via an environment variable "maxcpuclk". + +The maximum clock rate allowed depends on the silicon populated on the EVM. +Please make sure you understand the restrictions placed on this clock in the +device specific datasheet before setting up this variable. + +If "maxcpuclk" is not defined, the configuration CONFIG_DA850_EVM_MAX_CPU_CLK +is used to obtain this information. + Links ===== diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 357715d..3ea9032 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -102,6 +102,7 @@ */ #define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) #define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS \ "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" -- 1.6.2.4

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[U-Boot] Please pull u-boot-mpc85xx.git
by Kumar Gala 19 Aug '10

19 Aug '10

The following changes since commit bd2313078114c4b44c4a5ce149af43bcb7fc8854: Wolfgang Denk (1): Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master are available in the git repository at: git://git.denx.de/u-boot-mpc85xx master Kim Phillips (1): powerpc/8xxx: share PIC defines among 85xx and 86xx Kumar Gala (2): powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs powerpc/83xx: Fix build issue with ve8313 board due to lbus changes Lian Minghuan (1): powerpc/85xx: Fix SRIO LAW setup on corenet_ds boards york (1): powerpc/8xxx: Fix quad-rank DIMMs support on corenet_ds board. arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 6 ++-- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 8 ++-- arch/powerpc/cpu/mpc85xx/traps.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 8 +++-- arch/powerpc/include/asm/fsl_liodn.h | 8 ++-- arch/powerpc/include/asm/immap_85xx.h | 10 ++---- arch/powerpc/include/asm/immap_86xx.h | 9 ++++-- board/freescale/corenet_ds/corenet_ds.c | 47 ++++++++++++++++-------------- board/freescale/corenet_ds/ddr.c | 18 +++++++++++- board/ve8313/ve8313.c | 2 +- drivers/mtd/nand/fsl_elbc_nand.c | 4 ++- include/configs/corenet_ds.h | 2 +- include/configs/ve8313.h | 1 + 16 files changed, 78 insertions(+), 53 deletions(-)

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[U-Boot] [PATCH] powerpc/85xx: Fix SRIO LAW setup on corenet_ds boards
by Kumar Gala 19 Aug '10

19 Aug '10

From: Lian Minghuan <B31939(a)freescale.com> In funciton board_early_init_r(), serdes does not initialize yet. variable "serdes_prtcl_map" in function is_serdes_configured() does not initialize. sRIO will always be disable. In the original code, there is a undefined variable gur if SRIO is not defined. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Lian Minghuan <B31939(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/corenet_ds/corenet_ds.c | 47 ++++++++++++++++-------------- 1 files changed, 25 insertions(+), 22 deletions(-) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3cdefb3..48d95d6 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> #include <netdev.h> +#include <linux/compiler.h> #include <asm/mmu.h> #include <asm/processor.h> #include <asm/cache.h> @@ -120,28 +121,6 @@ int board_early_init_r(void) set_liodns(); setup_portals(); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - return 0; } @@ -164,10 +143,34 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_SRIO1 + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_1); + } else { + printf (" SRIO1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ +#endif + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_2); + } else { + printf (" SRIO2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ +#endif + /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. -- 1.6.0.6

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[U-Boot] commit f51cdaf1 breaks ve8313 board
by Wolfgang Denk 19 Aug '10

19 Aug '10

Dear Becky, your commit f51cdaf1: "83xx/85xx/86xx: LBC register cleanup" breaks building of the ve8313 board which now fails like this: fsl_elbc_nand.c: In function 'fsl_elbc_run_command': fsl_elbc_nand.c:231: error: 'fsl_lbc_t' has no member named 'lsor' make[1]: *** [/work/wd/tmp-ppc/drivers/mtd/nand/fsl_elbc_nand.o] Error 1 Please fix. Thanks in advance. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Einstein argued that there must be simplified explanations of nature, because God is not capricious or arbitrary. No such faith comforts the software engineer. - Fred Brooks, Jr.

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[U-Boot] [PATCH] powerpc/8xxx: Fix quad-rank DIMMs support on corenet_ds board.
by Kumar Gala 19 Aug '10

19 Aug '10

From: york <yorksun(a)freescale.com> The board specific parameters associated with quad rank dimms where missing. This fixes it so the board will function if quad rank dimms are placed in it. Signed-off-by: York Sun <yorksun(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/corenet_ds/ddr.c | 18 +++++++++++++++++- include/configs/corenet_ds.h | 2 +- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 82b2b4f..18adf2f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -66,11 +66,19 @@ typedef struct { * seem reliable, but errors will appear when memory intensive * program is run. */ /* XXX: Single rank at 800 MHz is OK. */ -const board_specific_parameters_t board_specific_parameters[][20] = { +const board_specific_parameters_t board_specific_parameters[][30] = { { /* memory controller 0 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, @@ -90,6 +98,14 @@ const board_specific_parameters_t board_specific_parameters[][20] = { /* memory controller 1 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index dd609da..3dcee85 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -124,7 +124,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -- 1.6.0.6

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[U-Boot] [PATCH] powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs
by Kumar Gala 19 Aug '10

19 Aug '10

Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 8 ++++---- arch/powerpc/include/asm/fsl_liodn.h | 8 ++++---- arch/powerpc/include/asm/immap_85xx.h | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 3861146..a6cfaa5 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -81,10 +81,10 @@ struct liodn_id_table fman2_liodn_tbl[] = { #endif struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JQ_LIODN_ENTRY(0, 146, 154), - SET_SEC_JQ_LIODN_ENTRY(1, 147, 155), - SET_SEC_JQ_LIODN_ENTRY(2, 178, 186), - SET_SEC_JQ_LIODN_ENTRY(3, 179, 187), + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), + SET_SEC_JR_LIODN_ENTRY(1, 147, 155), + SET_SEC_JR_LIODN_ENTRY(2, 178, 186), + SET_SEC_JR_LIODN_ENTRY(3, 179, 187), SET_SEC_RTIC_LIODN_ENTRY(a, 144), SET_SEC_RTIC_LIODN_ENTRY(b, 145), SET_SEC_RTIC_LIODN_ENTRY(c, 176), diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index acdc99a..4c17fe2 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -115,11 +115,11 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ -#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \ - SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\ - offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \ +#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum) + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index e5a02c3..3dd2b7f 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2063,7 +2063,7 @@ typedef struct ccsr_sec { struct { u32 ms; /* Job Ring LIODN Register, MS */ u32 ls; /* Job Ring LIODN Register, LS */ - } jqliodnr[4]; + } jrliodnr[4]; u8 res2[0x30]; struct { u32 ms; /* RTIC LIODN Register, MS */ @@ -2108,8 +2108,8 @@ typedef struct ccsr_sec { #define SEC_CTPR_MS_AXI_LIODN 0x08000000 #define SEC_CTPR_MS_QI 0x02000000 #define SEC_RVID_MA 0x0f000000 -#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 -#define SEC_CHANUM_MS_JQNUM_SHIFT 28 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 #endif -- 1.6.0.6

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[U-Boot] Debugging why my kernel won't start
by Rogan Dawes 19 Aug '10

19 Aug '10

Hi folks, I'm trying to get mainline u-boot working on my DNS323 (Orion5x based). Until I am confident in the config, I'm using a chainloaded approach, wrapping my featureful u-boot in an image file: $ mkimage -A arm -O u-boot -T kernel -C none -a 0x3000000 -e 0x3000000 -n "UBoot dns323" -d u-boot.bin uImage.bin I am trying to boot the default kernel that is already flashed into the device first. The first problem is that the DNS323 uses an incorrect mach-type value of 526, while the registered value is 1542. See <http://wiki.dns323.info/software:kernel>). I have modified arch/arm/include/asm/mach-types.h to set MACH_TYPE_DNS323 to the "correct" Dlink value, which should match what the default kernel is expecting. Unfortunately, all I get is: DNS323B1> bootm FF820000 ## Booting kernel from Legacy Image at ff820000 ... Image Name: Linux-2.6.12.6-arm1 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1490204 Bytes = 1.4 MiB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK Loading Kernel Image ... and it hangs there. That appears to be this code from cmd_bootm: case IH_COMP_NONE: if (load == blob_start) { printf (" XIP %s ... ", type_name); } else { printf (" Loading %s ... ", type_name); memmove_wd ((void *)load, (void *)image_start, image_len, CHUNKSZ); } *load_end = load + image_len; puts("OK\n"); break; So, the memmove_wd never completes, it seems. I added a debug statement at the top of memmove_wd, and got: Moving memory from ff820040 to 00008000 Is that because the uImage header is 64 bytes? Also, the following suggests that there may be something wrong with the addresses that I am using: DNS323B1> bootm FF820000 FF9A0000 ## Booting kernel from Legacy Image at ff820000 ... Image Name: Linux-2.6.12.6-arm1 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1490204 Bytes = 1.4 MiB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at ff9a0000 ... Image Name: Ramdisk Image Type: ARM Linux RAMDisk Image (gzip compressed) Data Size: 5240600 Bytes = 5 MiB Load Address: 00800000 Entry Point: 00800000 Verifying Checksum ... Bad Data CRC Ramdisk image is corrupt or invalid DNS323B1> My chainloaded u-boot is configured in an image to load at 0x3000000, and stay there (no relocation), if I have understood these parameters correctly: -a 0x3000000 -e 0x3000000 Can anyone see what I am doing wrong? Many thanks! Rogan

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[U-Boot] commit a37c36f4 breaks several non-85xx boards
by Wolfgang Denk 19 Aug '10

19 Aug '10

Dear Kim, your commit a37c36f4: "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" breaks a number of boards with error messages like here: cpu.c: In function 'cpu_numcores': cpu.c:113: error: 'CONFIG_SYS_MPC85xx_PIC_ADDR' undeclared (first use in this function) cpu.c:113: error: (Each undeclared identifier is reported only once cpu.c:113: error: for each function it appears in.) cpu.c:118: error: 'MPC85xx_PICFRR_NCPU_MASK' undeclared (first use in this function) cpu.c:119: error: 'MPC85xx_PICFRR_NCPU_SHIFT' undeclared (first use in this function) make[1]: *** [/work/wd/tmp-ppc/arch/powerpc/cpu/mpc8xxx/cpu.o] Error 1 make: *** [/work/wd/tmp-ppc/arch/powerpc/cpu/mpc8xxx/lib8xxx.a] Error 2 Affected board configurations: MPC8610HPCD, MPC8641HPCN, MPC8641HPCN_36BIT, XPEDITE5170, sbc8641d. Please fix. Thanks in advance. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Another war ... must it always be so? How many comrades have we lost in this way? ... Obedience. Duty. Death, and more death ... -- Romulan Commander, "Balance of Terror", stardate 1709.2

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