August 2010 - U-Boot

[U-Boot] [PATCH] MXC: Add watchdog support to serial driver
by Stefano Babic 20 Aug '10

20 Aug '10

Calls WATCHDOG_RESET() inside serial driver for boards enabling watchdog. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- drivers/serial/serial_mxc.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 4b93e7b..110bd15 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -18,6 +18,7 @@ */ #include <common.h> +#include <watchdog.h> #ifdef CONFIG_MX31 #include <asm/arch/mx31.h> #else @@ -189,7 +190,8 @@ void serial_setbrg (void) int serial_getc (void) { - while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + WATCHDOG_RESET(); return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ } @@ -198,7 +200,8 @@ void serial_putc (const char c) __REG(UART_PHYS + UTXD) = c; /* wait for transmitter to be ready */ - while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); + while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + WATCHDOG_RESET(); /* If \n, also do \r */ if (c == '\n') -- 1.6.3.3

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[U-Boot] [PATCH] MX51: Added pins definition to set up pads
by Stefano Babic 20 Aug '10

20 Aug '10

Add pins definitions to set up RAM pads. Pins have only a pad, there is no entry in the multiplexer. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-mx51/mx51_pins.h | 44 ++++++++++++++++++++++++++++ 1 files changed, 44 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx51/mx51_pins.h index ca26f41..b44ff25 100644 --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h +++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h @@ -368,6 +368,50 @@ enum iomux_pins { MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), + + /* The following are PADS used for drive strength */ + + MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820), + MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838), + MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890), + MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C), + MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C), + MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884), + MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C), + MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864), + MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C), + MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874), + MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878), + MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880), + MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C), + MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C), + MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4), + MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC), + MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8), + MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C), + MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0), + MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0), + MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4), + MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC), + MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C), + MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848), + MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868), + MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4), + MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8), + MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac), + MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0), + MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4), + MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8), + MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC), + MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0), + MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4), + MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8), + MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC), + MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0), + MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4), + MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8), + MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC), + MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), }; #endif /* __ASSEMBLY__ */ -- 1.6.3.3

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[U-Boot] [PATCH] ARM: Use syslib functions for all CORTEXA8
by Stefano Babic 20 Aug '10

20 Aug '10

The OMAP3 cpu directory contains a syslib file with some utilities that can be shared by all targets using arm cortexa8 processors, not only OMAP. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/armv7/Makefile | 3 +- arch/arm/cpu/armv7/omap3/Makefile | 1 - arch/arm/cpu/armv7/omap3/syslib.c | 72 ---------------------------- arch/arm/cpu/armv7/syslib.c | 69 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx51/sys_proto.h | 1 + 5 files changed, 72 insertions(+), 74 deletions(-) delete mode 100644 arch/arm/cpu/armv7/omap3/syslib.c create mode 100644 arch/arm/cpu/armv7/syslib.c diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ae20299..de4b065 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(CPU).a START := start.o COBJS := cpu.o +COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -44,4 +45,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -######################################################################### \ No newline at end of file +######################################################################### diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 79ae267..95526d6 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -32,7 +32,6 @@ COBJS += board.o COBJS += clock.o COBJS += gpio.o COBJS += mem.o -COBJS += syslib.o COBJS += sys_info.o COBJS-$(CONFIG_EMIF4) += emif4.o diff --git a/arch/arm/cpu/armv7/omap3/syslib.c b/arch/arm/cpu/armv7/omap3/syslib.c deleted file mode 100644 index 9ced495..0000000 --- a/arch/arm/cpu/armv7/omap3/syslib.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * - * Richard Woodruff <r-woodruff2(a)ti.com> - * Syed Mohammed Khasim <khasim(a)ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = readl((u32)addr) & ~(msk << start_bit); - tmp |= value << start_bit; - writel(tmp, (u32)addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, - u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = readl((u32)read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c new file mode 100644 index 0000000..84d17f0 --- /dev/null +++ b/arch/arm/cpu/armv7/syslib.c @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = readl((u32)addr) & ~(msk << start_bit); + tmp |= value << start_bit; + writel(tmp, (u32)addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = readl((u32)read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx51/sys_proto.h index bf500a8..f687503 100644 --- a/arch/arm/include/asm/arch-mx51/sys_proto.h +++ b/arch/arm/include/asm/arch-mx51/sys_proto.h @@ -26,5 +26,6 @@ u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); #endif -- 1.6.3.3

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[U-Boot] [PATCH 0/4] Add support for PRTLVT2 boards
by David Jander 20 Aug '10

20 Aug '10

The following patches add support for PRTLVT2 based boards (i.MX515 SoC). [PATCH 1/4] MX51: iomux: Added support for mxc_iomux_set_input() [PATCH 2/4] MX51: Added missing pin definition [PATCH 3/4] mc13982 driver: corrected/added some definitions according to latest user-manual [PATCH 4/4] Added initial support for PRTLVT2-based boards. Signed-off-by: David Jander <david(a)protonic.nl>

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[U-Boot] [PATCH] Align linebuf to avoid misaligned aliases of it
by Albert Aribaud 20 Aug '10

20 Aug '10

Commit 64419e47518bbba059c80b77558f93ad4804145c aliases the uint16_t usp and uint32_t uip variables in print_buffer() to uint8_t variable linebuf without aligning it to an uint32_t address, thus causing data aborts on ARM when doing md.l on 32-bit wide area (and probably 16-bit wide as well). Aligning linebuf fixes the issue. Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- lib/display_options.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/lib/display_options.c b/lib/display_options.c index 20319e6..c544777 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -101,7 +101,8 @@ void print_size(unsigned long long size, const char *s) #define DEFAULT_LINE_LENGTH_BYTES (16) int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen) { - uint8_t linebuf[MAX_LINE_LENGTH_BYTES + 1]; + uint8_t linebuf[MAX_LINE_LENGTH_BYTES + 1] + __attribute__((__aligned__(sizeof(uint32_t)))); uint32_t *uip = (void*)linebuf; uint16_t *usp = (void*)linebuf; uint8_t *ucp = (void*)linebuf; -- 1.7.1

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[U-Boot] Winning Code (AQ11WWRZZA1)!!!
by British National Lottery 20 Aug '10

20 Aug '10

This is to inform you that you have been selected for a cash prize of 1,200,000 (British Pounds) held on the 11th of August, 2010 in London (United Kingdom). 1.Full Name 2.Full Address 3.Marital Status 4.Occupation 5.Age 6.Sex 7.Country Of Residence 8.Telephone Number 9.Next of Kin Agent Name: Mr. Richard Carpenter Tel: +44-701-1132-955 Email: (bnl.org100(a)btinternet.com)

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[U-Boot] [PATCH] mpx85xx/fdt: Add cpu-release-addr for all cores
by Matthew McClintock 20 Aug '10

20 Aug '10

We currently do not add a cpu-release-addr for core 0, this is needed when we want to reset core 0 and later restart it from Linux --- arch/powerpc/cpu/mpc85xx/fdt.c | 21 ++++++++------------- 1 files changed, 8 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 8e7b827..acc70bf 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -47,25 +47,20 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) int off; ulong spin_tbl_addr = get_spin_phys_addr(); u32 bootpg = determine_mp_bootpg(); - u32 id = get_my_id(); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) { - if (*reg == id) { - fdt_setprop_string(blob, off, "status", "okay"); - } else { - u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; - val = cpu_to_fdt32(val); - fdt_setprop_string(blob, off, "status", - "disabled"); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); - } + u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt32(val); + fdt_setprop_string(blob, off, "status", + "disabled"); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); } else { printf ("cpu NULL\n"); } -- 1.6.6.1

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[U-Boot] [PATCH] nios2: fix out of reach case for do_reset
by Thomas Chou 20 Aug '10

20 Aug '10

The "Nios II Processor Reference Handbook" said, "call can transfer execution anywhere within the 256 MByte range determined by PC31..28. The Nios II GNU linker does not automatically handle cases in which the address is out of this range." So we have to use registered "callr" instruction to do the job. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/cpu/cpu.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 6379534..d9c3003 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -40,11 +40,13 @@ int checkcpu (void) return (0); } - -int do_reset (void) +int do_reset(void) { - void (*rst)(void) = (void(*)(void))CONFIG_SYS_RESET_ADDR; - disable_interrupts (); - rst(); - return(0); + disable_interrupts(); + __asm__ __volatile__ ( + "callr %0" + : + : "r" (CONFIG_SYS_RESET_ADDR) + ); + return 0; } -- 1.7.2.1

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[U-Boot] Please pull u-boot-mpc85xx.git (fwd)
by Kumar Gala 20 Aug '10

20 Aug '10

[ Updated ve8313 patch and adding Matt's fix to cpu release dts nodes ] The following changes since commit bd2313078114c4b44c4a5ce149af43bcb7fc8854: Wolfgang Denk (1): Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master are available in the git repository at: git://git.denx.de/u-boot-mpc85xx master Kim Phillips (1): powerpc/8xxx: share PIC defines among 85xx and 86xx Kumar Gala (2): powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs powerpc/83xx: Fix build issue with ve8313 board due to lbus changes Lian Minghuan (1): powerpc/85xx: Fix SRIO LAW setup on corenet_ds boards Matthew McClintock (1): mpx85xx/fdt: Add cpu-release-addr for all cores york (1): powerpc/8xxx: Fix quad-rank DIMMs support on corenet_ds board. arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fdt.c | 15 +++++---- arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 6 ++-- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 8 ++-- arch/powerpc/cpu/mpc85xx/traps.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 8 +++-- arch/powerpc/include/asm/fsl_liodn.h | 8 ++-- arch/powerpc/include/asm/immap_85xx.h | 10 ++---- arch/powerpc/include/asm/immap_86xx.h | 9 ++++-- board/freescale/corenet_ds/corenet_ds.c | 47 ++++++++++++++++-------------- board/freescale/corenet_ds/ddr.c | 18 +++++++++++- board/ve8313/ve8313.c | 2 +- include/configs/corenet_ds.h | 2 +- include/configs/ve8313.h | 1 + 16 files changed, 83 insertions(+), 59 deletions(-)

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[U-Boot] NAND 16 bit buswidth issue
by Pete Murray 19 Aug '10

19 Aug '10

I am running U-boot 2009.08 on a sequoia based custom board. The board has a Micron 29F2G16AAD nand chip. This chip is a large page device with a 16 bit buswidth. I have an issue in nand_base.c in the nand_get_flash_type function where the check for buswidth fails, causing the print out - printk(KERN_WARNING "NAND bus width %d instead %d bit\n", (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, busw ? 16 : 8); The busw is read from the nand chip and is correct, but the chip->options is incorrect. I don't see where this gets set to the options shown in nand_ids.c. I see that here: /* Lookup the flash id */ for (i = 0; nand_flash_ids[i].name != NULL; i++) { if (dev_id == nand_flash_ids[i].id) { type = &nand_flash_ids[i]; break; } } type gets the correct values from nand_ids, should the value of type->options be assigned to chip->options? Or am I missing something and need to set chip->options somewhere in my board specific files?

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