September 2009 - U-Boot

[U-Boot] I found an error
by sun peng 17 Sep '09

17 Sep '09

Hi there: Recently I'm playing with u-boot and want it be able to boot from nand. When I config u-boot to smdk6400, I found I can't get nand_spl with proper size. It need to be pad to 4k to fit into the steping stone. The final size of nand_spl is depend on the variable "PAD_TO": # PAD_TO used to generate a 4kByte binary needed for the combined image # -> PAD_TO = TEXT_BASE + 4096 PAD_TO := $(shell expr $$[$(TEXT_BASE) + 4096]) The lines above is in file: u-boot-xxx/nand_spl//board/samsung/smdk6400/config.mk Unfortunately the PAD_TO can not evaluate to the proper value when I run the makefile. I change the the line to below: PAD_TO := $(shell expr $(TEXT_BASE) + 4096) then the whole build works OK. Is there any body think this is an issue ? BRs/Sunpeng from Beijing China 10/09/2009

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[U-Boot] lowlevel_init.s for ARM920t/S3C2410
by J.Hwan.Kim 17 Sep '09

17 Sep '09

Hi, everyone I'm running u-boot (2009.03) in S3C2410 board now. But I have a problem. It seems that "bl lowlevel_init" routine in ARM920t/start.s is not working. The label, lowlevel_init, is defined as global label in /board/samsung/s3c2410/lowlevel_init.s and is seen system.map file. I think the code does not jump to lowlevel_init in /board/samsung/s3c2410/lowlevel_init.S from start.S When I copy lowlevel_init subroutine into ARM920t/start.S instead of "bl lowlevel_init", it does work. Why does the "bl lowlevel_init" not work? How can I solve this problem ? Thanks in advance. Regards, J.Hwan Kim

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[U-Boot] [PATCH 1/3] fsl_i2c: Wait for STOP condition to propagate
by Joakim Tjernlund 17 Sep '09

17 Sep '09

After issuing a STOP one must wait until the STOP has completed on the bus before doing something new to the controller. Also add an extra read of SR as the manual mentions doing that is a good idea. Remove surplus write of CR just before a write, isn't required and could potentially disturb the I2C bus. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund(a)transmode.se> --- drivers/i2c/fsl_i2c.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 47bbf79..56f9680 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -223,7 +223,7 @@ i2c_init(int speed, int slaveadd) #endif } -static __inline__ int +static int i2c_wait4bus(void) { unsigned long long timeval = get_ticks(); @@ -248,6 +248,8 @@ i2c_wait(int write) csr = readb(&i2c_dev[i2c_bus_num]->sr); if (!(csr & I2C_SR_MIF)) continue; + /* Read again to allow register to stabilise */ + csr = readb(&i2c_dev[i2c_bus_num]->sr); writeb(0x0, &i2c_dev[i2c_bus_num]->sr); @@ -293,9 +295,6 @@ __i2c_write(u8 *data, int length) { int i; - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &i2c_dev[i2c_bus_num]->cr); - for (i = 0; i < length; i++) { writeb(data[i], &i2c_dev[i2c_bus_num]->dr); @@ -351,6 +350,9 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) i = __i2c_read(data, length); + if (length && i2c_wait4bus()) /* Wait until STOP */ + debug("i2c_read: wait4bus timed out\n"); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); if (i == length) @@ -372,6 +374,8 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) } writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + if (i2c_wait4bus()) /* Wait until STOP */ + debug("i2c_write: wait4bus timed out\n"); if (i == length) return 0; -- 1.6.4.2

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[U-Boot] [PATCH v4 0/4]: bitops cleanup and fixes
by Simon Kagstrom 17 Sep '09

17 Sep '09

Hi yet again! This update to the patch series just cleans up the commit messages to have the comments in the git comments section. // Simon

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[U-Boot] [PATCH 1/2] fsl_i2c: Wait for STOP condition to propagate
by Joakim Tjernlund 17 Sep '09

17 Sep '09

After issuing a STOP one must wait until the STOP has completed on the bus before doing something new to the controller. Also add an extra read of SR as the manual mentions doing that is a good idea. Remove surplus write of CR just before a write, isn't required and could potentially disturb the I2C bus. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund(a)transmode.se> --- drivers/i2c/fsl_i2c.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 47bbf79..59bfab6 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -223,7 +223,7 @@ i2c_init(int speed, int slaveadd) #endif } -static __inline__ int +static int i2c_wait4bus(void) { unsigned long long timeval = get_ticks(); @@ -248,6 +248,8 @@ i2c_wait(int write) csr = readb(&i2c_dev[i2c_bus_num]->sr); if (!(csr & I2C_SR_MIF)) continue; + /* Read again to allow register to stabilise */ + csr = readb(&i2c_dev[i2c_bus_num]->sr); writeb(0x0, &i2c_dev[i2c_bus_num]->sr); @@ -293,9 +295,6 @@ __i2c_write(u8 *data, int length) { int i; - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &i2c_dev[i2c_bus_num]->cr); - for (i = 0; i < length; i++) { writeb(data[i], &i2c_dev[i2c_bus_num]->dr); @@ -351,6 +350,9 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) i = __i2c_read(data, length); + if (i2c_wait4bus()) /* Wait until STOP */ + debug("i2c_read: wait4bus timed out\n"); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); if (i == length) @@ -372,6 +374,8 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) } writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + if (i2c_wait4bus()) /* Wait until STOP */ + debug("i2c_write: wait4bus timed out\n"); if (i == length) return 0; -- 1.6.4.2

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[U-Boot] [PATCH][v3] FDT: remove obsolete OF_CPU and OF_SOC macros.
by Marcel Ziswiler 17 Sep '09

17 Sep '09

Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)noser.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski(a)gmx.de> --- Changes since v1: - CC all respective board maintainers Changes since v2: - Added Guennadi Liakhovetski's ack README | 6 ++++-- include/configs/IDS8247.h | 2 -- include/configs/MPC8260ADS.h | 1 - include/configs/linkstation.h | 2 -- include/configs/mgcoge.h | 2 -- include/configs/mpc7448hpc2.h | 1 - include/configs/muas3001.h | 2 -- include/configs/stxxtc.h | 1 - 8 files changed, 4 insertions(+), 13 deletions(-) diff --git a/README b/README index ff4ed8b..3cb7786 100644 --- a/README +++ b/README @@ -368,8 +368,10 @@ The following options need to be configured: * Adds the "fdt" command * The bootm command automatically updates the fdt - OF_CPU - The proper name of the cpus node. - OF_SOC - The proper name of the soc node. + OF_CPU - The proper name of the cpus node (only required for + MPC512X and MPC5xxx based boards). + OF_SOC - The proper name of the soc node (only required for + MPC512X and MPC5xxx based boards). OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 4c4af05..147a8b2 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -125,8 +125,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 942a4cc..677a143 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -209,7 +209,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #if defined(CONFIG_OF_LIBFDT) -#define OF_CPU "cpu@0" #define OF_TBCLK (bd->bi_busfreq / 4) #endif diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 2feb3ae..16b464c 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -96,8 +96,6 @@ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,603e" -#define OF_SOC "soc10x@80000000" #define OF_STDOUT_PATH "/soc10x/serial@80004600" /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index b955749..55d1fc9 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -347,8 +347,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 4f98ba4..be12186 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -79,7 +79,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,7448@0" #define OF_TSI "tsi108@c0000000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index ae033b2..c94daa3 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -405,8 +405,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8270@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #if defined(CONFIG_MUAS_DEV_BOARD) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index d16262b..5854366 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -509,7 +509,6 @@ typedef unsigned int led_id_t; /* pass open firmware flattened device tree */ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) #endif /* __CONFIG_H */ -- 1.6.4.2

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[U-Boot] No NAND device found!!! Freescale MPC8544+SAMSUNG 1GB Nand Flash , please help!
by duckycool 17 Sep '09

17 Sep '09

http://www.nabble.com/file/p25455541/nand_error.bmp nand_error.bmp Hi all, I can't do READID with nand_get_flash_type in the nand_base.c What I get is an error "No NAND device found!!!" My board is freescale mpc8544 with samsung K9K8G08U0A, the device is supposed {NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS} . What I did is copy the nand.c from /board/tqc/tqm85xx/nand.c into /board/freescale/mpc8544ds Add #define CONFIG_CMD_NAND into MPC8544DS.h, setup TLB/LAW/BR/OR for nand flash. Add RAM array of upm into /board/.../nand.c. When booting, I can get the chip select signal put low with scope. Trace the code, it get both dev_id and tmp_id 0x000000ff. Per the /driver/mtd/nand/nand_base.c , /driver/mtd/nand/fsl_upm.c , and /board/.../nand.c .... I break down the upm operation into the upm control(mamr, mar, IO_ADDR_R, IO_ADDR_W) And then, I tried the low level register control under CodeWarrior command window, it's still failed. As below: (CCSRBR = 0xe0000000 , nand_flash_base = 0xff000000) change 0xe0005070 0x30000008 (OP=11, pattern_offset=8) change 0xe0005068 0x90000000 change 0xff000000 0x0 change 0xe0005070 0x0 change 0xe0005070 0x30000010 change 0xe0005068 0x00000000 change 0xff000000 0x0 change 0xe0005070 0x0 change 0xe0005070 0x30000008 change 0xe0005068 0x00000000 change 0xff000000 0x0 change 0xe0005070 0x0 display 0xff000000 I don't know why? Any MARCO I should add ? Or any special operation should I add into nand_base.c ? Please help, thank you. -- View this message in context: http://www.nabble.com/No-NAND-device-found%21%21%21-Freescale-MPC8544%2BSAM… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] Please pull u-boot-mpc85xx
by Kumar Gala 16 Sep '09

16 Sep '09

The following changes since commit 3ca55bce9c8bf00df06a20487fafc16fa2f8084b: Marcel Ziswiler (1): mpc8260: remove Ethernet node fixup to use generic FDT code. are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master Kumar Gala (7): ppc/8xxx: Misc DDR related fixes ppc/85xx: Introduce low level write_tlb function ppc/85xx: Repack tlb_table to save space ppc/85xx: Move code around to prep for NAND_SPL ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL ppc/85xx: Disable all async interrupt sources when we boot Mingkai Hu (2): ppc/85xx: add boot from NAND/eSDHC/eSPI support NAND boot: change NAND loader's relocate SP to CONFIG param Roy Zang (1): ppc/85xx: Enable usb ehci support for p2020ds board Scott Wood (3): ppc/85xx: Don't enable interrupts before we're ready ppc/85xx: Ensure that MAS8 is zero when writing TLB entries. ppc/85xx: Remove some bogus code from external interrupt handler. board/freescale/mpc8313erdb/mpc8313erdb.c | 2 +- board/sheldon/simpc8313/simpc8313.c | 2 +- cpu/mpc85xx/Makefile | 1 + cpu/mpc85xx/cpu_init.c | 67 +++++++-------- cpu/mpc85xx/cpu_init_early.c | 76 ++++++++++++++++ cpu/mpc85xx/start.S | 55 +++++++++++- cpu/mpc85xx/tlb.c | 60 ++++++------- cpu/mpc85xx/traps.c | 9 +-- cpu/mpc85xx/u-boot-nand.lds | 138 +++++++++++++++++++++++++++++ cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +- cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 +- drivers/misc/fsl_law.c | 2 + include/asm-ppc/mmu.h | 25 +++--- include/asm-ppc/processor.h | 2 + include/configs/MPC8313ERDB.h | 1 + include/configs/P2020DS.h | 9 ++ include/configs/SIMPC8313.h | 1 + 17 files changed, 364 insertions(+), 100 deletions(-) create mode 100644 cpu/mpc85xx/cpu_init_early.c create mode 100644 cpu/mpc85xx/u-boot-nand.lds

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[U-Boot] [PATCH 5/5] mpc83xx: mpc8360emds: Add QE USB device tree fixups
by Anton Vorontsov 16 Sep '09

16 Sep '09

With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc8360emds/mpc8360emds.c | 12 ++++++++++++ include/configs/MPC8360EMDS.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 54f2989..d4ba043 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -25,6 +25,8 @@ #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif +#include <hwconfig.h> +#include <fdt_support.h> #if defined(CONFIG_PQ_MDS_PIB) #include "../common/pq-mds-pib.h" #endif @@ -357,12 +359,22 @@ static int sdram_init(unsigned int base) { return 0; } #endif #if defined(CONFIG_OF_BOARD_SETUP) +static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) +{ + if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) + return; + + do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode", + "peripheral", sizeof("peripheral"), 1); +} + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + ft_board_fixup_qe_usb(blob, bd); /* * mpc8360ea pb mds errata 2: RGMII timing * if on mpc8360ea rev. 2.1, diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 30a8d45..dab0173 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -382,6 +382,8 @@ #define CONFIG_NET_MULTI 1 #endif +#define CONFIG_HWCONFIG 1 + /* * QE UEC ethernet configuration */ -- 1.6.3.3

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[U-Boot] [PATCH 3/5] mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is available
by Anton Vorontsov 16 Sep '09

16 Sep '09

Since commit 5c2ff323a94e27e481f70c44838d43fcd844dd46 ("mpc8360emds: rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux. Though, it appears that QE Ethernet in Gigabit mode can't transmit large packets when it tries to work with a data in LBC SDRAM (memtest didn't discover any issues, is LBC SDRAM just too slow?). With this patch we can still use the board without DDR memory, but if DDR is available, we don't use LBC SDRAM. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc8360emds/mpc8360emds.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index dc4dbd3..769eb2f 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -126,6 +126,7 @@ phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; + u32 lbc_sdram_size; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; @@ -147,7 +148,9 @@ phys_size_t initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - msize += sdram_init(msize * 1024 * 1024); + lbc_sdram_size = sdram_init(msize * 1024 * 1024); + if (!msize) + msize = lbc_sdram_size; /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); -- 1.6.3.3

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