September 2009 - U-Boot

[U-Boot] [PATCH 1/2] ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL
by Kumar Gala 16 Sep '09

16 Sep '09

Use write_tlb and don't use memset so we can use the same code for cpu_init_early_f between NAND SPL and not. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/cpu_init.c | 34 +++++++++++++++++++++++++--------- 1 files changed, 25 insertions(+), 9 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5f66511..07856c2 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao(a)motorola.com @@ -132,15 +132,26 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { + u32 mas0, mas1, mas2, mas3, mas7; + int i; + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); + /* + * Clear initial global data + * we don't use memset so we can share this code with NAND_SPL + */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; - set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 0, BOOKE_PAGESZ_4K, 0); + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + + write_tlb(mas0, mas1, mas2, mas3, mas7); /* set up CCSR if we want it moved */ #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) @@ -149,9 +160,14 @@ void cpu_init_early_f(void) volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 1, BOOKE_PAGESZ_4K, 0); + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, + MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + + write_tlb(mas0, mas1, mas2, mas3, mas7); temp = in_be32(ccsr_virt); out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); -- 1.6.0.6

1 3

Re: [U-Boot] LCRR setting on XPEDITE5370 & XPEDITE5200
by Kumar Gala 16 Sep '09

16 Sep '09

Peter, I see you guys set LCRR in the config.h. You are using LCRR_CLKDIV_4. Do you think this means clk/4? (I ask because the defines aren't correct, and wasn't sure about your expectation). - k

2 2

[U-Boot] Flashing images bigger than ram
by Ben Goska 16 Sep '09

16 Sep '09

Is there a standard way to have U-Boot flash really large images? I want to setup rootfs flashing from U-Boot but this requires flashing an image that is bigger than the ram of my system. I thought about breaking the image into chunks, but when flashing to NAND with bad blocks it is difficult to handle skipping the bad blocks. I know I could make this happen with a custom command added to U-Boot but I was wondering if someone else had solved the problem already. My hardware: OMAP3530, 128MB Ram, 256MB NAND. Trying to flash from MMC (fat, or ext2) to NAND. Thanks for any help. Ben Goska goskab(a)onid.oregonstate.edu

3 2

[U-Boot] [PATCH] Add Elpida Memory Configuration to mpc5121ads Boards
by Martha M Stan 15 Sep '09

15 Sep '09

Signed-off-by: Martha M Stan <mmarx(a)silicontkx.com> --- board/freescale/mpc5121ads/mpc5121ads.c | 97 ++++++++++++++++++++++++++++++- include/configs/mpc5121ads.h | 39 ++++++++++++- 2 files changed, 132 insertions(+), 4 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 8defb00..9892d50 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -31,6 +31,7 @@ #ifdef CONFIG_MISC_INIT_R #include <i2c.h> #endif +#include <net.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -133,11 +134,103 @@ int board_early_init_f(void) return 0; } +int is_micron(void){ + + ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00); + uchar macaddr[6]; + u32 brddate, macchk, ismicron; + + /* + * MAC address has serial number with date of manufacture + * Boards made before Nov-08 #1180 use Micron memory; + * 001e59 is the STx vendor # + * Default is Elpida since it works for both but is slightly slower + */ + ismicron = 0; + if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) { + brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; + macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; + debug("brddate = %d\n\t", brddate); + + if (macchk == 0x001e59 && brddate <= 8111180) + ismicron = 1; + } else if (brd_rev < 0x400) { + ismicron = 1; + } + debug("Using %s Memory settings\n\t", + ismicron ? "Micron" : "Elpida"); + return(ismicron); +} + phys_size_t initdram(int board_type) { - u32 msize = 0; + /* Elpida MDDRC and initialization settings are an alternative + * to the Default Micron ones for all but the earliest Rev 4 boards + */ + u32 elpida_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, + CONFIG_SYS_MDDRC_TIME_CFG0, + CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, + CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA + }; + + u32 elpida_init_sequence[] = { + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_EM2, + CONFIG_SYS_MICRON_EM3, + CONFIG_SYS_MICRON_EN_DLL, + CONFIG_SYS_ELPIDA_RES_DLL, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_ELPIDA_INIT_DEV_OP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_OCD_DEFAULT, + CONFIG_SYS_ELPIDA_OCD_EXIT, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP + }; - msize = fixed_sdram(NULL, NULL, 0); + u32 msize = 0; + if (is_micron()) + msize = fixed_sdram(NULL, NULL, 0); + else + msize = fixed_sdram(elpida_mddrc_config, + elpida_init_sequence, + sizeof(elpida_init_sequence)/sizeof(u32)); return msize; } diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index d96e7f5..fda63dd 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -141,14 +141,49 @@ #endif #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E +#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xFA802B00 +#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 + +/* MICRON Configuration and Commands + * These also work for Elpida unless explicitly overwritten + */ #define CONFIG_SYS_MICRON_NOP 0x01380000 #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 #define CONFIG_SYS_MICRON_EM2 0x01020000 #define CONFIG_SYS_MICRON_EM3 0x01030000 #define CONFIG_SYS_MICRON_EN_DLL 0x01010000 #define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 + +#define DDR_CMD_EMR_OCD(pr, ohm) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (1 << 16) | /* MODE Reg BA[2:0] */ \ + (0 << 12) | /* Outputs 0=Enabled */ \ + (0 << 11) | /* RDQS */ \ + (1 << 10) | /* DQS# */ \ + (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ + /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ + ((ohm & 0x1) << 6)| /* Rtt1 */ \ + (0 << 3) | /* additive posted CAS# */ \ + ((ohm & 0x2) << 2)| /* Rtt0 */ \ + (0 << 0) | /* Output Drive Strength */ \ + (0 << 0)) /* DLL Enable 0=Normal */ + +#define CONFIG_SYS_MICRON_OCD_DEFAULT DDR_CMD_EMR_OCD(7, 0) +#define CONFIG_SYS_ELPIDA_OCD_EXIT DDR_CMD_EMR_OCD(0, 0) + +#define DDR_CMD_MODE_REG(cas, wr) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (0 << 16) | /* MODE Reg BA[2:0] */ \ + ((wr-1) << 9)| /* Write Recovery */ \ + (cas << 4) | /* CAS */ \ + (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ + (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ + +#define CONFIG_SYS_MICRON_INIT_DEV_OP DDR_CMD_MODE_REG(3, 3) +#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDR_CMD_MODE_REG(4, 4) +#define CONFIG_SYS_ELPIDA_RES_DLL (DDR_CMD_MODE_REG(4, 4) | (1 << 8)) + /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -- 1.5.2.4

2 1

[U-Boot] [PATCH] Streamlined mpc512x fixed_sdram init sequence allowing for
by Martha M Stan 15 Sep '09

15 Sep '09

Signed-off-by: Martha M Stan <mmarx(a)silicontkx.com> --- board/davedenx/aria/aria.c | 2 +- board/esd/mecp5123/mecp5123.c | 2 +- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- cpu/mpc512x/fixed_sdram.c | 94 ++++++++++++++++++++----------- include/asm-ppc/immap_512x.h | 5 +- include/asm-ppc/mpc512x.h | 2 +- include/configs/aria.h | 6 +-- include/configs/mecp5123.h | 5 +- include/configs/mpc5121ads.h | 6 +-- 9 files changed, 72 insertions(+), 52 deletions(-) diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index 2064aa2..cc69c9d 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -101,7 +101,7 @@ int board_early_init_f(void) phys_size_t initdram (int board_type) { - return fixed_sdram(); + return fixed_sdram(NULL, NULL, 0); } int misc_init_r(void) diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index f591e32..5139358 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -135,7 +135,7 @@ int board_early_init_f(void) phys_size_t initdram(int board_type) { - return get_ram_size(0, fixed_sdram()); + return get_ram_size(0, fixed_sdram(NULL, NULL, 0)); } int misc_init_r(void) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index a0d7a82..8defb00 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -137,7 +137,7 @@ phys_size_t initdram(int board_type) { u32 msize = 0; - msize = fixed_sdram(); + msize = fixed_sdram(NULL, NULL, 0); return msize; } diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index d906903..eb0811c 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -20,23 +20,73 @@ * MA 02111-1307 USA * */ - +#define DEBUG 0xff #include <common.h> #include <asm/io.h> #include <asm/mpc512x.h> +/* config settings in order of the 4 mddrc cfg registers */ +u32 default_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG, + CONFIG_SYS_MDDRC_TIME_CFG0, + CONFIG_SYS_MDDRC_TIME_CFG1, + CONFIG_SYS_MDDRC_TIME_CFG2 +}; + +u32 default_init_sequence[] = { + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_EM2, + CONFIG_SYS_MICRON_NOP, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_EM2, + CONFIG_SYS_MICRON_EM3, + CONFIG_SYS_MICRON_EN_DLL, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_RFSH, + CONFIG_SYS_MICRON_INIT_DEV_OP, + CONFIG_SYS_MICRON_OCD_DEFAULT, + CONFIG_SYS_MICRON_PCHG_ALL, + CONFIG_SYS_MICRON_NOP +}; + /* * fixed sdram init: * The board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ -long int fixed_sdram(void) +long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_sequence, int seq_table_size) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); u32 i; + /* take default settings and init sequence if necessary */ + if (mddrc_config == 0) + mddrc_config = default_mddrc_config; + if (dram_init_sequence == 0) { + dram_init_sequence = default_init_sequence; + seq_table_size = sizeof(default_init_sequence)/sizeof(u32); + } + /* Initialize IO Control */ out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); @@ -46,7 +96,7 @@ long int fixed_sdram(void) sync_law(&im->sysconf.ddrlaw.ar); /* Enable DDR */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); /* Initialize DDR Priority Manager */ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); @@ -74,40 +124,18 @@ long int fixed_sdram(void) out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); /* Initialize MDDRC */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); - out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); - out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[0]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[1] & MDDRC_TIME_CFG0_RFRSH0); + out_be32(&im->mddrc.ddr_time_config1, mddrc_config[2]); + out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); /* Initialize DDR */ - for (i = 0; i < 10; i++) - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + for (i = 0; i < seq_table_size; i++) + out_be32(&im->mddrc.ddr_command, dram_init_sequence[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config[1]); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config[0] & MDDRC_SYS_CFG_RUN); return msize; } diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 24e6c69..13d3d0e 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -45,7 +45,6 @@ #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) - #ifndef __ASSEMBLY__ typedef struct law512x { u32 bar; /* Base Addr Register */ @@ -341,6 +340,10 @@ typedef struct ddr512x { u32 res2[0x3AD]; } ddr512x_t; +/* MDDRC SYS CFG and Timing CFG0 Registers */ +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_RUN ~(0x01 << 28) +#define MDDRC_TIME_CFG0_RFRSH0 0x0000FFFF /* * DMA/Messaging Unit diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h index 20456f5..6a65492 100644 --- a/include/asm-ppc/mpc512x.h +++ b/include/asm-ppc/mpc512x.h @@ -50,7 +50,7 @@ static inline void sync_law(volatile void *addr) /* * Prototypes */ -extern long int fixed_sdram(void); +extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_sequence, int seq_table_size); extern int mpc5121_diu_init(void); extern void ide_set_reset(int idereset); diff --git a/include/configs/aria.h b/include/configs/aria.h index 4211113..a6fa168 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -143,14 +143,10 @@ (0 << 0) /* FIFO_UV_EN */ \ ) -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28)) +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E - #define CONFIG_SYS_MICRON_NOP 0x01380000 #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 1ecae00..8bed9d1 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -112,12 +112,9 @@ * [04:00] DRAM tRPA */ #define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E #define CONFIG_SYS_MICRON_NOP 0x01380000 #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 76f174d..d96e7f5 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -132,18 +132,14 @@ */ #ifdef CONFIG_MPC5121ADS_REV2 #define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 #else #define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E #define CONFIG_SYS_MICRON_NOP 0x01380000 #define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -- 1.5.2.4

2 1

[U-Boot] [PATCH][v3] mpc8260: remove Ethernet node fixup to use generic FDT code.
by Marcel Ziswiler 15 Sep '09

15 Sep '09

Remove Ethernet node fixup from mgcoge and muas3001 boards and modify its configs for the common mpc8260 code to use generic Ethernet fixup. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)noser.com> Tested-by: Heiko Schocher <hs(a)denx.de> --- Changes since v1: - Added Heiko's tested-by Changes since v2: - Re-based to origin/master board/keymile/mgcoge/mgcoge.c | 5 ----- board/muas3001/muas3001.c | 15 --------------- include/configs/mgcoge.h | 1 + include/configs/muas3001.h | 1 + 4 files changed, 2 insertions(+), 20 deletions(-) diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index d24a4b5..b16a01c 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -25,7 +25,6 @@ #include <mpc8260.h> #include <ioports.h> #include <malloc.h> -#include <net.h> #include <asm/io.h> #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) @@ -373,10 +372,6 @@ void ft_blob_update (void *blob, bd_t *bd) flash_reg[5] = cpu_to_be32 (info->size); fdt_set_node_and_value (blob, "/localbus/flash@5,0", "reg", flash_reg, sizeof (flash_reg)); - - /* MAC addr */ - fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address", - bd->bi_enetaddr, sizeof (u8) * 6); } void ft_board_setup (void *blob, bd_t *bd) diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index bf4ccb6..36caed8 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -342,21 +342,6 @@ void ft_blob_update (void *blob, bd_t *bd) printf ("ft_blob_update(): cannot find /localbus node " "err:%s\n", fdt_strerror (nodeoffset)); } - /* MAC Adresse */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); - if (nodeoffset >= 0) { - uchar ethaddr[6]; - eth_getenv_enetaddr("ethaddr", ethaddr); - ret = fdt_setprop (blob, nodeoffset, "mac-address", ethaddr, - sizeof (uchar) * 6); - if (ret < 0) - printf ("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " - "property err:%s\n", fdt_strerror (ret)); - } else { - /* memory node is required in dts */ - printf ("ft_blob_update(): cannot find /soc/cpm/ethernet node " - "err:%s\n", fdt_strerror (nodeoffset)); - } /* baudrate */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index ea14948..b955749 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -70,6 +70,7 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_ETHER_INDEX 4 +#define CONFIG_HAS_ETH0 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index f031a17..ae033b2 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -74,6 +74,7 @@ #define CONFIG_ETHER_INDEX 1 #define CONFIG_ETHER_ON_FCC1 +#define CONFIG_HAS_ETH0 #define FCC_ENET /* -- 1.6.4.2

2 1

[U-Boot] [PATCH] tools/netconsole: make a bit more robust and use ncb when possible
by Mike Frysinger 15 Sep '09

15 Sep '09

The netcat utility likes to exit when it receives an empty packet (as it thinks this means EOF). This can easily occur when working with command line editing as this behavior will be triggered when using backspace. Or with tabs and command line completion. Since the local ncb util does not have this "feature" and it supports broadcast udp, default to using that rather than netcat. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- tools/netconsole | 18 +++++++++++++++--- 1 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tools/netconsole b/tools/netconsole index 09c8981..aa30d9b 100755 --- a/tools/netconsole +++ b/tools/netconsole @@ -31,12 +31,24 @@ if [ -z "${ip}" ] || [ -n "$3" ] ; then fi for nc in netcat nc ; do - type ${nc} >/dev/null && break + type ${nc} >/dev/null 2>&1 && break done trap "stty icanon echo intr ^C" 0 2 3 5 10 13 15 echo "NOTE: the interrupt signal (normally ^C) has been remapped to ^T" stty -icanon -echo intr ^T -${nc} -u -l -p ${port} < /dev/null & -exec ${nc} -u ${ip} ${port} +( +if [ -x ./ncb ] ; then + exec ./ncb ${port} +elif [ -x ${0%/*}/ncb ] ; then + exec ${0%/*}/ncb ${port} +else + while ${nc} -u -l -p ${port} < /dev/null ; do + : + done +fi +) & +pid=$! +${nc} -u ${ip} ${port} +kill $pid 2>/dev/null -- 1.6.1

2 15

[U-Boot] [PATCH 00/10] add boot from NAND/eSDHC/eSPI support
by Mingkai Hu 15 Sep '09

15 Sep '09

The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patchset implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the second stage image to L2SRAM which lets us use the SPD to initialize the SDRAM. [PATCH 01/10] mkconfig: parse top level makefile target to multiple config targets [PATCH 02/10] NAND boot: change NAND loader's relocate SP to CONFIG param [PATCH 03/10] Add L2SRAM Register's macro definition [PATCH 04/10] 85xx: add boot from NAND/eSDHC/eSPI support [PATCH 05/10] NAND boot: MPC8536DS support [PATCH 06/10] On-chip ROM boot: MPC8536DS support Add description for the different boot method: [PATCH 07/10] Add README.mpc8536ds The follow three patches implement save env to SDCard: [PATCH 08/10] Make mmc init come before env_relocate [PATCH 09/10] Add support for save environment variable to MMC/SD card [PATCH 10/10] Get the address of env on the SDCard

6 28

[U-Boot] still nothing on serial output sa1100
by Kristoffer Ericson 15 Sep '09

15 Sep '09

Greetings, Ive been busy trying to get any signs from my generated u-boot.bin. I started thinking it was caused by the memory setup and replicated the one I had used in blob (which works). Still got nothing and now Im looking for suggestions on where to proceed. Can I count on the serial drivers working? What process starts after the memory is setup? Attached my current Setup.S: diff --git a/board/jornada/setup.S b/board/jornada/setup.S new file mode 100644 index 0000000..1c6e233 --- /dev/null +++ b/board/jornada/setup.S @@ -0,0 +1,226 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + +/*----------------------------------------------------------------------- + * Board defines: + */ + +#define MDCNFG 0x00 +#define MDCAS00 0x04 +#define MDCAS01 0x08 +#define MDCAS02 0x0C +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 +#define MDREFR 0x1C +#define MDCAS20 0x20 +#define MDCAS21 0x24 +#define MDCAS22 0x28 +#define MSC2 0x2C +#define SMCNFG 0x30 + +#define MDCNFG_BANK0_ENABLE (1 << 0) +#define MDCNFG_DTIM0_SDRAM (1 << 2) +#define MDCNFG_DWID0_32B (0 << 3) +#define MDCNFG_DRAC0(n_) (((n_) & 7) << 4) +#define MDCNFG_TRP0(n_) (((n_) & 0xF) << 8) +#define MDCNFG_TDL0(n_) (((n_) & 3) << 12) +#define MDCNFG_TWR0(n_) (((n_) & 3) << 14) +#define MSC_RT_ROMFLASH 0 +#define MSC_RBW32 (0 << 2) +#define MSC_RDF(n_) (((n_) & 0x1f) << 3) +#define MSC_RDN(n_) (((n_) & 0x1f) << 8) +#define MSC_RRR(n_) (((n_) & 0x07) << 13) +#define MSC_RT_VARLAT_345 1 +#define MDREFR_TRASR(n_) (n_ & (0x0000000f)) +#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4) +#define MDREFR_K0RUN (1 << 17) +#define MDREFR_K0DB2 (1 << 18) +#define MDREFR_K1RUN (1 << 21) +#define MDREFR_K1DB2 (1 << 22) +#define MDREFR_K2RUN (1 << 25) +#define MDREFR_K2DB2 (1 << 26) +#define MDREFR_SLFRSH (1 << 31) +#define MDREFR_E1PIN (1 << 20) +#define PSSR_DH 0x00000008 +#define PSSR 0x04 +#define PM_BASE 0x90020000 + +#define mdcnfg_1 (MDCNFG_BANK0_ENABLE|MDCNFG_DTIM0_SDRAM|MDCNFG_DWID0_32B|MDCNFG_DRAC0(6)|MDCNFG_TRP0(2)|MDCNFG_TDL0(3)|MDCNFG_TWR0(1)) +#define cs0_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(15)|MSC_RDN(15)|MSC_RRR(2)) +#define cs1_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7)) +#define cs2_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7)) +#define cs3_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7)) +#define cs4_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(11)|MSC_RDN(9)|MSC_RRR(1)) +#define cs5_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(3)|MSC_RDN(0)|MSC_RRR(1)) +#define msc0_1 (cs0_1|(cs1_1 << 16)) +#define msc1_1 (cs2_1|(cs3_1 << 16)) +#define msc2_1 (cs4_1|(cs5_1 << 16)) + + +/*----------------------------------------------------------------------- + * Setup parameters for the board: + */ + + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 +PWR_BASE: .word PM_BASE + +/* calculated from old blob bootloader */ +MEMORY_CONFIG: + .long mdcnfg_1 /* mdcnfg 0x00007265 */ + .long 0x5555557f /* mdcas00 0x5555557f */ + .long 0x55555555 /* mdcas01 0x55555555 */ + .long 0x55555555 /* mdcas02 0x55555555 */ + .long msc0_1 /* msc0 0xfff04f78 */ + .long msc1_1 /* msc1 0xfff8fff0 */ + .long 0x98c698c6 /* mecr 0x98c698c6 */ + .long 0xdeadbeef /* mdrefr 0x04340327 */ + .long 0xd1284142 /* mdcas20 0xd1284142 */ + .long 0x72249529 /* mdcas21 0x72249529 */ + .long 0x78414351 /* mdcas22 0x78414351 */ + .long msc2_1 /* msc2 0x201d2959 */ + .long 0x00000000 /* smcnfg 0x00000000 */ + +.globl lowlevel_init +lowlevel_init: + mov r5, lr + + /* Setting up the memory and stuff */ + ldr r0, MEM_BASE + adr r1, MEMORY_CONFIG + + ldr r2, [r1, #MDCNFG] + str r2, [r0, #MDCNFG] + + ldr r2, [r1, #MDCAS00] + str r2, [r0, #MDCAS00] + + ldr r2, [r1, #MDCAS01] + str r2, [r0, #MDCAS01] + + ldr r2, [r1, #MDCAS02] + str r2, [r0, #MDCAS02] + + ldr r2, [r1, #MDCAS20] + str r2, [r0, #MDCAS20] + + ldr r2, [r1, #MDCAS21] + str r2, [r0, #MDCAS21] + + ldr r2, [r1, #MDCAS22] + str r2, [r0, #MDCAS22] + + /* clear kxDB2 */ + ldr r2, [r0, #MDREFR] + bic r2, r2, #MDREFR_K0DB2 + bic r2, r2, #MDREFR_K1DB2 + bic r2, r2, #MDREFR_K2DB2 + str r2, [r0, #MDREFR] + + /* set TRASR and DRI, KXDB2 */ + ldr r2, [r0, #MDREFR] + orr r2, r2, #MDREFR_TRASR(7) + + mov r4, #0x2000 +spin: subs r4, r4, #1 + bne spin + + ldr r1, PWR_BASE + mov r2, #PSSR_DH + str r2, [r1, #PSSR] + + /* clear KxDB2 */ + ldr r2, [r0, #MDREFR] + bic r2, r2, #MDREFR_K0DB2 + bic r2, r2, #MDREFR_K1DB2 + bic r2, r2, #MDREFR_K2DB2 + str r2, [r0, #MDREFR] + + /* set TRASR and DRI, KxDB2 */ + ldr r2, [r0, #MDREFR] + orr r2, r2, #MDREFR_TRASR(7) + orr r2, r2, #MDREFR_DRI(12) + orr r2, r2, #MDREFR_K0DB2 + orr r2, r2, #MDREFR_K1DB2 + orr r2, r2, #MDREFR_K2DB2 + str r2, [r0, #MDREFR] + + /* set KxRUN */ + ldr r2, [r0, #MDREFR] + orr r2, r2, #MDREFR_K0RUN + orr r2, r2, #MDREFR_K1RUN + orr r2, r2, #MDREFR_K2RUN + str r2, [r0, #MDREFR] + + /* clear SLFRSH */ + ldr r2, [r0, #MDREFR] + bic r2, r2, #MDREFR_SLFRSH + str r2, [r0, #MDREFR] + + /* toggle E1PIN (set -> clear) */ + ldr r2, [r0, #MDREFR] + orr r2, r2, #MDREFR_E1PIN + str r2, [r0, #MDREFR] + + /* Load something to activate bank */ + ldr r1, MEM_START +.rept 8 + ldr r0, [r1] +.endr + + ldr r0, MEM_BASE + adr r1, MEMORY_CONFIG + + /* Enable SDRAM banks */ + ldr r2, [r0, #MDCNFG] + orr r2, r2, #0x00000003 + orr r2, r2, #0x00030000 + str r2, [r0, #MDCNFG] + + ldr r2, [r1, #MSC0] + str r2, [r0, #MSC0] + + ldr r2, [r1, #MSC1] + str r2, [r0, #MSC1] + + ldr r2, [r1, #MSC2] + str r2, [r0, #MSC2] + + ldr r2, [r1, #SMCNFG] + str r2, [r0, #SMCNFG] + + ldr r2, [r1, #MECR] + str r2, [r0, #MECR] + + /* All done... */ + mov pc, r5 -- Kristoffer Ericson <kristoffer.ericson(a)gmail.com>

1 0

[U-Boot] [PATCH 1/3] push LOAD_ADDR out to arch mk files
by Mike Frysinger 15 Sep '09

15 Sep '09

Rather than maintain/extend the current ifeq($(ARCH)) mess that exists in the standalone Makefile, push the setting up of LOAD_ADDR out to the arch config.mk (and rename to STANDALONE_LOAD_ADDR in the process). This keeps the common code clean and lets the arch do whatever crazy crap it wants in its own area. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- examples/standalone/Makefile | 65 +----------------------------------------- lib_arm/config.mk | 10 ++++++ lib_avr32/config.mk | 2 + lib_blackfin/config.mk | 2 + lib_i386/config.mk | 2 + lib_m68k/config.mk | 3 ++ lib_microblaze/config.mk | 2 + lib_mips/config.mk | 2 + lib_nios/config.mk | 2 + lib_nios2/config.mk | 2 + lib_ppc/config.mk | 2 + lib_sh/config.mk | 5 +++ lib_sparc/config.mk | 2 + 13 files changed, 37 insertions(+), 64 deletions(-) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index d2e811a..d469904 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -21,65 +21,6 @@ # MA 02111-1307 USA # -ifeq ($(ARCH),ppc) -LOAD_ADDR = 0x40000 -endif - -ifeq ($(ARCH),i386) -LOAD_ADDR = 0x40000 -endif - -ifeq ($(ARCH),arm) -ifeq ($(BOARD),omap2420h4) -LOAD_ADDR = 0x80300000 -else -ifeq ($(SOC),omap3) -LOAD_ADDR = 0x80300000 -else -LOAD_ADDR = 0xc100000 -endif -endif -endif - -ifeq ($(ARCH),mips) -LOAD_ADDR = 0x80200000 -T mips.lds -endif - -ifeq ($(ARCH),nios) -LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds -endif - -ifeq ($(ARCH),nios2) -LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds -endif - -ifeq ($(ARCH),m68k) -LOAD_ADDR = 0x20000 -L $(clibdir) -endif - -ifeq ($(ARCH),microblaze) -LOAD_ADDR = 0x80F00000 -endif - -ifeq ($(ARCH),blackfin) -LOAD_ADDR = 0x1000 -endif - -ifeq ($(ARCH),avr32) -LOAD_ADDR = 0x00000000 -endif - -ifeq ($(ARCH),sh) -LOAD_ADDR = 0x8C000000 -ifeq ($(CPU),sh2) -BIG_ENDIAN=y -endif -endif - -ifeq ($(ARCH),sparc) -LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds -endif - include $(TOPDIR)/config.mk ELF = hello_world @@ -139,9 +80,6 @@ SREC += eepro100_eeprom.srec BIN += eepro100_eeprom.bin endif -ifeq ($(BIG_ENDIAN),y) -EX_LDFLAGS += -EB -endif COBJS := $(SREC:.srec=.o) @@ -164,7 +102,6 @@ BIN := $(addprefix $(obj),$(BIN)) SREC := $(addprefix $(obj),$(SREC)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) -clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) CPPFLAGS += -I.. @@ -176,7 +113,7 @@ $(LIB): $(obj).depend $(LIBOBJS) $(ELF): $(obj)%: $(obj)%.o $(LIB) - $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ + $(LD) -g -Ttext $(STANDALONE_LOAD_ADDR) \ -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ -L$(gcclibdir) -lgcc diff --git a/lib_arm/config.mk b/lib_arm/config.mk index 705dfc3..3c078df 100644 --- a/lib_arm/config.mk +++ b/lib_arm/config.mk @@ -23,6 +23,16 @@ CROSS_COMPILE ?= arm-linux- +ifeq ($(BOARD),omap2420h4) +STANDALONE_LOAD_ADDR = 0x80300000 +else +ifeq ($(SOC),omap3) +STANDALONE_LOAD_ADDR = 0x80300000 +else +STANDALONE_LOAD_ADDR = 0xc100000 +endif +endif + PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: diff --git a/lib_avr32/config.mk b/lib_avr32/config.mk index c258b4b..1121ca1 100644 --- a/lib_avr32/config.mk +++ b/lib_avr32/config.mk @@ -23,5 +23,7 @@ CROSS_COMPILE ?= avr32-linux- +STANDALONE_LOAD_ADDR = 0x00000000 + PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_LDFLAGS += --relax diff --git a/lib_blackfin/config.mk b/lib_blackfin/config.mk index 1267c99..3f560c9 100644 --- a/lib_blackfin/config.mk +++ b/lib_blackfin/config.mk @@ -23,6 +23,8 @@ CROSS_COMPILE ?= bfin-uclinux- +STANDALONE_LOAD_ADDR = 0x1000 + CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) diff --git a/lib_i386/config.mk b/lib_i386/config.mk index 5fe36d5..4b990e0 100644 --- a/lib_i386/config.mk +++ b/lib_i386/config.mk @@ -23,4 +23,6 @@ CROSS_COMPILE ?= i386-linux- +STANDALONE_LOAD_ADDR = 0x40000 + PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ diff --git a/lib_m68k/config.mk b/lib_m68k/config.mk index f41d1b3..749c389 100644 --- a/lib_m68k/config.mk +++ b/lib_m68k/config.mk @@ -23,5 +23,8 @@ CROSS_COMPILE ?= m68k-elf- +clibdir = $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) +STANDALONE_LOAD_ADDR = 0x20000 -L $(clibdir) + PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ PLATFORM_LDFLAGS += -n diff --git a/lib_microblaze/config.mk b/lib_microblaze/config.mk index 68e7e21..c3c9f95 100644 --- a/lib_microblaze/config.mk +++ b/lib_microblaze/config.mk @@ -26,4 +26,6 @@ CROSS_COMPILE ?= mb- +STANDALONE_LOAD_ADDR = 0x80F00000 + PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ diff --git a/lib_mips/config.mk b/lib_mips/config.mk index c785677..aa06761 100644 --- a/lib_mips/config.mk +++ b/lib_mips/config.mk @@ -23,6 +23,8 @@ CROSS_COMPILE ?= mips_4KC- +STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds + PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # diff --git a/lib_nios/config.mk b/lib_nios/config.mk index 3ed7170..d48aa6d 100644 --- a/lib_nios/config.mk +++ b/lib_nios/config.mk @@ -24,4 +24,6 @@ CROSS_COMPILE ?= nios-elf- +STANDALONE_LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds + PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs diff --git a/lib_nios2/config.mk b/lib_nios2/config.mk index 59931c2..34ee697 100644 --- a/lib_nios2/config.mk +++ b/lib_nios2/config.mk @@ -24,5 +24,7 @@ CROSS_COMPILE ?= nios2-elf- +STANDALONE_LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds + PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ PLATFORM_CPPFLAGS += -ffixed-r15 -G0 diff --git a/lib_ppc/config.mk b/lib_ppc/config.mk index d91ef7f..010d874 100644 --- a/lib_ppc/config.mk +++ b/lib_ppc/config.mk @@ -23,6 +23,8 @@ CROSS_COMPILE ?= ppc_8xx- +STANDALONE_LOAD_ADDR = 0x40000 + PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n diff --git a/lib_sh/config.mk b/lib_sh/config.mk index 67d7e9e..fa5369f 100644 --- a/lib_sh/config.mk +++ b/lib_sh/config.mk @@ -23,6 +23,11 @@ CROSS_COMPILE ?= sh4-linux- +STANDALONE_LOAD_ADDR = 0x8C000000 +ifeq ($(CPU),sh2) +STANDALONE_LOAD_ADDR += -EB +endif + PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE) diff --git a/lib_sparc/config.mk b/lib_sparc/config.mk index 07b528c..4de6515 100644 --- a/lib_sparc/config.mk +++ b/lib_sparc/config.mk @@ -23,4 +23,6 @@ CROSS_COMPILE ?= sparc-elf- +STANDALONE_LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds + PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ -- 1.6.4.2

2 8