June 2009 - U-Boot

[U-Boot] warnings from gcc-4.4 build
by Kumar Gala 11 Jul '09

11 Jul '09

When building the MPC8572DS_config w/gcc-4.4 I get: sys_eeprom.c: In function ‘do_mac’: sys_eeprom.c:323: warning: dereferencing type-punned pointer will break strict-aliasing rules sys_eeprom.c: In function ‘mac_read_from_eeprom’: sys_eeprom.c:395: warning: dereferencing type-punned pointer will break strict-aliasing rules ahci.c: In function ‘ata_scsiop_read_capacity10’: ahci.c:616: warning: dereferencing type-punned pointer will break strict-aliasing rules biosemu.c: In function ‘BE_setVGA’: biosemu.c:147: warning: dereferencing type-punned pointer will break strict-aliasing rules tsec.c: In function ‘tsec_init’: tsec.c:200: warning: dereferencing type-punned pointer will break strict-aliasing rules dlmalloc.c: In function ‘malloc_bin_reloc’: dlmalloc.c:1502: warning: dereferencing pointer ‘p’ does break strict- aliasing rules dlmalloc.c:1502: warning: dereferencing pointer ‘p’ does break strict- aliasing rules dlmalloc.c:1499: note: initialized from here dlmalloc.c:1502: note: initialized from here dlmalloc.c: In function ‘free’: dlmalloc.c:2474: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2474: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2474: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2474: note: initialized from here dlmalloc.c: In function ‘malloc’: dlmalloc.c:2219: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2219: note: initialized from here dlmalloc.c:2228: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2228: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2228: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2228: note: initialized from here dlmalloc.c:2235: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2235: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2235: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2235: note: initialized from here dlmalloc.c:2292: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2292: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2292: warning: dereferencing pointer ‘({anonymous})’ does break strict-aliasing rules dlmalloc.c:2292: note: initialized from here xyzModem.c: In function ‘xyzModem_stream_open’: xyzModem.c:564: warning: ‘dummy’ is used uninitialized in this function xyzModem.c:547: note: ‘dummy’ was declared here Should would be turning on -fno-strict-aliasing. The linux kernel has been doing this for some time. - k

5 6

[U-Boot] [PATCH 0/7] Initial support for the XPedite5170
by Peter Tyser 11 Jul '09

11 Jul '09

Initial support for Extreme Engineering Solutions XPedite5170 - a MPC8640-based 3U VPX single board computer with a PMC/XMC site. http://www.xes-inc.com/Products/XPedite5170/XPedite5170.html Peter Tyser (6): 85xx: Add PORBMSR and PORDEVSR shift defines 86xx: Unlock l1 cache unconditionally xes: Update Freescale PCI code to work with 86xx processors xes: Update Freescale DDR code to work with 86xx processors xes: Update Freescale clock code to work with 86xx processors XPedite5170 board support Zach LeRoy (1): tsec: Add support for BCM5482S PHY MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/xes/common/Makefile | 7 +- .../xes/common/{fsl_8572_clk.c => fsl_8xxx_clk.c} | 8 + .../xes/common/{fsl_85xx_ddr.c => fsl_8xxx_ddr.c} | 8 +- .../xes/common/{fsl_85xx_pci.c => fsl_8xxx_pci.c} | 81 ++- board/xes/xpedite5170/Makefile | 52 ++ board/xes/xpedite5170/config.mk | 32 + board/xes/xpedite5170/ddr.c | 168 +++++ board/xes/xpedite5170/law.c | 52 ++ board/xes/xpedite5170/u-boot.lds | 132 ++++ board/xes/xpedite5170/xpedite5170.c | 111 +++ drivers/net/tsec.c | 41 ++ include/asm-ppc/immap_85xx.h | 2 + include/configs/XPEDITE5170.h | 758 ++++++++++++++++++++ include/tsec.h | 2 + lib_ppc/board.c | 8 +- lib_ppc/bootm.c | 3 +- 19 files changed, 1453 insertions(+), 17 deletions(-) rename board/xes/common/{fsl_8572_clk.c => fsl_8xxx_clk.c} (86%) rename board/xes/common/{fsl_85xx_ddr.c => fsl_8xxx_ddr.c} (92%) rename board/xes/common/{fsl_85xx_pci.c => fsl_8xxx_pci.c} (79%) create mode 100644 board/xes/xpedite5170/Makefile create mode 100644 board/xes/xpedite5170/config.mk create mode 100644 board/xes/xpedite5170/ddr.c create mode 100644 board/xes/xpedite5170/law.c create mode 100644 board/xes/xpedite5170/u-boot.lds create mode 100644 board/xes/xpedite5170/xpedite5170.c create mode 100644 include/configs/XPEDITE5170.h

4 18

[U-Boot] [patch] csb337 board support (ARM at91rm9200)
by David Brownell 11 Jul '09

11 Jul '09

Add support for csb337, an older at91rm9200 board. These boards originally shipped with MicroMonitor, not U-Boot. This config supports boot from Ethernet, and talks over I2C and console. Open issues: - Console refuses to start at 115200 baud, and misbehaves if it's later changed to that speed. So, use 38400 (like MicroMonitor). - USB didn't work; the software wouldn't detect usb-storage devices. So it's not yet enabled. - There seems to be some issue copying lots of data from NOR flash. It works OK in chunks of up to 512 KB or so, but copying a kernel (1.4 MB) failed ... copying *way* over 15 MBytes, and trashing the DRAM image of U-Boot that was running. (Compiler issue?) Sending this along anyway; it basically works, bugs can be fixed later. Signed-off-by: David Brownell <dbrownell(a)users.sourceforge.net> --- NOTE: depends on cpu/arm920t/at91rm9200/ether.c patch to change how the Ethernet address is stored in chip registers so it matches the old MicroMonitor bug that Linux is working around. MAKEALL | 1 Makefile | 3 board/csb337/Makefile | 49 +++++++++ board/csb337/config.mk | 1 board/csb337/csb337.c | 74 +++++++++++++++ board/csb337/u-boot.lds | 56 +++++++++++ include/configs/csb337.h | 222 +++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 406 insertions(+) --- a/MAKEALL +++ b/MAKEALL @@ -579,6 +579,7 @@ LIST_at91=" \ at91sam9g20ek \ at91sam9rlek \ cmc_pu2 \ + csb337 \ csb637 \ kb9202 \ mp2usb \ --- a/Makefile +++ b/Makefile @@ -2638,6 +2638,9 @@ at91rm9200ek_config : unconfig cmc_pu2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200 +csb337_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t csb337 NULL at91rm9200 + csb637_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200 --- /dev/null +++ b/board/csb337/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS += $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + --- /dev/null +++ b/board/csb337/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 --- /dev/null +++ b/board/csb337/csb337.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2009 David Brownell + * + * Based on csb637 support: + * + * (C) Copyright 2005 + * REA Elektronik GmbH <www.rea.de> + * Anders Larsen <alarsen(a)rea.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/AT91RM9200.h> +#include <at91rm9200_net.h> +#include <lxt971a.h> + +DECLARE_GLOBAL_DATA_PTR; + + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_CSB337; + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET) + +/* The AT91 lxt972 glue modified the original lxt971 code by + * changing names and generalizing a bit. So we use "lxt972" + * names here even though the CSB337 has an lxt971 chip. + */ +extern unsigned char lxt972_InitPhy(AT91S_EMAC *mac); +extern unsigned lxt972_IsPhyConnected(AT91S_EMAC *mac); +extern unsigned char lxt972_GetLinkSpeed(AT91S_EMAC *mac); +extern unsigned char lxt972_AutoNegotiate(AT91S_EMAC *mac, int *status); + +void at91rm9200_GetPhyInterface(AT91S_PhyOps *ops) +{ + ops->Init = lxt972_InitPhy; + ops->IsPhyConnected = lxt972_IsPhyConnected; + ops->GetLinkSpeed = lxt972_GetLinkSpeed; + ops->AutoNegotiate = lxt972_AutoNegotiate; +} + +#endif --- /dev/null +++ b/board/csb337/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} --- /dev/null +++ b/include/configs/csb337.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de> + * Anders Larsen <alarsen(a)rea.de> + * + * Configuation settings for the Cogent CSB337 board. + * Modified from CSB637 settings. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> + +/* CSB337 board from Cogent */ +#define CONFIG_MACH_CSB337 +#define CONFIG_AT91RM9200 + +//#define CONFIG_SKIP_LOWLEVEL_INIT + +#define AT91_SLOW_CLOCK 32768 /* slow clock crystal */ +#define AT91_MAIN_CLOCK 3686400 /* 3.6864 MHz crystal */ + +#define CONFIG_SYS_USE_MAIN_OSCILLATOR + +/* default timings shipped by Cogent (PLLA --> MCK): + * 184.32 MHz for CPU (PLLA) + * 46.08 MHz for memory and peripherals (PLL/4) + * 96.00 MHz for USB (PLLB) + */ +#define AT91_PLLA_DIV 1 +#define AT91_PLLA_MULT 50 +#define AT91_PLLA_CLOCK ((AT91_MAIN_CLOCK / AT91_PLLA_DIV) * AT91_PLLA_MULT) + +#define AT91_PLLB_DIV 24 +#define AT91_PLLB_MULT 625 +#define AT91_PLLB_CLOCK ((AT91_MAIN_CLOCK / AT91_PLLB_DIV) * AT91_PLLB_MULT) + +#define AT91C_MASTER_CLOCK (AT91_PLLA_CLOCK / 4) + +#define CONFIG_SYS_HZ 1000 + +/* NOTE: uses TC0, not system timer. */ +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) + +/* clocks */ +#if 0 /* can't use this from startup.S, sigh */ +#define CONFIG_SYS_PLLAR_VAL \ + ( AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2 | (0x3e << 8) \ + | ((AT91_PLLA_MULT - 1) << 16) | (AT91_PLLA_DIV << 0)) +#define CONFIG_SYS_PLLBR_VAL \ + ( AT91C_CKGR_USB_PLL | AT91C_CKGR_OUTB_0 | (0x3e << 8) \ + | ((AT91_PLLB_MULT - 1) << 16) | (AT91_PLLB_DIV << 0)) +#define CONFIG_SYS_MCKR_VAL \ + (AT91C_PMC_MDIV_4 | AT91C_PMC_CSS_PLLA_CLK) +#else +#define CONFIG_SYS_PLLAR_VAL 0x20313e01 /* 184.32 MHz */ +#define CONFIG_SYS_PLLBR_VAL 0x12703e18 /* 96.00 MHz (+div2) */ +#define CONFIG_SYS_MCKR_VAL 0x00000302 /* 46.00 MHz */ +#endif + +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 /* NOTE: RESERVED ADDR! */ +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 /* NOTE: RESERVED ADDR! */ +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 /* NOTE: RESERVED ADDR! */ +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 /* NOTE: READ-ONLY REG! */ +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 /* NOTE: READ-ONLY REG! */ + +/* 32 bit bus */ +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS0=SMC, CS1=SDRAM */ +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 /* internal d15..d0 pullups */ +#define CONFIG_SYS_PIOC_ASR_VAL 0Xffff0000 /* pc31..pc16 are d31..d16 */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xffff0000 /* internal d31..d16 pullups */ + +/* CS0 == 16 bit flash */ +#define CONFIG_SYS_SMC_CSR0_VAL 0x1100328b /* 16 bit, 2 TDF, 10 WS */ + +/* CS1 == 32 bit SDRAM; timings are a function of the master clock speed */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188b0d5 /* SDRAM timings */ +#define CONFIG_SYS_SDRC_TR_VAL 0x00000200 /* Write refresh rate */ + +/* except maybe for SDRAM1, none of these are board-specic */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of SDRAM + mode register value */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* scratch value written to SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ + +/* define one of CONFIG_{DBGU,USART0,USART1} for console */ +#define CONFIG_AT91RM9200_USART +#define CONFIG_DBGU + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600,} + +/* RAM info */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE SZ_32M + +/* NOR flash (boot device) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* NOR FLASH - one 28F640J03A, 16 bits */ +#define PHYS_FLASH_SIZE SZ_8M +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware protection */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 64 + +#define NOR_SECTOR_SIZE SZ_128K + +#define CONFIG_MTD_PARTITIONS + +/* Ethernet, using full MII */ +#define CONFIG_DRIVER_ETHER + +#if 0 +/* REVISIT: USB failed to enumerate devices of any kind ... sw issues */ + +/* allow loading from USB media */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91-ohci" +#define CONFIG_USB_STORAGE +#endif + +/* I2C, RTC */ +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x08 /* SMBus host address */ + +#define CONFIG_RTC_DS1307 + +/* basic commands; and ones that need driver support */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_XIMG + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_PING + +#ifdef CONFIG_USB_OHCI_NEW +#define CONFIG_CMD_USB +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#endif + +/* general U-Boot configuration */ +#undef CONFIG_USE_IRQ /* no IRQ/FIQ stuff */ + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "CSB337# " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_TIMESTAMP + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_NET_RETRY_COUNT 10 + +#define CONFIG_STACKSIZE SZ_64K /* regular stack */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ +#define CONFIG_SYS_MALLOC_LEN SZ_512K /* heap */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_16M) +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM + +#define CONFIG_SYS_CBSIZE SZ_1K /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (2*CONFIG_SYS_CBSIZE) + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +/* flash layout: 3 sectors U-Boot, 1 sector env ... rest is configurable */ +#define UBOOT_SIZE (3 * NOR_SECTOR_SIZE) +#define CONFIG_ENV_SECT_SIZE NOR_SECTOR_SIZE + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + UBOOT_SIZE) + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0" \ + ":512k(bootloader)ro,-(filesystem)" + +#endif /* __CONFIG_H */

3 6

[U-Boot] [PATCH 1/4] api_examples/Makefile: Split up variable declarations
by Peter Tyser 11 Jul '09

11 Jul '09

This cleans up the Makefile a bit and simplifies future changes Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- These are some similar changes to the ones I made to the tools directory recently. It gets rid of symlinking source files which has the side benefit of resolving the out of tree build error for the API code. api_examples/Makefile | 15 +++++++++++---- 1 files changed, 11 insertions(+), 4 deletions(-) diff --git a/api_examples/Makefile b/api_examples/Makefile index 4c01437..be0b462 100644 --- a/api_examples/Makefile +++ b/api_examples/Makefile @@ -45,13 +45,20 @@ COBJS := $(COBJS-y) SOBJS := $(SOBJS-y) LIB = $(obj)libglue.a -LIBCOBJS-$(CONFIG_API) += glue.o crc32.o ctype.o string.o vsprintf.o \ - libgenwrap.o +LIBCOBJS-$(CONFIG_API) += glue.o +LIBCOBJS-$(CONFIG_API) += crc32.o +LIBCOBJS-$(CONFIG_API) += ctype.o +LIBCOBJS-$(CONFIG_API) += string.o +LIBCOBJS-$(CONFIG_API) += vsprintf.o +LIBCOBJS-$(CONFIG_API) += libgenwrap.o LIBCOBJS := $(LIBCOBJS-y) -LIBOBJS = $(addprefix $(obj),$(SOBJS) $(LIBCOBJS)) +LIBOBJS += $(addprefix $(obj),$(SOBJS)) +LIBOBJS += $(addprefix $(obj),$(LIBCOBJS)) -SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(SOBJS:.o=.S) +SRCS += $(COBJS:.o=.c) +SRCS += $(LIBCOBJS:.o=.c) +SRCS += $(SOBJS:.o=.S) OBJS := $(addprefix $(obj),$(COBJS)) ELF := $(addprefix $(obj),$(ELF)) BIN := $(addprefix $(obj),$(BIN)) -- 1.6.2.1

3 8

[U-Boot] [PATCH 1/2 V2] Move libgcc inclusion from common Makefile to platform configs files
by Jean-Christophe PLAGNIOL-VILLARD 11 Jul '09

11 Jul '09

This patch moves the libgcc Makefile inclusion from the toplevel Makefile to the arch_config.mk files. This is in preparation for the ARM architecture to move away from including libgcc function and only using self-contained U-Boot functions as done in Linux. Currently in the next branch all the ARM boards that use the nand are broken due to the adding of the 64 Bit device size support. In the past we have seen problems with different toolchains due to EABI, FPU as example. With this patch and the following one we move away from all these problems and we will be able to have full control to have a functions embedded into u-boot. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- Rebased against current HEAD Best Regards, J. Makefile | 2 +- api_examples/Makefile | 4 +--- arm_config.mk | 2 ++ avr32_config.mk | 2 ++ blackfin_config.mk | 2 ++ board/netstar/Makefile | 4 +--- board/sl8245/config.mk | 1 - board/trab/Makefile | 2 -- board/voiceblue/Makefile | 4 +--- examples/Makefile | 2 +- i386_config.mk | 2 ++ m68k_config.mk | 2 ++ microblaze_config.mk | 2 ++ mips_config.mk | 2 ++ nios2_config.mk | 2 ++ nios_config.mk | 2 ++ ppc_config.mk | 2 ++ sh_config.mk | 2 ++ sparc_config.mk | 2 ++ 19 files changed, 29 insertions(+), 14 deletions(-) diff --git a/Makefile b/Makefile index 6a2dd9f..8035831 100644 --- a/Makefile +++ b/Makefile @@ -288,7 +288,7 @@ LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) # Add GCC lib -PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc +PLATFORM_LIBS += $(PLATFORM_LIBGCC) ifeq ($(CONFIG_NAND_U_BOOT),y) NAND_SPL = nand_spl diff --git a/api_examples/Makefile b/api_examples/Makefile index 4c01437..4bfa7e6 100644 --- a/api_examples/Makefile +++ b/api_examples/Makefile @@ -56,8 +56,6 @@ OBJS := $(addprefix $(obj),$(COBJS)) ELF := $(addprefix $(obj),$(ELF)) BIN := $(addprefix $(obj),$(BIN)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - CPPFLAGS += -I.. all: $(obj).depend $(OBJS) $(LIB) $(ELF) $(BIN) @@ -70,7 +68,7 @@ $(ELF): $(obj)%: $(obj)%.o $(LIB) $(LD) $(obj)crt0.o -Ttext $(LOAD_ADDR) \ -o $@ $< $(LIB) \ - -L$(gcclibdir) -lgcc + $(PLATFORM_LIBGCC) $(BIN): $(obj)%.bin: $(obj)% diff --git a/arm_config.mk b/arm_config.mk index c4cf99d..b88a3f2 100644 --- a/arm_config.mk +++ b/arm_config.mk @@ -24,3 +24,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/avr32_config.mk b/avr32_config.mk index 441caa4..8569d5f 100644 --- a/avr32_config.mk +++ b/avr32_config.mk @@ -23,3 +23,5 @@ PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_LDFLAGS += --relax + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/blackfin_config.mk b/blackfin_config.mk index 989e976..1534c0d 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -60,3 +60,5 @@ LDR_FLAGS += $(LDR_FLAGS-y) ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),) LDSCRIPT = $(obj)lib_$(ARCH)/u-boot.lds endif + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/board/netstar/Makefile b/board/netstar/Makefile index 91bac38..1cc2722 100644 --- a/board/netstar/Makefile +++ b/board/netstar/Makefile @@ -36,8 +36,6 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - LOAD_ADDR = 0x10400000 LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds lnk = $(if $(obj),$(obj),.) @@ -55,7 +53,7 @@ $(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \ -L$(obj)../../examples -lstubs \ -L$(obj)../../lib_generic -lgeneric \ - -L$(gcclibdir) -lgcc + $(PLATFROM_LIBGCC) $(OBJCOPY) -O srec $(<:.o=) $@ $(obj)eeprom.bin: $(obj)eeprom.srec diff --git a/board/sl8245/config.mk b/board/sl8245/config.mk index 022512b..299fc6c 100644 --- a/board/sl8245/config.mk +++ b/board/sl8245/config.mk @@ -28,4 +28,3 @@ TEXT_BASE = 0xFFF00000 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -PLATFORM_LIBS += $(shell $(CC) -print-libgcc-file-name) diff --git a/board/trab/Makefile b/board/trab/Makefile index 30e5fbb..a3661c4 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -36,8 +36,6 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) OBJS_FKT := $(addprefix $(obj),$(COBJS_FKT)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - LOAD_ADDR = 0xc100000 ######################################################################### diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile index e7c1cbb..0d1e079 100644 --- a/board/voiceblue/Makefile +++ b/board/voiceblue/Makefile @@ -33,8 +33,6 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c eeprom_start.S OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - LOAD_ADDR = 0x10400000 LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds lnk = $(if $(obj),$(obj),.) @@ -49,7 +47,7 @@ $(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \ -L$(obj)../../examples -lstubs \ -L$(obj)../../lib_generic -lgeneric \ - -L$(gcclibdir) -lgcc + $(PLATFROM_LIBGCC) $(OBJCOPY) -O srec $(<:.o=) $@ $(obj)eeprom.bin: $(obj)eeprom.srec diff --git a/examples/Makefile b/examples/Makefile index dbcfa92..5bd13f1 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -178,7 +178,7 @@ $(ELF): $(obj)%: $(obj)%.o $(LIB) $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ - -L$(gcclibdir) -lgcc + $(PLATFORM_LIBGCC) $(SREC): $(obj)%.srec: $(obj)% diff --git a/i386_config.mk b/i386_config.mk index 9e6d37d..03b2538 100644 --- a/i386_config.mk +++ b/i386_config.mk @@ -22,3 +22,5 @@ # PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/m68k_config.mk b/m68k_config.mk index 12bd27c..f0c963b 100644 --- a/m68k_config.mk +++ b/m68k_config.mk @@ -23,3 +23,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ PLATFORM_LDFLAGS += -n + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/microblaze_config.mk b/microblaze_config.mk index e44c79e..5f78c5c 100644 --- a/microblaze_config.mk +++ b/microblaze_config.mk @@ -25,3 +25,5 @@ # PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/mips_config.mk b/mips_config.mk index 05eb05d..3ae6c19 100644 --- a/mips_config.mk +++ b/mips_config.mk @@ -23,6 +23,8 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + # # From Linux arch/mips/Makefile # diff --git a/nios2_config.mk b/nios2_config.mk index 3f23b56..1bf4992 100644 --- a/nios2_config.mk +++ b/nios2_config.mk @@ -24,3 +24,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ PLATFORM_CPPFLAGS += -ffixed-r15 -G0 + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/nios_config.mk b/nios_config.mk index 1cf0f32..d72db7d 100644 --- a/nios_config.mk +++ b/nios_config.mk @@ -23,3 +23,5 @@ # PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/ppc_config.mk b/ppc_config.mk index c95b3b1..74a4f11 100644 --- a/ppc_config.mk +++ b/ppc_config.mk @@ -24,6 +24,8 @@ PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + # # When cross-compiling on NetBSD, we have to define __PPC__ or else we # will pick up a va_list declaration that is incompatible with the diff --git a/sh_config.mk b/sh_config.mk index 49d50f7..311699a 100644 --- a/sh_config.mk +++ b/sh_config.mk @@ -22,3 +22,5 @@ # PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc diff --git a/sparc_config.mk b/sparc_config.mk index 87f745f..15d2f5b 100644 --- a/sparc_config.mk +++ b/sparc_config.mk @@ -22,3 +22,5 @@ # PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ + +PLATFORM_LIBGCC += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -- 1.6.3.1

5 15

[U-Boot] [PATCH v3] remove _IO_BASE and KSEG1ADDR from board configuration files
by Timur Tabi 11 Jul '09

11 Jul '09

The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet driver, but the code that used that macro was removed over a year ago, so board configuration files no longer need to define it. The _IO_BASE macro is also automatically defined to 0 if it isn't already set, so there's no need to define that macro either in the board configuration files. Signed-off-by: Timur Tabi <timur(a)freescale.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Acked-by: Andy Fleming <afleming(a)freescale.com> Acked-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- v3: removed the change for PN62.h, which does not have _IO_BASE at 0 include/configs/HIDDEN_DRAGON.h | 4 +--- include/configs/M5253DEMO.h | 1 - include/configs/M5253EVBE.h | 1 - include/configs/M54455EVB.h | 1 - include/configs/MPC8349ITX.h | 7 ------- include/configs/MPC8536DS.h | 6 ------ include/configs/MPC8544DS.h | 6 ------ include/configs/MPC8572DS.h | 6 ------ include/configs/MPC8610HPCD.h | 4 ---- include/configs/MPC8641HPCN.h | 4 ---- include/configs/MVBLM7.h | 2 -- include/configs/P2020DS.h | 6 ------ include/configs/mpc7448hpc2.h | 4 ---- include/configs/r2dplus.h | 2 -- 14 files changed, 1 insertions(+), 53 deletions(-) diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index f6777b9..251fe67 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -103,9 +103,7 @@ #define PCI_ENET1_MEMADDR 0x81000000 #define CONFIG_RTL8139 -#define _IO_BASE 0x00000000 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) + /* Make sure the ethaddr can be overwritten TODO: Remove this on final product */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 50b3a03..5e86e4c 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -85,7 +85,6 @@ # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -# define _IO_BASE 0 #endif #define CONFIG_NET_MULTI 1 diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index cf8b773..df6970c 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -91,7 +91,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -#define _IO_BASE 0 #define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 101dced..87f3a73 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -180,7 +180,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -#define _IO_BASE 0 /* Realtime clock */ #define CONFIG_MCFRTC diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index f2e574b..d4d3256 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -360,16 +360,9 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ #endif -#define _IO_BASE 0x00000000 /* points to PCI I/O space */ - #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR 0x00000000 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9e00b89..7085d28 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -427,12 +427,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #undef CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 59cfde6..1d8fecf 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -340,12 +340,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_TULIP #define CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2aba689..c7385e4 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -484,12 +484,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #undef CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1091043..2f40ef4 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -280,10 +280,6 @@ #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) -#define _IO_BASE 0x00000000 - /* controller 1, Base address 0xa000 */ #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d8042fb..de2cf1a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -348,10 +348,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 - #ifdef CONFIG_PHYS_64BIT /* * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9675205..ac8cb57 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -193,8 +193,6 @@ #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 -#define _IO_BASE 0x00000000 - #define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 3 diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a39ff26..443bc40 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -517,12 +517,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #define CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 7d42155..4f98ba4 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -124,8 +124,6 @@ /* Networking Configuration */ -#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ - #define CONFIG_TSI108_ETH #define CONFIG_TSI108_ETH_NUM_PORTS 2 @@ -303,8 +301,6 @@ #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */ -#define _IO_BASE 0x00000000 /* points to PCI I/O space */ - /* PCI Config Space mapping */ #define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 6fa1eaf..37d4fff 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -123,7 +123,5 @@ */ #define CONFIG_NET_MULTI #define CONFIG_RTL8139 -#define _IO_BASE 0x00000000 -#define KSEG1ADDR(x) (x) #endif /* __CONFIG_H */ -- 1.6.0.6

3 3

[U-Boot] [PATCH v6] board support patch for phyCORE-MPC5200B-tiny
by Jon Smirl 10 Jul '09

10 Jul '09

Add support for the Phytec phyCORE-MPC5200B-tiny. Code originally from Pengutronix.de. Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on Timer 0/1 Signed-off-by: Jon Smirl <jonsmirl(a)gmail.com> --- MAINTAINERS | 4 MAKEALL | 1 Makefile | 9 + board/phytec/pcm030/Makefile | 50 ++++ board/phytec/pcm030/config.mk | 41 +++ board/phytec/pcm030/mt46v32m16-75.h | 37 +++ board/phytec/pcm030/pcm030.c | 220 +++++++++++++++++ cpu/mpc5xxx/ide.c | 3 doc/README.phytec.pcm030 | 46 ++++ include/configs/pcm030.h | 444 +++++++++++++++++++++++++++++++++++ 10 files changed, 855 insertions(+), 0 deletions(-) create mode 100644 board/phytec/pcm030/Makefile create mode 100644 board/phytec/pcm030/config.mk create mode 100644 board/phytec/pcm030/mt46v32m16-75.h create mode 100644 board/phytec/pcm030/pcm030.c create mode 100644 doc/README.phytec.pcm030 create mode 100644 include/configs/pcm030.h diff --git a/MAINTAINERS b/MAINTAINERS index bba6ce9..bfcd991 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -409,6 +409,10 @@ Andre Schwarz <andre.schwarz(a)matrix-vision.de> mvbc_p MPC5200 mvblm7 MPC8343 +Jon Smirl <jonsmirl(a)gmail.com> + + pcm030 MPC5200 + Timur Tabi <timur(a)freescale.com> MPC8349E-mITX MPC8349 diff --git a/MAKEALL b/MAKEALL index fd31252..d6b6599 100755 --- a/MAKEALL +++ b/MAKEALL @@ -60,6 +60,7 @@ LIST_5xxx=" \ munices \ MVBC_P \ o2dnt \ + pcm030 \ pf5200 \ PM520 \ TB5200 \ diff --git a/Makefile b/Makefile index 4bf4442..8cd99ce 100644 --- a/Makefile +++ b/Makefile @@ -696,6 +696,15 @@ MVBC_P_config: unconfig o2dnt_config: unconfig @$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt +pcm030_config \ +pcm030_LOWBOOT_config: unconfig + @ >include/config.h + @[ -z "$(findstring LOWBOOT_,$@)" ] || \ + { echo "TEXT_BASE = 0xFF000000" >$(obj)board/phytec/pcm030/config.tmp ; \ + echo "... with LOWBOOT configuration" ; \ + } + @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec + pf5200_config: unconfig @$(MKCONFIG) pf5200 ppc mpc5xxx pf5200 esd diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile new file mode 100644 index 0000000..22ce8e6 --- /dev/null +++ b/board/phytec/pcm030/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2007 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/phytec/pcm030/config.mk b/board/phytec/pcm030/config.mk new file mode 100644 index 0000000..92fecc6 --- /dev/null +++ b/board/phytec/pcm030/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# phyCORE-MPC5200B tiny board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFF000000 boot low +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h new file mode 100644 index 0000000..d69c09c --- /dev/null +++ b/board/phytec/pcm030/mt46v32m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas(a)motorola.com. + * + * Eric Schumann, Phytec Messtechnik + * adapted for mt46v32m16-75 DDR-RAM + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x71500F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x47770000 + +#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c new file mode 100644 index 0000000..6a93874 --- /dev/null +++ b/board/phytec/pcm030/pcm030.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas(a)motorola.com. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messtechnik GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> +#include <asm-ppc/io.h> + +#include "mt46v32m16-75.h" + +#ifndef CONFIG_SYS_RAMBOOT +static void sdram_start(int hi_addr) +{ + volatile struct mpc5xxx_cdm *cdm = + (struct mpc5xxx_cdm *)MPC5XXX_CDM; + volatile struct mpc5xxx_sdram *sdram = + (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); + + /* precharge all banks */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); + +#ifdef SDRAM_DDR + /* set mode register: extended mode */ + out_be32 (&sdram->mode, (SDRAM_EMODE)); + + /* set mode register: reset DLL */ + out_be32 (&sdram->mode, + (SDRAM_MODE | 0x04000000)); +#endif + + /* precharge all banks */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); + + /* auto refresh */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); + + /* set mode register */ + out_be32 (&sdram->mode, (SDRAM_MODE)); + + /* normal operation */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | hi_addr_bit)); + + /* set CDM clock enable register, set MPC5200B SDRAM bus */ + /* to reduced driver strength */ + out_be32 (&cdm->clock_enable, (0x00CFFFFF)); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make + * real use of CONFIG_SYS_SDRAM_BASE. The code does not + * work if CONFIG_SYS_SDRAM_BASE + * is something else than 0x00000000. + */ + +phys_size_t initdram(int board_type) +{ + volatile struct mpc5xxx_mmap_ctl *mm = + (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + volatile struct mpc5xxx_cdm *cdm = + (struct mpc5xxx_cdm *)MPC5XXX_CDM; + volatile struct mpc5xxx_sdram *sdram = + (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CONFIG_SYS_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + /* 256MB at 0x0 */ + out_be32 (&mm->sdram0, 0x0000001b); + /* disabled */ + out_be32 (&mm->sdram1, 0x10000000); + + /* setup config registers */ + out_be32 (&sdram->config1, SDRAM_CONFIG1); + out_be32 (&sdram->config2, SDRAM_CONFIG2); + +#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY) + /* set tap delay */ + out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); + sdram_start(1); + test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + out_be32 (&mm->sdram0, + (0x13 + __builtin_ffs(dramsize >> 20) - 1)); + } else { + /* disabled */ + out_be32 (&mm->sdram0, 0); + } + +#else /* CONFIG_SYS_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = in_be32(&mm->sdram0) & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = in_be32(&mm->sdram1) & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CONFIG_SYS_RAMBOOT */ + + return dramsize + dramsize2; +} + +int checkboard(void) +{ + puts("Board: phyCORE-MPC5200B-tiny\n"); + return 0; +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t * bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) + +#define GPIO_PSC2_4 0x02000000UL + +void init_ide_reset(void) +{ + volatile struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + debug("init_ide_reset\n"); + + /* Configure PSC2_4 as GPIO output for ATA reset */ + setbits_be32(&wu_gpio->enable, GPIO_PSC2_4); + setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4); + /* Deassert reset */ + setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); +} + +void ide_set_reset(int idereset) +{ + volatile struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + debug("ide_reset(%d)\n", idereset); + + if (idereset) { + clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else + setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); +} +#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ + diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 9e8f29b..d337abb 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -45,6 +45,9 @@ int ide_preinit (void) #if defined(CONFIG_SYS_ATA_CS_ON_I2C2) /* ATA cs0/1 on i2c2 clk/io */ reg = (reg & ~0x03000000ul) | 0x02000000ul; +#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01) + /* ATA cs0/1 on Timer 0/1 */ + reg = (reg & ~0x03000000ul) | 0x03000000ul; #else /* ATA cs0/1 on Local Plus cs4/5 */ reg = (reg & ~0x03000000ul) | 0x01000000ul; diff --git a/doc/README.phytec.pcm030 b/doc/README.phytec.pcm030 new file mode 100644 index 0000000..35a411a --- /dev/null +++ b/doc/README.phytec.pcm030 @@ -0,0 +1,46 @@ +To build RAMBOOT, replace this section the main Makefile + +pcm030_config \ +pcm030_RAMBOOT_config \ +pcm030_LOWBOOT_config: unconfig + @ >include/config.h + @[ -z "$(findstring LOWBOOT_,$@)" ] || \ + { echo "TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \ + echo "... with LOWBOOT configuration" ; \ + } + @[ -z "$(findstring RAMBOOT_,$@)" ] || \ + { echo "TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\ + config.tmp ; \ + echo "... with RAMBOOT configuration" ; \ + echo "... remember to make sure that MBAR is already \ + switched to 0xF0000000 !!!" ; \ + } + @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec + @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1" + + +Alternative SDRAM settings: + +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x715f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 + +/* Settings for XLB = 99 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714b0f00 +#define SDRAM_CONFIG1 0x63611730 +#define SDRAM_CONFIG2 0x47670000 + +The board ships default with the environment in EEPROM +Moving the environment to flash can be more reliable + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + + + diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h new file mode 100644 index 0000000..8acf3c7 --- /dev/null +++ b/include/configs/pcm030.h @@ -0,0 +1,444 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messatechnik GmbH + * + * (C) Copyright 2009 + * Jon Smirl <jonsmirl(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" + +/*----------------------------------------------------------------------------- +High Level Configuration Options +(easy to change) +-----------------------------------------------------------------------------*/ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ +#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ + /* FEC configuration and IDE */ +#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------------- +Serial console configuration +-----------------------------------------------------------------------------*/ +#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */ + /*define gps port conf. */ + /* register later on to */ + /*enable UART function! */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +#if (TEXT_BASE == 0xFF000000) /* Boot low */ +#define CONFIG_SYS_LOWBOOT 1 +#endif +/* RAMBOOT will be defined automatically in memory section */ + +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ + "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" + +/*----------------------------------------------------------------------------- +Autobooting +-----------------------------------------------------------------------------*/ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ + /* even with bootdelay=0 */ +#undef CONFIG_BOOTARGS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\ + "mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uimage=uImage-pcm030\0" \ + "oftree=oftree-pcm030.dtb\0" \ + "jffs2=root-pcm030.jffs2\0" \ + "uboot=u-boot-pcm030.bin\0" \ + "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \ + " $(mtdparts) rw\0" \ + "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \ + " rootfstype=jffs2\0" \ + "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \ + " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \ + "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \ + " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \ + "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \ + "0xfff40000\0" \ + " cp.b 0x400000 0xff040000 $(filesize)\0" \ + "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \ + "cp.b 0x400000 0xff200000 $(filesize)\0" \ + "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \ + " cp.b 0x400000 0xfff40000 $(filesize)\0" \ + "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \ + " cp.b 0x400000 0xFFF00000 $(filesize)\0" \ + "unlock=yes\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run bcmd_flash" + +/*-------------------------------------------------------------------------- +IPB Bus clocking configuration. + ---------------------------------------------------------------------------*/ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ + +/*------------------------------------------------------------------------- + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + * -----------------------------------------------------------------------*/ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 +#define CONFIG_SYS_XLB_PIPELINING 1 + +/*--------------------------------------------------------------------------- + I2C configuration +---------------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/*--------------------------------------------------------------------------- + EEPROM CAT24WC32 configuration +---------------------------------------------------------------------------*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ +#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_SIZE 2048 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 + +/*--------------------------------------------------------------------------- +RTC configuration +---------------------------------------------------------------------------*/ +#define RTC +#define CONFIG_RTC_PCF8563 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +/*--------------------------------------------------------------------------- + Flash configuration +---------------------------------------------------------------------------*/ + +#define CONFIG_SYS_FLASH_BASE 0xff000000 +#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ + /* (= chip selects) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* + * Use also hardware protection. This seems required, as the BDI uses + * hardware protection. Without this, U-Boot can't work with this sectors, + * as its protection is software only by default + */ +#define CONFIG_SYS_FLASH_PROTECTION 1 + +/*--------------------------------------------------------------------------- + Environment settings +---------------------------------------------------------------------------*/ + +/* pcm030 ships with environment is EEPROM by default */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ + /*beginning of the EEPROM */ +#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE + +#define CONFIG_ENV_OVERWRITE 1 + +/*----------------------------------------------------------------------------- + Memory map +-----------------------------------------------------------------------------*/ +#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ + /* bootloader or debugger config */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 +/* Use SRAM until RAM will be available */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used */ + /* area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes */ + /* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 +#endif + +#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------------- + Ethernet configuration +-----------------------------------------------------------------------------*/ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x01 + +/*--------------------------------------------------------------------------- + GPIO configuration + ---------------------------------------------------------------------------*/ + +/* GPIO port configuration + * + * Pin mapping: + * + * [29:31] = 01x + * PSC1_0 -> AC97 SDATA out + * PSC1_1 -> AC97 SDTA in + * PSC1_2 -> AC97 SYNC out + * PSC1_3 -> AC97 bitclock out + * PSC1_4 -> AC97 reset out + * + * [25:27] = 001 + * PSC2_0 -> CAN 1 Tx out + * PSC2_1 -> CAN 1 Rx in + * PSC2_2 -> CAN 2 Tx out + * PSC2_3 -> CAN 2 Rx in + * PSC2_4 -> GPIO (claimed for ATA reset, active low) + * + * + * [20:23] = 1100 + * PSC3_0 -> UART Tx out + * PSC3_1 -> UART Rx in + * PSC3_2 -> UART RTS (in/out FIXME) + * PSC3_3 -> UART CTS (in/out FIXME) + * PSC3_4 -> LocalPlus Bus CS6 \ + * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5] + * PSC3_6 -> dedicated SPI MOSI out (master case) + * PSC3_7 -> dedicated SPI MISO in (master case) + * PSC3_8 -> dedicated SPI SS out (master case) + * PSC3_9 -> dedicated SPI CLK out (master case) + * + * [18:19] = 01 + * USB_0 -> USB OE out + * USB_1 -> USB Tx- out + * USB_2 -> USB Tx+ out + * USB_3 -> USB RxD (in/out FIXME) + * USB_4 -> USB Rx+ in + * USB_5 -> USB Rx- in + * USB_6 -> USB PortPower out + * USB_7 -> USB speed out + * USB_8 -> USB suspend (in/out FIXME) + * USB_9 -> USB overcurrent in + * + * [17] = 0 + * USB differential mode + * + * [16] = 0 + * PCI enabled + * + * [12:15] = 0101 + * ETH_0 -> ETH Txen + * ETH_1 -> ETH TxD0 + * ETH_2 -> ETH TxD1 + * ETH_3 -> ETH TxD2 + * ETH_4 -> ETH TxD3 + * ETH_5 -> ETH Txerr + * ETH_6 -> ETH MDC + * ETH_7 -> ETH MDIO + * ETH_8 -> ETH RxDv + * ETH_9 -> ETH RxCLK + * ETH_10 -> ETH Collision + * ETH_11 -> ETH TxD + * ETH_12 -> ETH RxD0 + * ETH_13 -> ETH RxD1 + * ETH_14 -> ETH RxD2 + * ETH_15 -> ETH RxD3 + * ETH_16 -> ETH Rxerr + * ETH_17 -> ETH CRS + * + * [9:11] = 101 + * PSC6_0 -> UART RxD in + * PSC6_1 -> UART CTS (in/out FIXME) + * PSC6_2 -> UART TxD out + * PSC6_3 -> UART RTS (in/out FIXME) + * + * [2:3/6:7] = 00/11 + * TMR_0 -> ATA_CS0 out + * TMR_1 -> ATA_CS1 out + * TMR_2 -> GPIO + * TMR_3 -> GPIO + * TMR_4 -> GPIO + * TMR_5 -> GPIO + * TMR_6 -> GPIO + * TMR_7 -> GPIO + * I2C_0 -> I2C 1 Clock out + * I2C_1 -> I2C 1 IO in/out + * I2C_2 -> I2C 2 Clock out + * I2C_3 -> I2C 2 IO in/out + * + * [4] = 1 + * PSC3_5 is used as CS7 + * + * [5] = 1 + * PSC3_4 is used as CS6 + * + * [1] = 0 + * gpio_wkup_7 is GPIO + * + * [0] = 0 + * gpio_wkup_6 is GPIO + * + */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12 + +/*----------------------------------------------------------------------------- + Miscellaneous configurable options +-------------------------------------------------------------------------------*/ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_DISPLAY_BOARDINFO 1 + +/*----------------------------------------------------------------------------- + Various low-level settings +-----------------------------------------------------------------------------*/ +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE + +/* no burst access on the LPB */ +#define CONFIG_SYS_CS_BURST 0x00000000 +/* one deadcycle for the 33MHz statemachine */ +#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 +/* one additional waitstate for the 33MHz statemachine */ +#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00 +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE + +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*--------------------------------------------------------------------------- + IDE/ATA stuff Supports IDE harddisk +----------------------------------------------------------------------------*/ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#define CONFIG_SYS_ATA_CS_ON_TIMER01 +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ +#define CONFIG_IDE_PREINIT +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA +/* Offset for data I/O */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) +/* Offset for alternate registers */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 +#define CONFIG_ATAPI 1 + +/* we enable IDE and FAT support, so we also need partition support */ +#define CONFIG_DOS_PARTITION 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,5200@0" +#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN +#define OF_SOC "soc5200@f0000000" +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400" + +#endif /* __CONFIG_H */

3 3

[U-Boot] [PATCH 0/6] Blackfin fixes for 2009.08
by Mike Frysinger 10 Jul '09

10 Jul '09

A few fixes and tweaks to use latest code in master. Mike Frysinger (4): Blackfin: bf548-ezkit: bump up monitor size Blackfin: enable -O2 in lib_generic/ for ADI/Bluetechnix boards Blackfin: fix SPI flash speed define name Blackfin: move ALL += u-boot.ldr to blackfin_config.mk Vivi Li (2): Blackfin: bump up default JTAG console timeout Blackfin: bf533-stamp/bf537-stamp: fix env settings for SPI flash Makefile | 4 +--- blackfin_config.mk | 6 ++++-- board/bf518f-ezbrd/config.mk | 3 +++ board/bf526-ezbrd/config.mk | 3 +++ board/bf527-ezkit/config.mk | 3 +++ board/bf533-ezkit/config.mk | 3 +++ board/bf533-stamp/config.mk | 3 +++ board/bf537-stamp/config.mk | 3 +++ board/bf538f-ezkit/config.mk | 3 +++ board/bf548-ezkit/config.mk | 3 +++ board/bf561-ezkit/config.mk | 3 +++ board/cm-bf527/config.mk | 3 +++ board/cm-bf533/config.mk | 3 +++ board/cm-bf537e/config.mk | 3 +++ board/cm-bf548/config.mk | 3 +++ board/cm-bf561/config.mk | 3 +++ board/tcm-bf537/config.mk | 3 +++ cpu/blackfin/jtag-console.c | 2 +- include/configs/bf518f-ezbrd.h | 2 +- include/configs/bf526-ezbrd.h | 2 +- include/configs/bf527-ezkit.h | 2 +- include/configs/bf533-stamp.h | 6 +++--- include/configs/bf537-minotaur.h | 2 +- include/configs/bf537-pnav.h | 2 +- include/configs/bf537-srv1.h | 2 +- include/configs/bf537-stamp.h | 6 +++--- include/configs/bf538f-ezkit.h | 2 +- include/configs/bf548-ezkit.h | 4 ++-- include/configs/blackstamp.h | 2 +- 29 files changed, 67 insertions(+), 22 deletions(-)

2 13

[U-Boot] [PATCH v5] board support patch for phyCORE-MPC5200B-tiny
by Jon Smirl 10 Jul '09

10 Jul '09

Add support for the Phytec phyCORE-MPC5200B-tiny. Code originally from Pengutronix.de. v5 - Rebased onto u-boot/next. Changed official board name to phyCORE-MPC5200B-tiny. Signed-off-by: Jon Smirl <jonsmirl(a)gmail.com> --- MAINTAINERS | 4 MAKEALL | 1 Makefile | 9 + board/phytec/pcm030/Makefile | 50 ++++ board/phytec/pcm030/config.mk | 42 +++ board/phytec/pcm030/mt46v32m16-75.h | 54 ++++ board/phytec/pcm030/pcm030.c | 219 ++++++++++++++++ cpu/mpc5xxx/ide.c | 3 include/configs/pcm030.h | 472 +++++++++++++++++++++++++++++++++++ 9 files changed, 854 insertions(+), 0 deletions(-) create mode 100644 board/phytec/pcm030/Makefile create mode 100644 board/phytec/pcm030/config.mk create mode 100644 board/phytec/pcm030/mt46v32m16-75.h create mode 100644 board/phytec/pcm030/pcm030.c create mode 100644 include/configs/pcm030.h diff --git a/MAINTAINERS b/MAINTAINERS index bba6ce9..bfcd991 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -409,6 +409,10 @@ Andre Schwarz <andre.schwarz(a)matrix-vision.de> mvbc_p MPC5200 mvblm7 MPC8343 +Jon Smirl <jonsmirl(a)gmail.com> + + pcm030 MPC5200 + Timur Tabi <timur(a)freescale.com> MPC8349E-mITX MPC8349 diff --git a/MAKEALL b/MAKEALL index fd31252..d6b6599 100755 --- a/MAKEALL +++ b/MAKEALL @@ -60,6 +60,7 @@ LIST_5xxx=" \ munices \ MVBC_P \ o2dnt \ + pcm030 \ pf5200 \ PM520 \ TB5200 \ diff --git a/Makefile b/Makefile index 4bf4442..fb036c6 100644 --- a/Makefile +++ b/Makefile @@ -696,6 +696,15 @@ MVBC_P_config: unconfig o2dnt_config: unconfig @$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt +pcm030_config \ +pcm030_LOWBOOT_config: unconfig + @ >include/config.h + @[ -z "$(findstring LOWBOOT_,$@)" ] || \ + { echo "TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \ + echo "... with LOWBOOT configuration" ; \ + } + @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec + pf5200_config: unconfig @$(MKCONFIG) pf5200 ppc mpc5xxx pf5200 esd diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile new file mode 100644 index 0000000..22ce8e6 --- /dev/null +++ b/board/phytec/pcm030/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2007 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/phytec/pcm030/config.mk b/board/phytec/pcm030/config.mk new file mode 100644 index 0000000..5d3469c --- /dev/null +++ b/board/phytec/pcm030/config.mk @@ -0,0 +1,42 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# phyCORE-MPC5200B tiny board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFF000000 boot low +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board + diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h new file mode 100644 index 0000000..4b501c6 --- /dev/null +++ b/board/phytec/pcm030/mt46v32m16-75.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas(a)motorola.com. + * + * Eric Schumann, Phytec Messtechnik + * adapted for mt46v32m16-75 DDR-RAM + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x71500F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x47770000 + +/* +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x715f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +*/ + +/* Settings for XLB = 99 MHz */ +/* +#define SDRAM_MODE 0x008D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714b0f00 +#define SDRAM_CONFIG1 0x63611730 +#define SDRAM_CONFIG2 0x47670000 +*/ + +#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c new file mode 100644 index 0000000..34e5245 --- /dev/null +++ b/board/phytec/pcm030/pcm030.c @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas(a)motorola.com. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messtechnik GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> +#include <asm-ppc/io.h> + +#include "mt46v32m16-75.h" + +#ifndef CONFIG_SYS_RAMBOOT +static void sdram_start(int hi_addr) +{ + volatile struct mpc5xxx_cdm *cdm = + (struct mpc5xxx_cdm *)MPC5XXX_CDM; + volatile struct mpc5xxx_sdram *sdram = + (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); + + /* precharge all banks */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); + +#ifdef SDRAM_DDR + /* set mode register: extended mode */ + out_be32 (&sdram->mode, (SDRAM_EMODE)); + + /* set mode register: reset DLL */ + out_be32 (&sdram->mode, + (SDRAM_MODE | 0x04000000)); +#endif + + /* precharge all banks */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); + + /* auto refresh */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); + + /* set mode register */ + out_be32 (&sdram->mode, (SDRAM_MODE)); + + /* normal operation */ + out_be32 (&sdram->ctrl, + (SDRAM_CONTROL | hi_addr_bit)); + + /* set CDM clock enable register, set MPC5200B SDRAM bus */ + /* to reduced driver strength */ + out_be32 (&cdm->clock_enable, (0x00CFFFFF)); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make + * real use of CONFIG_SYS_SDRAM_BASE. The code does not + * work if CONFIG_SYS_SDRAM_BASE + * is something else than 0x00000000. + */ + +phys_size_t initdram(int board_type) +{ + volatile struct mpc5xxx_mmap_ctl *mm = + (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + volatile struct mpc5xxx_cdm *cdm = + (struct mpc5xxx_cdm *)MPC5XXX_CDM; + volatile struct mpc5xxx_sdram *sdram = + (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CONFIG_SYS_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + /* 256MB at 0x0 */ + out_be32 (&mm->sdram0, 0x0000001b); + /* disabled */ + out_be32 (&mm->sdram1, 0x10000000); + + /* setup config registers */ + out_be32 (&sdram->config1, SDRAM_CONFIG1); + out_be32 (&sdram->config2, SDRAM_CONFIG2); + +#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY) + /* set tap delay */ + out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); + sdram_start(1); + test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + out_be32 (&mm->sdram0, + (0x13 + __builtin_ffs(dramsize >> 20) - 1)); + } else + /* disabled */ + out_be32 (&mm->sdram0, 0); + +#else /* CONFIG_SYS_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = in_be32(&mm->sdram0) & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = in_be32(&mm->sdram1) & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CONFIG_SYS_RAMBOOT */ + + return dramsize + dramsize2; +} + +int checkboard(void) +{ + puts("Board: phyCORE-MPC5200B-tiny\n"); + return 0; +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t * bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) + +#define GPIO_PSC2_4 0x02000000UL + +void init_ide_reset(void) +{ + volatile struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + debug("init_ide_reset\n"); + + /* Configure PSC2_4 as GPIO output for ATA reset */ + setbits_be32(&wu_gpio->enable, GPIO_PSC2_4); + setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4); + /* Deassert reset */ + setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); +} + +void ide_set_reset(int idereset) +{ + volatile struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + debug("ide_reset(%d)\n", idereset); + + if (idereset) { + clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else + setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); +} +#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ + diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 9e8f29b..0129180 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -45,6 +45,9 @@ int ide_preinit (void) #if defined(CONFIG_SYS_ATA_CS_ON_I2C2) /* ATA cs0/1 on i2c2 clk/io */ reg = (reg & ~0x03000000ul) | 0x02000000ul; +#elif defined(CONFIG_PHYCORE_MPC5200B_TINY) + /* ATA cs0/1 on Timer 0/1 */ + reg = (reg & ~0x03000000ul) | 0x03000000ul; #else /* ATA cs0/1 on Local Plus cs4/5 */ reg = (reg & ~0x03000000ul) | 0x01000000ul; diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h new file mode 100644 index 0000000..6ca7778 --- /dev/null +++ b/include/configs/pcm030.h @@ -0,0 +1,472 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2006 + * Eric Schumann, Phytec Messatechnik GmbH + * + * (C) Copyright 2009 + * Jon Smirl <jonsmirl(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* #define DEBUG */ + +/* To build RAMBOOT, replace this section the main Makefile +pcm030_config \ +pcm030_RAMBOOT_config \ +pcm030_LOWBOOT_config: unconfig + @ >include/config.h + @[ -z "$(findstring LOWBOOT_,$@)" ] || \ + { echo "TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \ + echo "... with LOWBOOT configuration" ; \ + } + @[ -z "$(findstring RAMBOOT_,$@)" ] || \ + { echo "TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\ + config.tmp ; \ + echo "... with RAMBOOT configuration" ; \ + echo "... remember to make sure that MBAR is already \ + switched to 0xF0000000 !!!" ; \ + } + @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec + @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1" +*/ + +#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" + +/*----------------------------------------------------------------------------- +High Level Configuration Options +(easy to change) +-----------------------------------------------------------------------------*/ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ +#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ + /* FEC configuration and IDE */ +#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------------- +Serial console configuration +-----------------------------------------------------------------------------*/ +#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */ + /*define gps port conf. */ + /* register later on to */ + /*enable UART function! */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +#if (TEXT_BASE == 0xFF000000) /* Boot low */ +#define CONFIG_SYS_LOWBOOT 1 +#endif +/* RAMBOOT will be defined automatically in memory section */ + +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ + "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" + +/*----------------------------------------------------------------------------- +Autobooting +-----------------------------------------------------------------------------*/ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ + /* even with bootdelay=0 */ +#undef CONFIG_BOOTARGS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\ + "mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uimage=uImage-pcm030\0" \ + "oftree=oftree-pcm030.dtb\0" \ + "jffs2=root-pcm030.jffs2\0" \ + "uboot=u-boot-pcm030.bin\0" \ + "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \ + " $(mtdparts) rw\0" \ + "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \ + " rootfstype=jffs2\0" \ + "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \ + " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \ + "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \ + " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \ + "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \ + "0xfff40000\0" \ + " cp.b 0x400000 0xff040000 $(filesize)\0" \ + "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \ + "cp.b 0x400000 0xff200000 $(filesize)\0" \ + "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \ + " cp.b 0x400000 0xfff40000 $(filesize)\0" \ + "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \ + " cp.b 0x400000 0xFFF00000 $(filesize)\0" \ + "unlock=yes\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run bcmd_flash" + +/*-------------------------------------------------------------------------- +IPB Bus clocking configuration. + ---------------------------------------------------------------------------*/ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ + +/*------------------------------------------------------------------------- + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + * -----------------------------------------------------------------------*/ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 +#define CONFIG_SYS_XLB_PIPELINING 1 + +/*--------------------------------------------------------------------------- + I2C configuration +---------------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/*--------------------------------------------------------------------------- + EEPROM CAT24WC32 configuration +---------------------------------------------------------------------------*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ +#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_SIZE 2048 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 + +/*--------------------------------------------------------------------------- +RTC configuration +---------------------------------------------------------------------------*/ +#define RTC +#define CONFIG_RTC_PCF8563 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +/*--------------------------------------------------------------------------- + Flash configuration +---------------------------------------------------------------------------*/ + +#define CONFIG_SYS_FLASH_BASE 0xff000000 +#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ + /* (= chip selects) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* + * Use also hardware protection. This seems required, as the BDI uses + * hardware protection. Without this, U-Boot can't work with this sectors, + * as its protection is software only by default + */ +#define CONFIG_SYS_FLASH_PROTECTION 1 + +/*--------------------------------------------------------------------------- + Environment settings +---------------------------------------------------------------------------*/ + +/* pcm030 ships with environment is EEPROM by default */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ + /*beginning of the EEPROM */ +#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE + +/* Moving the environment to flash can be more reliable +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +*/ + +#define CONFIG_ENV_OVERWRITE 1 + +/*----------------------------------------------------------------------------- + Memory map +-----------------------------------------------------------------------------*/ +#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ + /* bootloader or debugger config */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 +/* Use SRAM until RAM will be available */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used */ + /* area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes */ + /* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 +#endif + +#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------------- + Ethernet configuration +-----------------------------------------------------------------------------*/ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x01 + +/*--------------------------------------------------------------------------- + GPIO configuration + ---------------------------------------------------------------------------*/ + +/* GPIO port configuration + * + * Pin mapping: + * + * [29:31] = 01x + * PSC1_0 -> AC97 SDATA out + * PSC1_1 -> AC97 SDTA in + * PSC1_2 -> AC97 SYNC out + * PSC1_3 -> AC97 bitclock out + * PSC1_4 -> AC97 reset out + * + * [25:27] = 001 + * PSC2_0 -> CAN 1 Tx out + * PSC2_1 -> CAN 1 Rx in + * PSC2_2 -> CAN 2 Tx out + * PSC2_3 -> CAN 2 Rx in + * PSC2_4 -> GPIO (claimed for ATA reset, active low) + * + * + * [20:23] = 1100 + * PSC3_0 -> UART Tx out + * PSC3_1 -> UART Rx in + * PSC3_2 -> UART RTS (in/out FIXME) + * PSC3_3 -> UART CTS (in/out FIXME) + * PSC3_4 -> LocalPlus Bus CS6 \ + * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5] + * PSC3_6 -> dedicated SPI MOSI out (master case) + * PSC3_7 -> dedicated SPI MISO in (master case) + * PSC3_8 -> dedicated SPI SS out (master case) + * PSC3_9 -> dedicated SPI CLK out (master case) + * + * [18:19] = 01 + * USB_0 -> USB OE out + * USB_1 -> USB Tx- out + * USB_2 -> USB Tx+ out + * USB_3 -> USB RxD (in/out FIXME) + * USB_4 -> USB Rx+ in + * USB_5 -> USB Rx- in + * USB_6 -> USB PortPower out + * USB_7 -> USB speed out + * USB_8 -> USB suspend (in/out FIXME) + * USB_9 -> USB overcurrent in + * + * [17] = 0 + * USB differential mode + * + * [16] = 0 + * PCI enabled + * + * [12:15] = 0101 + * ETH_0 -> ETH Txen + * ETH_1 -> ETH TxD0 + * ETH_2 -> ETH TxD1 + * ETH_3 -> ETH TxD2 + * ETH_4 -> ETH TxD3 + * ETH_5 -> ETH Txerr + * ETH_6 -> ETH MDC + * ETH_7 -> ETH MDIO + * ETH_8 -> ETH RxDv + * ETH_9 -> ETH RxCLK + * ETH_10 -> ETH Collision + * ETH_11 -> ETH TxD + * ETH_12 -> ETH RxD0 + * ETH_13 -> ETH RxD1 + * ETH_14 -> ETH RxD2 + * ETH_15 -> ETH RxD3 + * ETH_16 -> ETH Rxerr + * ETH_17 -> ETH CRS + * + * [9:11] = 101 + * PSC6_0 -> UART RxD in + * PSC6_1 -> UART CTS (in/out FIXME) + * PSC6_2 -> UART TxD out + * PSC6_3 -> UART RTS (in/out FIXME) + * + * [2:3/6:7] = 00/11 + * TMR_0 -> ATA_CS0 out + * TMR_1 -> ATA_CS1 out + * TMR_2 -> GPIO + * TMR_3 -> GPIO + * TMR_4 -> GPIO + * TMR_5 -> GPIO + * TMR_6 -> GPIO + * TMR_7 -> GPIO + * I2C_0 -> I2C 1 Clock out + * I2C_1 -> I2C 1 IO in/out + * I2C_2 -> I2C 2 Clock out + * I2C_3 -> I2C 2 IO in/out + * + * [4] = 1 + * PSC3_5 is used as CS7 + * + * [5] = 1 + * PSC3_4 is used as CS6 + * + * [1] = 0 + * gpio_wkup_7 is GPIO + * + * [0] = 0 + * gpio_wkup_6 is GPIO + * + */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12 + +/*----------------------------------------------------------------------------- + Miscellaneous configurable options +-------------------------------------------------------------------------------*/ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_DISPLAY_BOARDINFO 1 + +/*----------------------------------------------------------------------------- + Various low-level settings +-----------------------------------------------------------------------------*/ +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE + +/* no burst access on the LPB */ +#define CONFIG_SYS_CS_BURST 0x00000000 +/* one deadcycle for the 33MHz statemachine */ +#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 +/* one additional waitstate for the 33MHz statemachine */ +#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00 +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE + +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*--------------------------------------------------------------------------- + IDE/ATA stuff Supports IDE harddisk +----------------------------------------------------------------------------*/ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ +#define CONFIG_IDE_PREINIT +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA +/* Offset for data I/O */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) +/* Offset for alternate registers */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 +#define CONFIG_ATAPI 1 + +/* we enable IDE and FAT support, so we also need partition support */ +#define CONFIG_DOS_PARTITION 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,5200@0" +#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN +#define OF_SOC "soc5200@f0000000" +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400" + +#endif /* __CONFIG_H */

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[U-Boot] [patch] rm9200 ethernet driver: board-specific quirk (csb337)
by David Brownell 10 Jul '09

10 Jul '09

CSB337 boards originally shipped with MicroMonitor, not U-Boot; and with a version using a different convention for recording Ethernet addresses than anyone else. To avoid breaking Linux when it uses U-Boot, have it use the same convention on that hardware. Signed-off-by: David Brownell <dbrownell(a)users.sourceforge.net> --- cpu/arm920t/at91rm9200/ether.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) --- a/cpu/arm920t/at91rm9200/ether.c +++ b/cpu/arm920t/at91rm9200/ether.c @@ -24,6 +24,7 @@ #include <at91rm9200_net.h> #include <net.h> #include <miiphy.h> +#include <asm/mach-types.h> /* ----- Ethernet Buffer definitions ----- */ @@ -184,7 +185,7 @@ int eth_init (bd_t * bd) p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ - /* Init Ehternet buffers */ + /* Init Ethernet buffers */ for (i = 0; i < RBF_FRAMEMAX; i++) { rbfdt[i].addr = (unsigned long)rbf_framebuf[i]; rbfdt[i].size = 0; @@ -193,9 +194,22 @@ int eth_init (bd_t * bd) rbfp = &rbfdt[0]; eth_getenv_enetaddr("ethaddr", enetaddr); - p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16) - | (enetaddr[1] << 8) | (enetaddr[0]); - p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]); + + /* The CSB337 originally used a version of the MicroMonitor bootloader + * which saved Ethernet addresses in the "wrong" order. Operating + * systems (like Linux) know this, and apply a workaround. Replicate + * that MicroMonitor behavior so we avoid needing to make such OS code + * care about which bootloader was used. + */ + if (machine_is_csb337()) { + p_mac->EMAC_SA2H = (enetaddr[0] << 8) | (enetaddr[1]); + p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16) + | (enetaddr[4] << 8) | (enetaddr[5]); + } else { + p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16) + | (enetaddr[1] << 8) | (enetaddr[0]); + p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]); + } p_mac->EMAC_RBQP = (long) (&rbfdt[0]); p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);

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