June 2009 - U-Boot

[U-Boot] From European Shell Grants
by EUROPEAN SHELL GRANTS 01 Jun '09

01 Jun '09

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[U-Boot] [PATCH] The omap3 L2 cache enable/disable function to omap3 dependent code
by Kim, Heung Jun 01 Jun '09

01 Jun '09

CC: Dirk Behme <dirk.behme(a)googlemail.com> Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> --- The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved to cpu/arm_cortexa8/omap3/cache.c. This patches fixes the First issue in the following http://lists.denx.de/pipermail/u-boot/2009-May/053433.html The Second issue is fixed by http://lists.denx.de/pipermail/u-boot/2009-May/053490.html cpu/arm_cortexa8/cpu.c | 68 +--------------------- cpu/arm_cortexa8/omap3/Makefile | 2 +- cpu/arm_cortexa8/omap3/board.c | 5 +- cpu/arm_cortexa8/omap3/cache.c | 99 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-omap3/sys_proto.h | 1 - include/asm-arm/cache.h | 37 ++++++++++++ 6 files changed, 143 insertions(+), 69 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache.c create mode 100644 include/asm-arm/cache.h diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 3e1780b..96f42a9 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -35,15 +35,12 @@ #include <command.h> #include <asm/arch/sys_proto.h> #include <asm/system.h> +#include <asm/cache.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -#ifndef CONFIG_L2_OFF -void l2cache_disable(void); -#endif - static void cache_flush(void); int cpu_init(void) @@ -80,7 +77,7 @@ int cleanup_before_linux(void) #ifndef CONFIG_L2_OFF /* turn off L2 cache */ - l2cache_disable(); + l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif @@ -89,71 +86,12 @@ int cleanup_before_linux(void) asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF - l2cache_enable(); + l2_cache_enable(); #endif return 0; } -void l2cache_enable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - -} - -void l2cache_disable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index b96b3dd..f83036b 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o -COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o +COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 51d5cf6..439ea6a 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -36,6 +36,7 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> +#include <asm/cache.h> extern omap3_sysinfo sysinfo; @@ -206,9 +207,9 @@ void s_init(void) #endif #ifdef CONFIG_L2_OFF - l2cache_disable(); + l2_cache_disable(); #else - l2cache_enable(); + l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c new file mode 100644 index 0000000..4b3e64a --- /dev/null +++ b/cpu/arm_cortexa8/omap3/cache.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2009 + * Samsung Electornics, HeungJun Kim <riverful.kim(a)samsung.com> + * + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * L2 cache specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/cache.h> + +void l2_cache_enable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void l2_cache_disable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } +} + diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 7361d08..9314c7c 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -50,7 +50,6 @@ u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); u32 get_device_type(void); -void l2cache_enable(void); void secureworld_exit(void); void setup_auxcr(void); void try_unlock_memory(void); diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h new file mode 100644 index 0000000..38ecd6b --- /dev/null +++ b/include/asm-arm/cache.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _L2_CACHE_H_ +#define _L2_CACHE_H_ + +void l2_cache_disable(); +void l2_cache_enable(); + +#endif + -- 1.5.6.3

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[U-Boot] unsubscribe
by Malenboim Vadim 01 Jun '09

01 Jun '09

Vadim Malenboim Mobile : +972 - 54 - 4925862 Office : +972 - 04 - 8315075 Fax : +972 - 04 - 8315657 Advanced Technology Center P.O.BOX 539 Haifa 31053 , Israel The information in this e-mail transmission contains proprietary and business sensitive information. Unauthorized interception of this e-mail may constitute a violation of law. If you are not the intended recipient, you are hereby notified that any review, dissemination, distribution or duplication of this communication is strictly prohibited. You are also asked to contact the sender by reply email and immediately destroy all copies of the original message.

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Re: [U-Boot] [U-BOot] new cpu(Ingenic), new board(PI)
by xiangfu 01 Jun '09

01 Jun '09

Hi Wolfgang Denk wrote: > > Dear xiangfu_gmail, > > > > In message <49E5A2ED.2060503(a)gmail.com> you wrote: >> >> there is a device name PI, >> >> the CPU is Ingenic 4740 [1], >> >> now we have the u-boot-1.1.6 patch.[2] >> >> >> >> I want the u-boot Integrate with 'upstream' >> >> what am I got do. >> >> just give some advice or step. > > > > Please see http://www.denx.de/wiki/U-Boot/CodingStyle and > > http://www.denx.de/wiki/U-Boot/Patches . > > > > We appreciate if you submit your patches following the above > > guidelines - but you got to spend a lot of work before being able to > > do that. U-Boot 1.1.6 is extremely old, so you must rebase your code > > first against current top of tree. > > Thanks Wolfgang. Sorry for so later to reply your email. those weeks I follow the CodingStyle, and also merge ingenic u-boot to V2009.06. for now it can not boot the kernel. but it's boot the device and output something from the serial console. there is two branch in my git[2]. [xiangfu] this one , I try to merge with the upstream. [u-boot] is the upstream. I use "git diff u-boot..xiangfu > ~/pi_project.patch" to generate the patch[1]. what am I got do next? thanks. [1] http://www.openmobilefree.net/other/xiangfu/file/pi_project.patch [2] http://github.com/xiangfu/pi-u-boot/tree/xiangfu

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[U-Boot] [PATCH] omap3 L2-cache enable/disable function to omap3 dependent code
by Kim, Heung Jun 01 Jun '09

01 Jun '09

Dear Jean, I miss mail title sorry. :) ============= Dear Jean, I made new patch about L2 cane enable/disable function. The related thread is here. http://www.mail-archive.com/u-boot@lists.denx.de/msg14744.html I fixed title issue & apart header. Thanks to read :) Best Regards, riverful ===== omap3 L2 cache enable/disable function moved from cpu/arm_cortexa8/cpu.c to cpu/arm_cortexa8/omap3/. for generic SoC supports. Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> --- cpu/arm_cortexa8/cpu.c | 68 +--------------------- cpu/arm_cortexa8/omap3/Makefile | 2 +- cpu/arm_cortexa8/omap3/board.c | 5 +- cpu/arm_cortexa8/omap3/cache.c | 99 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-omap3/sys_proto.h | 1 - include/asm-arm/cache.h | 37 ++++++++++++ 6 files changed, 143 insertions(+), 69 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache.c create mode 100644 include/asm-arm/cache.h diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 3e1780b..96f42a9 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -35,15 +35,12 @@ #include <command.h> #include <asm/arch/sys_proto.h> #include <asm/system.h> +#include <asm/cache.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -#ifndef CONFIG_L2_OFF -void l2cache_disable(void); -#endif - static void cache_flush(void); int cpu_init(void) @@ -80,7 +77,7 @@ int cleanup_before_linux(void) #ifndef CONFIG_L2_OFF /* turn off L2 cache */ - l2cache_disable(); + l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif @@ -89,71 +86,12 @@ int cleanup_before_linux(void) asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF - l2cache_enable(); + l2_cache_enable(); #endif return 0; } -void l2cache_enable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - -} - -void l2cache_disable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index b96b3dd..f83036b 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o -COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o +COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 51d5cf6..439ea6a 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -36,6 +36,7 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> +#include <asm/cache.h> extern omap3_sysinfo sysinfo; @@ -206,9 +207,9 @@ void s_init(void) #endif #ifdef CONFIG_L2_OFF - l2cache_disable(); + l2_cache_disable(); #else - l2cache_enable(); + l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c new file mode 100644 index 0000000..4b3e64a --- /dev/null +++ b/cpu/arm_cortexa8/omap3/cache.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2009 + * Samsung Electornics, HeungJun Kim <riverful.kim(a)samsung.com> + * + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * L2 cache specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/cache.h> + +void l2_cache_enable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void l2_cache_disable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } +} + diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 7361d08..9314c7c 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -50,7 +50,6 @@ u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); u32 get_device_type(void); -void l2cache_enable(void); void secureworld_exit(void); void setup_auxcr(void); void try_unlock_memory(void); diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h new file mode 100644 index 0000000..38ecd6b --- /dev/null +++ b/include/asm-arm/cache.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _L2_CACHE_H_ +#define _L2_CACHE_H_ + +void l2_cache_disable(); +void l2_cache_enable(); + +#endif + -- 1.5.6.3 ===== =============

2 1

[U-Boot] [PATCH]
by Kim, Heung Jun 01 Jun '09

01 Jun '09

Dear Jean, I made new patch about L2 cane enable/disable function. The related thread is here. http://www.mail-archive.com/u-boot@lists.denx.de/msg14744.html I fixed title issue & apart header. Thanks to read :) Best Regards, riverful ===== omap3 L2 cache enable/disable function moved from cpu/arm_cortexa8/cpu.c to cpu/arm_cortexa8/omap3/. for generic SoC supports. Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> --- cpu/arm_cortexa8/cpu.c | 68 +--------------------- cpu/arm_cortexa8/omap3/Makefile | 2 +- cpu/arm_cortexa8/omap3/board.c | 5 +- cpu/arm_cortexa8/omap3/cache.c | 99 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-omap3/sys_proto.h | 1 - include/asm-arm/cache.h | 37 ++++++++++++ 6 files changed, 143 insertions(+), 69 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache.c create mode 100644 include/asm-arm/cache.h diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 3e1780b..96f42a9 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -35,15 +35,12 @@ #include <command.h> #include <asm/arch/sys_proto.h> #include <asm/system.h> +#include <asm/cache.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -#ifndef CONFIG_L2_OFF -void l2cache_disable(void); -#endif - static void cache_flush(void); int cpu_init(void) @@ -80,7 +77,7 @@ int cleanup_before_linux(void) #ifndef CONFIG_L2_OFF /* turn off L2 cache */ - l2cache_disable(); + l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif @@ -89,71 +86,12 @@ int cleanup_before_linux(void) asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF - l2cache_enable(); + l2_cache_enable(); #endif return 0; } -void l2cache_enable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - -} - -void l2cache_disable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index b96b3dd..f83036b 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o -COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o +COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 51d5cf6..439ea6a 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -36,6 +36,7 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> +#include <asm/cache.h> extern omap3_sysinfo sysinfo; @@ -206,9 +207,9 @@ void s_init(void) #endif #ifdef CONFIG_L2_OFF - l2cache_disable(); + l2_cache_disable(); #else - l2cache_enable(); + l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c new file mode 100644 index 0000000..4b3e64a --- /dev/null +++ b/cpu/arm_cortexa8/omap3/cache.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2009 + * Samsung Electornics, HeungJun Kim <riverful.kim(a)samsung.com> + * + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * L2 cache specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/cache.h> + +void l2_cache_enable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void l2_cache_disable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } +} + diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 7361d08..9314c7c 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -50,7 +50,6 @@ u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); u32 get_device_type(void); -void l2cache_enable(void); void secureworld_exit(void); void setup_auxcr(void); void try_unlock_memory(void); diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h new file mode 100644 index 0000000..38ecd6b --- /dev/null +++ b/include/asm-arm/cache.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _L2_CACHE_H_ +#define _L2_CACHE_H_ + +void l2_cache_disable(); +void l2_cache_enable(); + +#endif + -- 1.5.6.3 =====

2 1

[U-Boot] [PATCH] ppc4xx/net: Fix MDIO clock setup
by Felix Radensky 01 Jun '09

01 Jun '09

This patch fixes MDIO clock setup in case when OPB frequency is 100MHz. Current code assumes that the value of sysinfo.freqOPB is 100000000 when OPB frequency is 100MHz. In reality it is 100000001. As a result MDIO clock is set to incorrect value, larger than 2.5MHz, thus violating the standard. This in not a problem on boards equipped with Marvell PHYs (e.g. Canyonlands), since those PHYs support MDIO clocks up to 8.3MHz, but can be a problem for other PHYs (e.g. Realtek ones). Signed-off-by: Felix Radensky <felix(a)embedded-sol.com> --- drivers/net/4xx_enet.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 918373b..7bf3e0a 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -871,6 +871,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) + u32 opbfreq; sys_info_t sysinfo; #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -997,12 +998,13 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; - if (sysinfo.freqOPB <= 50000000); - else if (sysinfo.freqOPB <= 66666667) + opbfreq = sysinfo.freqOPB / 1000000; + if (opbfreq <= 50); + else if (opbfreq <= 66) mode_reg |= EMAC_M1_OBCI_66; - else if (sysinfo.freqOPB <= 83333333) + else if (opbfreq <= 83) mode_reg |= EMAC_M1_OBCI_83; - else if (sysinfo.freqOPB <= 100000000) + else if (opbfreq <= 100) mode_reg |= EMAC_M1_OBCI_100; else mode_reg |= EMAC_M1_OBCI_GT100; -- 1.5.4.3

2 1

[U-Boot] [PATCH v3 1/3][Net][ARM] Moved Davinci Ethernet driver to drivers/net
by Ben Warren 01 Jun '09

01 Jun '09

This driver has been renamed davinci_emac.c Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- Change in V3: Renamed driver to davinci_emac cpu/arm926ejs/davinci/Makefile | 2 +- drivers/net/Makefile | 1 + .../davinci/ether.c => drivers/net/davinci_emac.c | 0 3 files changed, 2 insertions(+), 1 deletions(-) rename cpu/arm926ejs/davinci/ether.c => drivers/net/davinci_emac.c (100%) diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 6eaa89c..e45ad25 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).a COBJS-y += cpu.o timer.o psc.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o -COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o +COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o SOBJS = reset.o diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..26f1ea6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -64,6 +64,7 @@ COBJS-$(CONFIG_SH_ETHER) += sh_eth.o COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o +COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o COBJS-$(CONFIG_TSEC_ENET) += tsec.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o diff --git a/cpu/arm926ejs/davinci/ether.c b/drivers/net/davinci_emac.c similarity index 100% rename from cpu/arm926ejs/davinci/ether.c rename to drivers/net/davinci_emac.c -- 1.5.6.3

1 2

[U-Boot] [RFC PATCH 1/2] sh: make lds more generic
by Jean-Christophe PLAGNIOL-VILLARD 01 Jun '09

01 Jun '09

currently the sh lds need to sync the lds enty and TEXT_BASE manualy and the reloc_dst is based on it instead provide it now from the ldflags tested on r2dplus Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- board/mpr2/u-boot.lds | 13 +++---------- board/ms7720se/u-boot.lds | 15 +++------------ board/ms7722se/u-boot.lds | 15 +++------------ board/ms7750se/u-boot.lds | 15 +++------------ board/renesas/MigoR/u-boot.lds | 15 +++------------ board/renesas/ap325rxa/u-boot.lds | 15 +++------------ board/renesas/r2dplus/u-boot.lds | 15 +++------------ board/renesas/r7780mp/u-boot.lds | 15 +++------------ board/renesas/rsk7203/u-boot.lds | 10 ++-------- board/renesas/sh7763rdp/u-boot.lds | 15 +++------------ board/renesas/sh7785lcr/u-boot.lds | 7 ++++--- sh_config.mk | 1 + 12 files changed, 34 insertions(+), 117 deletions(-) diff --git a/board/mpr2/u-boot.lds b/board/mpr2/u-boot.lds index deae344..4180522 100644 --- a/board/mpr2/u-boot.lds +++ b/board/mpr2/u-boot.lds @@ -34,16 +34,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x8C000000. - U-Boot resides in the last 256 kB of the 64 MB. - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/ms7720se/u-boot.lds b/board/ms7720se/u-boot.lds index 1f9b792..7aaaaf8 100644 --- a/board/ms7720se/u-boot.lds +++ b/board/ms7720se/u-boot.lds @@ -31,18 +31,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/ms7722se/u-boot.lds b/board/ms7722se/u-boot.lds index 7b0fb67..db3741c 100644 --- a/board/ms7722se/u-boot.lds +++ b/board/ms7722se/u-boot.lds @@ -28,18 +28,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/ms7750se/u-boot.lds b/board/ms7750se/u-boot.lds index 7b0fb67..db3741c 100644 --- a/board/ms7750se/u-boot.lds +++ b/board/ms7750se/u-boot.lds @@ -28,18 +28,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/renesas/MigoR/u-boot.lds b/board/renesas/MigoR/u-boot.lds index c004b83..9b83cad 100644 --- a/board/renesas/MigoR/u-boot.lds +++ b/board/renesas/MigoR/u-boot.lds @@ -28,18 +28,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/renesas/ap325rxa/u-boot.lds b/board/renesas/ap325rxa/u-boot.lds index 94bacca..9b83cad 100644 --- a/board/renesas/ap325rxa/u-boot.lds +++ b/board/renesas/ap325rxa/u-boot.lds @@ -28,18 +28,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x88000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x88000000 + (128*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/renesas/r2dplus/u-boot.lds b/board/renesas/r2dplus/u-boot.lds index e1c15b0..93a7d31 100644 --- a/board/renesas/r2dplus/u-boot.lds +++ b/board/renesas/r2dplus/u-boot.lds @@ -28,18 +28,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x0C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/renesas/r7780mp/u-boot.lds b/board/renesas/r7780mp/u-boot.lds index f32d0b8..93a7d31 100644 --- a/board/renesas/r7780mp/u-boot.lds +++ b/board/renesas/r7780mp/u-boot.lds @@ -28,18 +28,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x08000000 + (128*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/renesas/rsk7203/u-boot.lds b/board/renesas/rsk7203/u-boot.lds index bd4a550..7f3cfbd 100644 --- a/board/renesas/rsk7203/u-boot.lds +++ b/board/renesas/rsk7203/u-boot.lds @@ -28,15 +28,9 @@ ENTRY(_start) SECTIONS { /* - * Base address of internal SDRAM is 0x0C000000. - * - * NOTE: This address must match with the definition of - *TEXT_BASE in config.mk (in this directory). + * entry and reloct_dst will be provide by command line */ - - . = 0x0C000000 + (8*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/renesas/sh7763rdp/u-boot.lds b/board/renesas/sh7763rdp/u-boot.lds index b1a967d..93a7d31 100644 --- a/board/renesas/sh7763rdp/u-boot.lds +++ b/board/renesas/sh7763rdp/u-boot.lds @@ -28,18 +28,9 @@ ENTRY(_start) SECTIONS { /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/board/renesas/sh7785lcr/u-boot.lds b/board/renesas/sh7785lcr/u-boot.lds index 255ab37..777ab92 100644 --- a/board/renesas/sh7785lcr/u-boot.lds +++ b/board/renesas/sh7785lcr/u-boot.lds @@ -28,9 +28,10 @@ ENTRY(_start) SECTIONS { - . = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024); - - PROVIDE (reloc_dst = .); + /* + * entry and reloct_dst will be provide by command line + */ + . = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); diff --git a/sh_config.mk b/sh_config.mk index 49d50f7..c19db53 100644 --- a/sh_config.mk +++ b/sh_config.mk @@ -22,3 +22,4 @@ # PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ +PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE) -- 1.6.1.3

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