June 2009 - U-Boot

[U-Boot] [PATCH] 85xx: Fix the clock adjust of mpc8569mds board
by Dave Liu 02 Jun '09

02 Jun '09

Currently the clk_adj is 6 (3/4 cycle), The settings will cause the DDR controller hang at the data init. Change the clk_adj from 6 to 4 (1/2 cycle), make the memory system stable. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- board/freescale/mpc8569mds/ddr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index c4e63fb..da1e675 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -56,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, * 0110 3/4 cycle late * 0111 7/8 cycle late */ - popts->clk_adjust = 6; + popts->clk_adjust = 4; /* * Factors to consider for CPO: -- 1.5.4

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[U-Boot] JFFS2 + cache coherency
by Renaud barbier 02 Jun '09

02 Jun '09

My system is based on MPc8544. I am loading a small standalone program (2KB) from the JFFS2 partition (NOR flash) My program crashes while it does not crash if loaded from a tftp server. After investifgation using Codewarrior I noticed that there is a difference between the memory and Dcache content. Some number of words (8 = cache line)) are all zero in Dcache. Hence when jumping the program crashes as I guess the instruction cache is picking the instructions from the Dcache. When the program is loaded from a tftp server both the cache (in copyback mode) and DDR are set with the same data and therefore the program works. When loaded from a JFFS2 partition, the data are loaded to inode buffer (flash to memory with cache inhibited) in memory and then (mem)copied to the destination address (memory to memory). (Hope I got this right). This is why the cache/memory is not in sync. The problem does not exist when the cache is write-through. Also the Freescale documentation on cache cohenrency specifies that software should make sure that the cache/memory are synchronized before jumping to a new location. Hence, I think the cache should be flushed in or after do_jffs2_fsload. A call to flush_dcache(); fixes the problem. Let me know if you think I am right regarding this issue. cheers, Renaud

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[U-Boot] [patch] Add display cpuinfo for Atmel at91sam9261 Cores
by Remy Bohmer 02 Jun '09

02 Jun '09

This patch adds support for displaying CPU type information about Atmel AT91 cores during boot. It currently only configures it for the at91sam9261ek board, but it can easily be configured for all at91 based cores. This patch also provides at91_dbgu.h which is also used by the upcoming USB CDC-ethernet and USB-gadget support for this board. Signed-off-by: Remy Böhmer <linux(a)bohmer.net> --- cpu/arm926ejs/at91/Makefile | 1 cpu/arm926ejs/at91/cpuinfo.c | 83 ++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_dbgu.h | 69 +++++++++++++++++++++++ include/asm-arm/arch-at91/cpu.h | 99 ++++++++++++++++++++++++++++++++++ include/configs/at91sam9261ek.h | 2 5 files changed, 254 insertions(+) create mode 100644 cpu/arm926ejs/at91/cpuinfo.c create mode 100644 include/asm-arm/arch-at91/at91_dbgu.h create mode 100644 include/asm-arm/arch-at91/cpu.h Index: u-boot-usb.tmp/cpu/arm926ejs/at91/Makefile =================================================================== --- u-boot-usb.tmp.orig/cpu/arm926ejs/at91/Makefile 2009-05-02 21:43:41.000000000 +0200 +++ u-boot-usb.tmp/cpu/arm926ejs/at91/Makefile 2009-05-02 22:01:46.000000000 +0200 @@ -55,6 +55,7 @@ COBJS-y += at91sam9rl_serial.o COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9rl_spi.o endif COBJS-$(CONFIG_AT91_LED) += led.o +COBJS-$(CONFIG_DISPLAY_CPUINFO) +=cpuinfo.o COBJS-y += clock.o COBJS-y += cpu.o COBJS-y += timer.o Index: u-boot-usb.tmp/cpu/arm926ejs/at91/cpuinfo.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-usb.tmp/cpu/arm926ejs/at91/cpuinfo.c 2009-05-02 22:01:46.000000000 +0200 @@ -0,0 +1,83 @@ +#include <command.h> +#include <common.h> +#include <arm926ejs.h> +#include <asm/hardware.h> +#include <asm/arch/at91_dbgu.h> +#include <asm/arch/io.h> + +int print_cpuinfo(void) +{ + unsigned long cidr; + const char *txt; + + cidr = at91_sys_read(AT91_DBGU_CIDR); + + switch ((cidr & AT91_CIDR_EPROC) >> 5) { + case 0x1: txt = "ARM946ES"; break; + case 0x2: txt = "ARM7TDMI"; break; + case 0x4: txt = "ARM920T"; break; + case 0x5: txt = "ARM926EJS"; break; + default: txt = "undefined"; break; + } + printf("Embedded Processor: %s\n", txt); + + switch ((cidr & AT91_CIDR_ARCH) >> 20) { + case 0x19: txt = "AT91SAM9xx"; break; + case 0x29: txt = "AT91SAM9XExx"; break; + case 0x34: txt = "AT91x34"; break; + case 0x37: txt = "CAP7"; break; + case 0x39: txt = "CAP9"; break; + case 0x3B: txt = "CAP11"; break; + case 0x40: txt = "AT91x40"; break; + case 0x42: txt = "AT91x42"; break; + case 0x55: txt = "AT91x55"; break; + case 0x60: txt = "AT91SAM7Axx"; break; + case 0x61: txt = "AT91SAM7AQxx"; break; + case 0x63: txt = "AT91x63"; break; + case 0x70: txt = "AT91SAM7Sxx"; break; + case 0x71: txt = "AT91SAM7XCxx"; break; + case 0x72: txt = "AT91SAM7SExx"; break; + case 0x73: txt = "AT91SAM7Lxx"; break; + case 0x75: txt = "AT91SAM7Xxx"; break; + case 0x92: txt = "AT91x92"; break; + case 0xF0: txt = "AT75Cxx"; break; + default: txt = "undefined"; break; + } + printf("Architecture: %s Series\n", txt); + + printf("CPU-revision: %c\n", (char)('A' + (cidr & AT91_CIDR_VERSION))); + + switch ((cidr & AT91_CIDR_NVPTYP) >> 28) { + case 0x0: txt = "ROM"; break; + case 0x1: txt = "ROMless or onchip flash"; break; + case 0x2: txt = "Embedded flash memory"; break; + case 0x3: txt = "ROM and Embedded flash memory"; break; + case 0x4: txt = "SRAM emulating ROM"; break; + default: txt = "undefined"; break; + } + printf("NonVolatile Program Memory type: %s\n", txt); + + switch (cidr & AT91_CIDR_SRAMSIZ) { + case AT91_CIDR_SRAMSIZ_1K: txt = "1K"; break; + case AT91_CIDR_SRAMSIZ_2K: txt = "2K"; break; + case AT91_CIDR_SRAMSIZ_112K: txt = "112K"; break; + case AT91_CIDR_SRAMSIZ_4K: txt = "4K"; break; + case AT91_CIDR_SRAMSIZ_80K: txt = "80K"; break; + case AT91_CIDR_SRAMSIZ_160K: txt = "160K"; break; + case AT91_CIDR_SRAMSIZ_8K: txt = "8K"; break; + case AT91_CIDR_SRAMSIZ_16K: txt = "16K"; break; + case AT91_CIDR_SRAMSIZ_32K: txt = "32K"; break; + case AT91_CIDR_SRAMSIZ_64K: txt = "64K"; break; + case AT91_CIDR_SRAMSIZ_128K: txt = "128K"; break; + case AT91_CIDR_SRAMSIZ_256K: txt = "256K"; break; + case AT91_CIDR_SRAMSIZ_96K: txt = "96K"; break; + case AT91_CIDR_SRAMSIZ_512K: txt = "512K"; break; + default: txt = "undefined"; break; + } + printf("Internal SRAM size: %s\n", txt); + + if (cidr & AT91_CIDR_EXT) + printf("Extension ID: 0x%x\n", at91_sys_read(AT91_DBGU_EXID)); + + return 0; +} Index: u-boot-usb.tmp/include/asm-arm/arch-at91/at91_dbgu.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-usb.tmp/include/asm-arm/arch-at91/at91_dbgu.h 2009-05-02 22:01:46.000000000 +0200 @@ -0,0 +1,69 @@ +/* + * include/asm-arm/arch-at91/at91_dbgu.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Debug Unit (DBGU) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_DBGU_H +#define AT91_DBGU_H + +#ifdef AT91_DBGU +#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ +#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ +#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable */ +#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ +#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ +#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable */ +#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask */ +#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ +#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding */ +#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding */ +#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator */ + +#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ +#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension */ +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif /* AT91_DBGU */ + +/* + * Some AT91 parts that don't have full DEBUG units still support the ID + * and extensions register. + */ +#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ +#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ +#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program + Memory Size */ +#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile + Program Memory Size */ +#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ +#define AT91_CIDR_SRAMSIZ_1K (1 << 16) +#define AT91_CIDR_SRAMSIZ_2K (2 << 16) +#define AT91_CIDR_SRAMSIZ_112K (4 << 16) +#define AT91_CIDR_SRAMSIZ_4K (5 << 16) +#define AT91_CIDR_SRAMSIZ_80K (6 << 16) +#define AT91_CIDR_SRAMSIZ_160K (7 << 16) +#define AT91_CIDR_SRAMSIZ_8K (8 << 16) +#define AT91_CIDR_SRAMSIZ_16K (9 << 16) +#define AT91_CIDR_SRAMSIZ_32K (10 << 16) +#define AT91_CIDR_SRAMSIZ_64K (11 << 16) +#define AT91_CIDR_SRAMSIZ_128K (12 << 16) +#define AT91_CIDR_SRAMSIZ_256K (13 << 16) +#define AT91_CIDR_SRAMSIZ_96K (14 << 16) +#define AT91_CIDR_SRAMSIZ_512K (15 << 16) +#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Id */ +#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program + Memory Type */ +#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ + +#endif Index: u-boot-usb.tmp/include/asm-arm/arch-at91/cpu.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-usb.tmp/include/asm-arm/arch-at91/cpu.h 2009-05-02 22:01:46.000000000 +0200 @@ -0,0 +1,99 @@ +/* + * include/asm-arm/arch-at91/cpu.h + * + * Copyright (C) 2006 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_CPU_H +#define __ASM_ARCH_CPU_H + +#include <asm/hardware.h> +#include <asm/arch/at91_dbgu.h> +#include <asm/arch/io.h> + + +#define ARCH_ID_AT91RM9200 0x09290780 +#define ARCH_ID_AT91SAM9260 0x019803a0 +#define ARCH_ID_AT91SAM9261 0x019703a0 +#define ARCH_ID_AT91SAM9263 0x019607a0 +#define ARCH_ID_AT91SAM9RL64 0x019b03a0 +#define ARCH_ID_AT91CAP9 0x039A03A0 + +#define ARCH_ID_AT91SAM9XE128 0x329973a0 +#define ARCH_ID_AT91SAM9XE256 0x329a93a0 +#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 + +#define ARCH_ID_AT91M40800 0x14080044 +#define ARCH_ID_AT91R40807 0x44080746 +#define ARCH_ID_AT91M40807 0x14080745 +#define ARCH_ID_AT91R40008 0x44000840 + +static inline unsigned long at91_cpu_identify(void) +{ + return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); +} + + +#define ARCH_FAMILY_AT91X92 0x09200000 +#define ARCH_FAMILY_AT91SAM9 0x01900000 +#define ARCH_FAMILY_AT91SAM9XE 0x02900000 + +static inline unsigned long at91_arch_identify(void) +{ + return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); +} + + +#ifdef CONFIG_AT91RM9200 +/* no actual detection for this architecture */ +#define cpu_is_at91rm9200() (1) +#else +#define cpu_is_at91rm9200() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) +#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) \ + || cpu_is_at91sam9xe()) +#else +#define cpu_is_at91sam9xe() (0) +#define cpu_is_at91sam9260() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) +#else +#define cpu_is_at91sam9261() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) +#else +#define cpu_is_at91sam9263() (0) +#endif + +#ifdef CONFIG_AT91SAM9RL +#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#else +#define cpu_is_at91sam9rl() (0) +#endif + +#ifdef CONFIG_AT91CAP9 +#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) +#else +#define cpu_is_at91cap9() (0) +#endif + +/* + * Since this is ARM, we will never run on any AVR32 CPU. But these + * definitions may reduce clutter in common drivers. + */ +#define cpu_is_at32ap7000() (0) + +#endif Index: u-boot-usb.tmp/include/configs/at91sam9261ek.h =================================================================== --- u-boot-usb.tmp.orig/include/configs/at91sam9261ek.h 2009-05-02 21:48:36.000000000 +0200 +++ u-boot-usb.tmp/include/configs/at91sam9261ek.h 2009-05-02 22:01:46.000000000 +0200 @@ -45,6 +45,8 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_DISPLAY_CPUINFO 1 + /* * Hardware drivers */ --

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[U-Boot] [PATCH v2 3/6] mpc83xx: USB: Reorganized its support
by Vivek Mahajan 02 Jun '09

02 Jun '09

The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan(a)freescale.com> --- v2 change: Moved usb_phy_type to CONFIG_EXTRA_ENV_SETTINGS in board specific config file(s). cpu/mpc83xx/cpu_init.c | 19 ++++++++++++- drivers/usb/host/ehci-fsl.c | 53 ++++++++++++----------------------- include/asm-ppc/immap_83xx.h | 5 ++- include/usb/ehci-fsl.h | 63 +++++++++++++++++++++++++++++++++++++++++- 4 files changed, 102 insertions(+), 38 deletions(-) diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 8e9c875..7224c27 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,6 +23,10 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> +#ifdef CONFIG_USB_EHCI_FSL +#include <asm/io.h> +#include <usb/ehci-fsl.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -294,6 +298,19 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif +#ifdef CONFIG_USB_EHCI_FSL + uint32_t temp; + struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR; + + /* Configure interface. */ + setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); + + /* Wait for clock to stabilize */ + do { + temp = in_be32((void *)ehci->control); + udelay(1000); + } while (!(temp & PHY_CLK_VALID)); +#endif } int cpu_init_r (void) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 39ef435..bf148c4 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -1,4 +1,6 @@ /* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB * * Author: Tor Krill tor(a)excito.com @@ -22,12 +24,10 @@ #include <common.h> #include <pci.h> #include <usb.h> -#include <mpc83xx.h> #include <asm/io.h> -#include <asm/bitops.h> +#include <usb/ehci-fsl.h> #include "ehci.h" -#include <usb/ehci-fsl.h> #include "ehci-core.h" /* @@ -38,50 +38,33 @@ */ int ehci_hcd_init(void) { - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - uint32_t addr, temp; + struct usb_ehci *ehci; - addr = (uint32_t)&(im->usb[0]); - hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI); + ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR; + hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - /* Configure clock */ - clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK, - MPC83XX_SCCR_USB_DRCM_11); - - /* Confgure interface. */ - temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); - out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp - | REFSEL_16MHZ | UTMI_PHY_EN); - - /* Wait for clock to stabilize */ - do { - temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); - udelay(1000); - } while (!(temp & PHY_CLK_VALID)); - /* Set to Host mode */ - temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE)); - out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST); + setbits_le32((void *)ehci->usbmode, CM_HOST); - out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB); - out_be32((void *)(addr + FSL_SOC_USB_SNOOP2), - 0x80000000 | SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ - /* TODO: handle different phys? */ - out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + if (!strcmp(getenv("usb_phy_type"), "utmi")) + out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + else + out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); /* Enable interface. */ - temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); - out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN); + setbits_be32((void *)ehci->control, USB_EN); - out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c); - out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040); - out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001); + out_be32((void *)ehci->prictrl, 0x0000000c); + out_be32((void *)ehci->age_cnt_limit, 0x00000040); + out_be32((void *)ehci->sictrl, 0x00000001); - temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE)); + in_le32((void *)ehci->usbmode); return 0; } diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 7b847f8..df46489 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2009 Freescale Semiconductor, Inc. * * MPC83xx Internal Memory Map * @@ -897,4 +897,7 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) #define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 +#define CONFIG_SYS_MPC83xx_USB_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index c429af1..7ae948c 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2005 freescale semiconductor + * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc * Copyright (c) 2005 MontaVista Software * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB * @@ -22,6 +22,8 @@ #ifndef _EHCI_FSL_H #define _EHCI_FSL_H +#include <asm/processor.h> + /* Global offsets */ #define FSL_SKIP_PCI 0x100 @@ -83,4 +85,63 @@ #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 +#if defined(CONFIG_MPC83XX) +#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR +#endif + +/* + * USB Registers + */ +struct usb_ehci { + u8 res1[0x100]; + u16 caplength; /* 0x100 - Capability Register Length */ + u16 hciversion; /* 0x102 - Host Interface Version */ + u32 hcsparams; /* 0x104 - Host Structural Parameters */ + u32 hccparams; /* 0x108 - Host Capability Parameters */ + u8 res2[0x14]; + u32 dciversion; /* 0x120 - Device Interface Version */ + u32 dciparams; /* 0x124 - Device Controller Params */ + u8 res3[0x18]; + u32 usbcmd; /* 0x140 - USB Command */ + u32 usbsts; /* 0x144 - USB Status */ + u32 usbintr; /* 0x148 - USB Interrupt Enable */ + u32 frindex; /* 0x14C - USB Frame Index */ + u8 res4[0x4]; + u32 perlistbase; /* 0x154 - Periodic List Base + - USB Device Address */ + u32 ep_list_addr; /* 0x158 - Next Asynchronous List + - End Point Address */ + u8 res5[0x4]; + u32 burstsize; /* 0x160 - Programmable Burst Size */ + u32 txfilltuning; /* 0x164 - Host TT Transmit + pre-buffer packet tuning */ + u8 res6[0x8]; + u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ + u8 res7[0xc]; + u32 config_flag; /* 0x180 - Configured Flag Register */ + u32 portsc; /* 0x184 - Port status/control */ + u8 res8[0x20]; + u32 usbmode; /* 0x1a8 - USB Device Mode */ + u32 epsetupstat; /* 0x1ac - End Point Setup Status */ + u32 epprime; /* 0x1b0 - End Point Init Status */ + u32 epflush; /* 0x1b4 - End Point De-initlialize */ + u32 epstatus; /* 0x1b8 - End Point Status */ + u32 epcomplete; /* 0x1bc - End Point Complete */ + u32 epctrl0; /* 0x1c0 - End Point Control 0 */ + u32 epctrl1; /* 0x1c4 - End Point Control 1 */ + u32 epctrl2; /* 0x1c8 - End Point Control 2 */ + u32 epctrl3; /* 0x1cc - End Point Control 3 */ + u32 epctrl4; /* 0x1d0 - End Point Control 4 */ + u32 epctrl5; /* 0x1d4 - End Point Control 5 */ + u8 res9[0x228]; + u32 snoop1; /* 0x400 - Snoop 1 */ + u32 snoop2; /* 0x404 - Snoop 2 */ + u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ + u32 prictrl; /* 0x40c - Priority Control */ + u32 sictrl; /* 0x410 - System Interface Control */ + u8 res10[0xEC]; + u32 control; /* 0x500 - Control */ + u8 res11[0xafc]; +}; + #endif /* _EHCI_FSL_H */ -- 1.5.6.5

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[U-Boot] Kconfig menu layout
by Kumar Gala 02 Jun '09

02 Jun '09

In chatting w/Wolfgang on IRC he felt that we should maintain the highlevel picking a board implies ARCH and other settings. However this seems like a lot of boards in one list.. To get a rough order of magnitude MAKEALL is ~880 lines. How can we reduce this to make it a bit more manageable? - k

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[U-Boot] Spanish888. Com Official Winnings Notifications
by Spanish888. Com Official Winnings Notifications 02 Jun '09

02 Jun '09

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Re: [U-Boot] JFFS2 with NAND flash is very SLOW ...
by Stefan Roese 02 Jun '09

02 Jun '09

On Tuesday 02 June 2009 15:56:25 Pierre Savary wrote: > In fact it is not better with this config: > #define CONFIG_ICACHE_ON > #define CONFIG_DCACHE_ON > #define CONFIG_SYS_DCACHE_SIZE 32768 > #define CONFIG_SYS_ICACHE_SIZE 32768 > #define CONFIG_SYS_CACHELINE_SIZE 32 > > My architecture is arm926ejs and it seems that CACHE management is not > implemented... > > I just measure a load of uImage (2MB) ... it takes more than 2 minutes :-( Yes, this is really slow. Jean-Christophe will be able to tell us if caches are supported on this platform in U-Boot. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot] [PATCH] ARM Cortex A8: Move OMAP3 specific reset handler to OMAP3 code
by Dirk Behme 02 Jun '09

02 Jun '09

Reset is SoC specific and not ARM Cortex A8 generic. Move it from generic code to OMAP3 SoC specific file. CC: "Kim, Heung Jun" <riverful(a)gmail.com> Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- This patches fixes the second issue found by riverful in http://lists.denx.de/pipermail/u-boot/2009-May/053433.html The first issue is fixed by http://lists.denx.de/pipermail/u-boot/2009-May/053444.html cpu/arm_cortexa8/omap3/lowlevel_init.S | 12 ++++++++++++ cpu/arm_cortexa8/start.S | 14 -------------- 2 files changed, 12 insertions(+), 14 deletions(-) Index: u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/lowlevel_init.S +++ u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S @@ -181,6 +181,18 @@ lowlevel_init: /* back to arch calling code */ mov pc, lr +.global reset_cpu +reset_cpu: + ldr r1, rstctl @ get addr for global reset + @ reg + mov r3, #0x2 @ full reset pll + mpu + str r3, [r1] @ force reset + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PRM_RSTCTRL + /* the literal pools origin */ .ltorg Index: u-boot-arm/cpu/arm_cortexa8/start.S =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/start.S +++ u-boot-arm/cpu/arm_cortexa8/start.S @@ -500,17 +500,3 @@ finished_inval: @ but we compile with armv5 ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} - - - .align 5 -.global reset_cpu -reset_cpu: - ldr r1, rstctl @ get addr for global reset - @ reg - mov r3, #0x2 @ full reset pll + mpu - str r3, [r1] @ force reset - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PRM_RSTCTRL

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[U-Boot] I wonder "---" in the patch file generated by the git-format-patch
by Kim, Heung Jun 02 Jun '09

02 Jun '09

Dear Wolfgang Denk, I have a question about git-format-patch usage. I generated the patch using git-format-patch. The my usage is the following : 1. pull latest git repo. 2. change the code 3. # git commit -a -s 4. insert commit & any other things. 5. # git-format-patch -1 So, I get patch. But, this patch's form is different with you said. First of all, the all comments is on the "---". But, you said all comments must belong below the "---" like this messages. : http://lists.denx.de/pipermail/u-boot/2009-June/053535.html It's different. What did I lose anything during the patching progress?? Can you tell me what is wrong?? Thanks to read. Best Regards, riverful

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Re: [U-Boot] JFFS2 with NAND flash is very SLOW ...
by Stefan Roese 02 Jun '09

02 Jun '09

On Tuesday 02 June 2009 15:23:57 Pierre Savary wrote: > Is it better to use or not D-cache and I-cache? Depends a bit on the "application". From my experience I-Cache is most important. But for memory intensive applications (JFFS2 might be such a beast) D-cache could be very helpful as well. Best is to have both enabled of course. > Currently, in my config file, I have only > #define CONFIG_CMD_CACHE > What do I have to add? Defining the cache commands doesn't insure that caches are really enabled. Some platforms don't support I- and/or D-cache in U-Boot. I can only speak for PPC4xx which has I-cache enabled and "usually" D-cache disabled (because of cache-coherency issues). This might be different on your platform. Again, just enabling the cache commands will most likely not help here. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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