June 2009 - U-Boot

[U-Boot] [patch] Convert DM9000 driver for CONFIG_NET_MULTI
by Remy Bohmer 03 Jun '09

03 Jun '09

All drivers need to be converted to CONFIG_NET_MULTI. This patch converts the dm9000 driver. Signed-off-by: Thomas Smits <ts.smits(a)gmail.com> Signed-off-by: Remy Bohmer <linux(a)bohmer.net> --- board/atmel/at91sam9261ek/at91sam9261ek.c | 7 ++++ board/freescale/m5253demo/m5253demo.c | 9 +++++ board/scb9328/scb9328.c | 8 +++++ board/trizepsiv/conxs.c | 8 +++++ drivers/net/dm9000x.c | 47 +++++++++++++++++++----------- include/configs/M5253DEMO.h | 1 include/configs/at91sam9261ek.h | 1 include/configs/scb9328.h | 1 include/configs/trizepsiv.h | 1 include/netdev.h | 1 10 files changed, 67 insertions(+), 17 deletions(-) Index: u-boot-usb.tmp/board/atmel/at91sam9261ek/at91sam9261ek.c =================================================================== --- u-boot-usb.tmp.orig/board/atmel/at91sam9261ek/at91sam9261ek.c 2009-05-02 21:43:42.000000000 +0200 +++ u-boot-usb.tmp/board/atmel/at91sam9261ek/at91sam9261ek.c 2009-05-02 21:46:50.000000000 +0200 @@ -36,6 +36,7 @@ #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) #include <net.h> +#include <netdev.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -227,6 +228,12 @@ int board_init(void) return 0; } +#ifdef CONFIG_DRIVER_DM9000 + int board_eth_init(bd_t *bis) + { + return dm9000_initialize(bis); + } + #endif int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM; Index: u-boot-usb.tmp/board/freescale/m5253demo/m5253demo.c =================================================================== --- u-boot-usb.tmp.orig/board/freescale/m5253demo/m5253demo.c 2009-05-02 21:43:42.000000000 +0200 +++ u-boot-usb.tmp/board/freescale/m5253demo/m5253demo.c 2009-05-02 21:46:50.000000000 +0200 @@ -26,6 +26,7 @@ #include <common.h> #include <asm/immap.h> +#include <netdev.h> int checkboard(void) { @@ -138,3 +139,11 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_CMD_IDE */ + + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif Index: u-boot-usb.tmp/board/scb9328/scb9328.c =================================================================== --- u-boot-usb.tmp.orig/board/scb9328/scb9328.c 2009-05-02 21:43:42.000000000 +0200 +++ u-boot-usb.tmp/board/scb9328/scb9328.c 2009-05-02 21:46:50.000000000 +0200 @@ -19,6 +19,7 @@ */ #include <common.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -70,3 +71,10 @@ void show_boot_progress (int status) { return; } + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif Index: u-boot-usb.tmp/board/trizepsiv/conxs.c =================================================================== --- u-boot-usb.tmp.orig/board/trizepsiv/conxs.c 2009-05-02 21:43:42.000000000 +0200 +++ u-boot-usb.tmp/board/trizepsiv/conxs.c 2009-05-02 21:46:50.000000000 +0200 @@ -33,6 +33,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -144,3 +145,10 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif Index: u-boot-usb.tmp/drivers/net/dm9000x.c =================================================================== --- u-boot-usb.tmp.orig/drivers/net/dm9000x.c 2009-05-02 21:43:41.000000000 +0200 +++ u-boot-usb.tmp/drivers/net/dm9000x.c 2009-05-02 21:46:50.000000000 +0200 @@ -54,6 +54,9 @@ v1.2 03/18/2003 Weilun Huang <we - some minor code cleanups These changes are tested with DM9000{A,EP,E} together with a 200MHz Atmel AT91SAM92161 core + 06/10/2008 Thomas Smits <ts.smits(a)gmail.com> + - moved to funtion ptr based API + TODO: external MII is not functional, only internal at the moment. */ @@ -102,14 +105,12 @@ typedef struct board_info { void (*outblk)(volatile void *data_ptr, int count); void (*inblk)(void *data_ptr, int count); void (*rx_status)(u16 *RxStatus, u16 *RxLen); + struct eth_device netdev; } board_info_t; static board_info_t dm9000_info; + /* function declaration ------------------------------------- */ -int eth_init(bd_t * bd); -int eth_send(volatile void *, int); -int eth_rx(void); -void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); @@ -279,17 +280,16 @@ dm9000_reset(void) printf("ERROR: resetting DM9000 -> not responding\n"); } -/* Initilize dm9000 board +/* Initialize dm9000 board */ -int -eth_init(bd_t * bd) +static int dm9000_init(struct eth_device *dev, bd_t *bd) { int i, oft, lnk; u8 io_mode; struct board_info *db = &dm9000_info; uchar enetaddr[6]; - DM9000_DBG("eth_init()\n"); + DM9000_DBG("%s\n", __func__); /* RESET device */ dm9000_reset(); @@ -411,13 +411,13 @@ eth_init(bd_t * bd) Hardware start transmission. Send a packet to media from the upper layer. */ -int -eth_send(volatile void *packet, int length) +static int dm9000_send(struct eth_device *netdev, volatile void *packet, + int length) { int tmo; struct board_info *db = &dm9000_info; - DM9000_DMP_PACKET("eth_send", packet, length); + DM9000_DMP_PACKET(__func__ , packet, length); DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ @@ -453,10 +453,9 @@ eth_send(volatile void *packet, int leng Stop the interface. The interface is stopped when it is brought. */ -void -eth_halt(void) +static void dm9000_halt(struct eth_device *netdev) { - DM9000_DBG("eth_halt\n"); + DM9000_DBG("%s\n", __func__); /* RESET devie */ phy_write(0, 0x8000); /* PHY RESET */ @@ -468,8 +467,7 @@ eth_halt(void) /* Received a packet and pass to upper layer */ -int -eth_rx(void) +static int dm9000_rx(struct eth_device *netdev) { u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; u16 RxStatus, RxLen = 0; @@ -529,7 +527,7 @@ eth_rx(void) dm9000_reset(); } } else { - DM9000_DMP_PACKET("eth_rx", rdptr, RxLen); + DM9000_DMP_PACKET(__func__ , rdptr, RxLen); DM9000_DBG("passing packet to upper layer\n"); NetReceive(NetRxPackets[0], RxLen); @@ -621,3 +619,18 @@ phy_write(int reg, u16 value) DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value); } + +int dm9000_initialize(bd_t *bis) +{ + struct eth_device *dev = &(dm9000_info.netdev); + + dev->init = dm9000_init; + dev->halt = dm9000_halt; + dev->send = dm9000_send; + dev->recv = dm9000_rx; + sprintf(dev->name, "dm9000"); + + eth_register(dev); + + return 0; +} Index: u-boot-usb.tmp/include/configs/M5253DEMO.h =================================================================== --- u-boot-usb.tmp.orig/include/configs/M5253DEMO.h 2009-05-02 21:43:41.000000000 +0200 +++ u-boot-usb.tmp/include/configs/M5253DEMO.h 2009-05-02 21:46:50.000000000 +0200 @@ -88,6 +88,7 @@ # define _IO_BASE 0 #endif +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) Index: u-boot-usb.tmp/include/configs/at91sam9261ek.h =================================================================== --- u-boot-usb.tmp.orig/include/configs/at91sam9261ek.h 2009-05-02 21:43:41.000000000 +0200 +++ u-boot-usb.tmp/include/configs/at91sam9261ek.h 2009-05-02 21:46:50.000000000 +0200 @@ -132,6 +132,7 @@ #define CONFIG_SYS_NO_FLASH 1 /* Ethernet */ +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x30000000 #define DM9000_IO CONFIG_DM9000_BASE Index: u-boot-usb.tmp/include/configs/scb9328.h =================================================================== --- u-boot-usb.tmp.orig/include/configs/scb9328.h 2009-05-02 21:43:41.000000000 +0200 +++ u-boot-usb.tmp/include/configs/scb9328.h 2009-05-02 21:46:50.000000000 +0200 @@ -255,6 +255,7 @@ #define CONFIG_SYS_CS5U_VAL 0x00008400 #define CONFIG_SYS_CS5L_VAL 0x00000D03 +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x16000000 #define DM9000_IO CONFIG_DM9000_BASE Index: u-boot-usb.tmp/include/configs/trizepsiv.h =================================================================== --- u-boot-usb.tmp.orig/include/configs/trizepsiv.h 2009-05-02 21:43:41.000000000 +0200 +++ u-boot-usb.tmp/include/configs/trizepsiv.h 2009-05-02 21:46:50.000000000 +0200 @@ -277,6 +277,7 @@ #define CONFIG_SYS_MCIO0_VAL 0x00008407 #define CONFIG_SYS_MCIO1_VAL 0x0000c108 +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x08000000 #define DM9000_IO CONFIG_DM9000_BASE Index: u-boot-usb.tmp/include/netdev.h =================================================================== --- u-boot-usb.tmp.orig/include/netdev.h 2009-05-02 21:43:42.000000000 +0200 +++ u-boot-usb.tmp/include/netdev.h 2009-05-02 21:46:50.000000000 +0200 @@ -73,6 +73,7 @@ int tsi108_eth_initialize(bd_t *bis); int uec_initialize(int index); int uli526x_initialize(bd_t *bis); int sh_eth_initialize(bd_t *bis); +int dm9000_initialize(bd_t *bis); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. --

3 2

[U-Boot] [PATCH 1/1] make MODEM SUPPORT generic instead of duplicate it
by Jean-Christophe PLAGNIOL-VILLARD 03 Jun '09

03 Jun '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- common/Makefile | 1 + common/modem.c | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ lib_arm/board.c | 99 -------------------------------------------- lib_ppc/board.c | 97 ------------------------------------------- 4 files changed, 124 insertions(+), 196 deletions(-) create mode 100644 common/modem.c diff --git a/common/Makefile b/common/Makefile index f13cd11..3038e46 100644 --- a/common/Makefile +++ b/common/Makefile @@ -147,6 +147,7 @@ COBJS-y += flash.o COBJS-$(CONFIG_CMD_KGDB) += kgdb.o COBJS-$(CONFIG_LCD) += lcd.o COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o +COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o COBJS-$(CONFIG_UPDATE_TFTP) += update.o COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o diff --git a/common/modem.c b/common/modem.c new file mode 100644 index 0000000..27e164a --- /dev/null +++ b/common/modem.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* called from main loop (common/main.c) */ +/* 'inline' - We have to do it fast */ +static inline void mdm_readline(char *buf, int bufsiz) +{ + char c; + char *p; + int n; + + n = 0; + p = buf; + for(;;) { + c = serial_getc(); + + /* dbg("(%c)", c); */ + + switch(c) { + case '\r': + break; + case '\n': + *p = '\0'; + return; + + default: + if(n++ > bufsiz) { + *p = '\0'; + return; /* sanity check */ + } + *p = c; + p++; + break; + } + } +} + +extern void dbg(const char *fmt, ...); +int mdm_init (void) +{ + char env_str[16]; + char *init_str; + int i; + extern char console_buffer[]; + extern void enable_putc(void); + extern int hwflow_onoff(int); + + enable_putc(); /* enable serial_putc() */ + +#ifdef CONFIG_HWFLOW + init_str = getenv("mdm_flow_control"); + if (init_str && (strcmp(init_str, "rts/cts") == 0)) + hwflow_onoff (1); + else + hwflow_onoff(-1); +#endif + + for (i = 1;;i++) { + sprintf(env_str, "mdm_init%d", i); + if ((init_str = getenv(env_str)) != NULL) { + serial_puts(init_str); + serial_puts("\n"); + for(;;) { + mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); + dbg("ini%d: [%s]", i, console_buffer); + + if ((strcmp(console_buffer, "OK") == 0) || + (strcmp(console_buffer, "ERROR") == 0)) { + dbg("ini%d: cmd done", i); + break; + } else /* in case we are originating call ... */ + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini%d: connect", i); + return 0; + } + } + } else + break; /* no init string - stop modem init */ + + udelay(100000); + } + + udelay(100000); + + /* final stage - wait for connect */ + for(;i > 1;) { /* if 'i' > 1 - wait for connection + message from modem */ + mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); + dbg("ini_f: [%s]", console_buffer); + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini_f: connected"); + return 0; + } + } + + return 0; +} diff --git a/lib_arm/board.c b/lib_arm/board.c index 09eaaf2..7d06c0f 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -484,102 +484,3 @@ void hang (void) puts ("### ERROR ### Please RESET the board ###\n"); for (;;); } - -#ifdef CONFIG_MODEM_SUPPORT -static inline void mdm_readline(char *buf, int bufsiz); - -/* called from main loop (common/main.c) */ -extern void dbg(const char *fmt, ...); -int mdm_init (void) -{ - char env_str[16]; - char *init_str; - int i; - extern char console_buffer[]; - extern void enable_putc(void); - extern int hwflow_onoff(int); - - enable_putc(); /* enable serial_putc() */ - -#ifdef CONFIG_HWFLOW - init_str = getenv("mdm_flow_control"); - if (init_str && (strcmp(init_str, "rts/cts") == 0)) - hwflow_onoff (1); - else - hwflow_onoff(-1); -#endif - - for (i = 1;;i++) { - sprintf(env_str, "mdm_init%d", i); - if ((init_str = getenv(env_str)) != NULL) { - serial_puts(init_str); - serial_puts("\n"); - for(;;) { - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini%d: [%s]", i, console_buffer); - - if ((strcmp(console_buffer, "OK") == 0) || - (strcmp(console_buffer, "ERROR") == 0)) { - dbg("ini%d: cmd done", i); - break; - } else /* in case we are originating call ... */ - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini%d: connect", i); - return 0; - } - } - } else - break; /* no init string - stop modem init */ - - udelay(100000); - } - - udelay(100000); - - /* final stage - wait for connect */ - for(;i > 1;) { /* if 'i' > 1 - wait for connection - message from modem */ - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini_f: [%s]", console_buffer); - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini_f: connected"); - return 0; - } - } - - return 0; -} - -/* 'inline' - We have to do it fast */ -static inline void mdm_readline(char *buf, int bufsiz) -{ - char c; - char *p; - int n; - - n = 0; - p = buf; - for(;;) { - c = serial_getc(); - - /* dbg("(%c)", c); */ - - switch(c) { - case '\r': - break; - case '\n': - *p = '\0'; - return; - - default: - if(n++ > bufsiz) { - *p = '\0'; - return; /* sanity check */ - } - *p = c; - p++; - break; - } - } -} -#endif /* CONFIG_MODEM_SUPPORT */ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 3bcfb45..cb23f52 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1220,103 +1220,6 @@ void hang (void) for (;;); } -#ifdef CONFIG_MODEM_SUPPORT -/* called from main loop (common/main.c) */ -/* 'inline' - We have to do it fast */ -static inline void mdm_readline(char *buf, int bufsiz) -{ - char c; - char *p; - int n; - - n = 0; - p = buf; - for(;;) { - c = serial_getc(); - - /* dbg("(%c)", c); */ - - switch(c) { - case '\r': - break; - case '\n': - *p = '\0'; - return; - - default: - if(n++ > bufsiz) { - *p = '\0'; - return; /* sanity check */ - } - *p = c; - p++; - break; - } - } -} - -extern void dbg(const char *fmt, ...); -int mdm_init (void) -{ - char env_str[16]; - char *init_str; - int i; - extern char console_buffer[]; - extern void enable_putc(void); - extern int hwflow_onoff(int); - - enable_putc(); /* enable serial_putc() */ - -#ifdef CONFIG_HWFLOW - init_str = getenv("mdm_flow_control"); - if (init_str && (strcmp(init_str, "rts/cts") == 0)) - hwflow_onoff (1); - else - hwflow_onoff(-1); -#endif - - for (i = 1;;i++) { - sprintf(env_str, "mdm_init%d", i); - if ((init_str = getenv(env_str)) != NULL) { - serial_puts(init_str); - serial_puts("\n"); - for(;;) { - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini%d: [%s]", i, console_buffer); - - if ((strcmp(console_buffer, "OK") == 0) || - (strcmp(console_buffer, "ERROR") == 0)) { - dbg("ini%d: cmd done", i); - break; - } else /* in case we are originating call ... */ - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini%d: connect", i); - return 0; - } - } - } else - break; /* no init string - stop modem init */ - - udelay(100000); - } - - udelay(100000); - - /* final stage - wait for connect */ - for(;i > 1;) { /* if 'i' > 1 - wait for connection - message from modem */ - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini_f: [%s]", console_buffer); - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini_f: connected"); - return 0; - } - } - - return 0; -} - -#endif #if 0 /* We could use plain global data, but the resulting code is bigger */ /* -- 1.5.6.5

2 6

[U-Boot] ARM next Pull Request
by Jean-Christophe PLAGNIOL-VILLARD 03 Jun '09

03 Jun '09

Hi Wolfgang Please pull The following changes since commit cab6c2a6135cc8f4244d8e9c005bddd208d2a26f: Wolfgang Denk (1): TQM834x: use buffered writes to accelerate writing to flash are available in the git repository at: git://git.denx.de/u-boot-arm.git next Dirk Behme (2): OMAP3: Zoom2: Enable Board and CPU info OMAP3: Fix CKE1 MUX setting to allow self-refresh Jean-Christophe PLAGNIOL-VILLARD (10): afeb9260: fix macb device init arm: unify linker script arm: unify interrupt init arm: remove cpu_init pxa: move serial driver to drivers/serial lh7a40x: move serial driver to drivers/serial omap24xx: rename reset file at91: extract reset from timer at91: move cpu name define to arm/arch/ cpu header at91: move cpu info print to cpu Prafulla Wadaskar (1): arch_misc_init support for ARM architectures Tom Rix (7): ZOOM2 Add serial support. ZOOM2 Add led support. OMAP3 Turn on the GPIO bank clocks ZOOM2 Define GPIO banks used. Fix a typo in the instructions on using omap3's gpio interface. Beagle Convert the board version detection to use the OMAP3 GPIO interface. ZOOM2 detect the version of the zoom2 board at runtime. arm_config.mk | 2 + board/actux1/config.mk | 2 + board/actux2/config.mk | 2 + board/actux3/config.mk | 2 + board/armadillo/u-boot.lds | 55 -------- board/armltd/integratorap/config.mk | 6 - board/armltd/integratorap/split_by_variant.sh | 4 - board/armltd/integratorap/u-boot.lds.template | 53 -------- board/armltd/integratorcp/config.mk | 6 - board/armltd/integratorcp/split_by_variant.sh | 4 - board/armltd/integratorcp/u-boot.lds.template | 53 -------- board/armltd/versatile/u-boot.lds | 51 -------- board/atmel/at91rm9200dk/u-boot.lds | 57 --------- board/atmel/at91rm9200ek/u-boot.lds | 56 --------- board/cerf250/u-boot.lds | 56 --------- board/cm4008/u-boot.lds | 56 --------- board/cm41xx/u-boot.lds | 56 --------- board/cmc_pu2/u-boot.lds | 57 --------- board/cradle/u-boot.lds | 56 --------- board/csb226/u-boot.lds | 56 --------- board/csb637/u-boot.lds | 56 --------- board/dave/B2/u-boot.lds | 58 --------- board/davedenx/qong/u-boot.lds | 58 --------- board/delta/u-boot.lds | 56 --------- board/dnp1110/u-boot.lds | 56 --------- board/ep7312/u-boot.lds | 56 --------- board/evb4510/u-boot.lds | 69 ----------- board/freescale/mx31ads/config.mk | 2 + board/gcplus/u-boot.lds | 58 --------- board/impa7/u-boot.lds | 56 --------- board/imx31_litekit/u-boot.lds | 59 --------- board/imx31_phycore/u-boot.lds | 59 --------- board/innokom/u-boot.lds | 56 --------- board/kb9202/u-boot.lds | 56 --------- board/lart/u-boot.lds | 56 --------- board/logodl/u-boot.lds | 56 --------- board/lpc2292sodimm/u-boot.lds | 55 -------- board/lubbock/u-boot.lds | 56 --------- board/m501sk/u-boot.lds | 55 -------- board/modnet50/u-boot.lds | 69 ----------- board/mp2usb/u-boot.lds | 56 --------- board/mpl/vcma9/u-boot.lds | 57 --------- board/mx1ads/u-boot.lds | 58 --------- board/netstar/u-boot.lds | 55 -------- board/ns9750dev/u-boot.lds | 59 --------- board/omap1510inn/u-boot.lds | 57 --------- board/omap1610inn/u-boot.lds | 52 -------- board/omap2420h4/u-boot.lds | 59 --------- board/omap3/beagle/beagle.c | 32 +++-- board/omap3/beagle/beagle.h | 2 +- board/omap3/overo/overo.h | 2 +- board/omap3/zoom2/Makefile | 7 +- board/omap3/zoom2/led.c | 129 +++++++++++++++++++ board/omap3/zoom2/zoom2.c | 102 +++++++++++++++- board/omap3/zoom2/zoom2.h | 9 ++ board/omap3/zoom2/zoom2_serial.c | 130 ++++++++++++++++++++ board/omap3/zoom2/zoom2_serial.h | 75 +++++++++++ board/pleb2/u-boot.lds | 56 --------- board/prodrive/pdnb3/u-boot.lds | 56 --------- board/ronetix/pm9263/pm9263.c | 7 - board/samsung/smdk2400/u-boot.lds | 57 --------- board/samsung/smdk2410/u-boot.lds | 57 --------- board/samsung/smdk6400/config.mk | 2 + board/sbc2410x/u-boot.lds | 56 --------- board/shannon/u-boot.lds | 56 --------- board/siemens/SMN42/u-boot.lds | 55 -------- board/sx1/u-boot.lds | 57 --------- board/trab/config.mk | 2 + board/trizepsiv/u-boot.lds | 56 --------- board/voiceblue/u-boot.lds | 56 --------- board/wepep250/u-boot.lds | 56 --------- board/xaeniax/u-boot.lds | 56 --------- board/xsengine/u-boot.lds | 56 --------- board/zylonite/u-boot.lds | 56 --------- common/serial.c | 2 + cpu/arm1136/cpu.c | 16 --- cpu/arm1136/omap24xx/Makefile | 2 +- cpu/arm1136/omap24xx/{start.S => reset.S} | 0 {board/apollon => cpu/arm1136}/u-boot.lds | 5 +- cpu/arm1176/cpu.c | 5 - {board/omap5912osk => cpu/arm1176}/u-boot.lds | 10 +- cpu/arm720t/cpu.c | 12 -- cpu/arm720t/interrupts.c | 2 +- {board/scb9328 => cpu/arm720t}/u-boot.lds | 7 +- cpu/arm920t/cpu.c | 16 --- {board/xm250 => cpu/arm920t}/u-boot.lds | 14 ++- cpu/arm925t/cpu.c | 16 --- {board/lpd7a40x => cpu/arm925t}/u-boot.lds | 10 +- cpu/arm926ejs/at91/Makefile | 1 + cpu/arm926ejs/at91/at91sam9260_devices.c | 2 +- cpu/arm926ejs/at91/config.mk | 1 - cpu/arm926ejs/at91/cpu.c | 19 +++- .../u-boot.lds => cpu/arm926ejs/at91/reset.c | 60 +++------- cpu/arm926ejs/at91/timer.c | 15 --- cpu/arm926ejs/at91/u-boot.lds | 57 --------- cpu/arm926ejs/cpu.c | 16 --- cpu/arm926ejs/davinci/config.mk | 2 - {board/st/nmdk8815 => cpu/arm926ejs}/u-boot.lds | 11 ++- cpu/arm946es/cpu.c | 16 --- {board/omap730p2 => cpu/arm946es}/u-boot.lds | 10 +- cpu/arm_cortexa8/cpu.c | 17 --- cpu/arm_cortexa8/omap3/clock.c | 22 ++++ cpu/arm_cortexa8/omap3/config.mk | 2 - cpu/arm_cortexa8/{omap3 => }/u-boot.lds | 0 cpu/arm_intcm/cpu.c | 16 --- cpu/{arm926ejs/davinci => arm_intcm}/u-boot.lds | 10 +- cpu/ixp/cpu.c | 17 --- cpu/ixp/interrupts.c | 2 +- {board/ixdp425 => cpu/ixp}/u-boot.lds | 8 +- cpu/lh7a40x/Makefile | 2 +- cpu/lh7a40x/cpu.c | 16 --- {board/st/nmdk8815 => cpu/lh7a40x}/u-boot.lds | 9 +- cpu/pxa/Makefile | 1 - cpu/pxa/cpu.c | 16 --- {board/pxa255_idp => cpu/pxa}/u-boot.lds | 6 +- cpu/s3c44b0/cpu.c | 2 +- {board/mx1fs2 => cpu/s3c44b0}/u-boot.lds | 5 +- cpu/sa1100/cpu.c | 12 -- {board/assabet => cpu/sa1100}/u-boot.lds | 7 +- doc/README.omap3 | 2 +- drivers/serial/Makefile | 2 + drivers/serial/ns16550.c | 4 +- .../serial.c => drivers/serial/serial_lh7a40x.c | 0 cpu/pxa/serial.c => drivers/serial/serial_pxa.c | 0 include/asm-arm/arch-at91/at91cap9.h | 5 + include/asm-arm/arch-at91/at91sam9260.h | 9 ++ include/asm-arm/arch-at91/at91sam9261.h | 4 + include/asm-arm/arch-at91/at91sam9263.h | 4 + include/asm-arm/arch-at91/at91sam9rl.h | 5 + include/asm-arm/u-boot-arm.h | 2 + include/configs/B2.h | 1 + include/configs/at91cap9adk.h | 1 - include/configs/at91sam9260ek.h | 2 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/cerf250.h | 1 + include/configs/cradle.h | 1 + include/configs/csb226.h | 1 + include/configs/delta.h | 1 + include/configs/innokom.h | 1 + include/configs/logodl.h | 1 + include/configs/lpd7a400.h | 1 + include/configs/lpd7a404.h | 1 + include/configs/lubbock.h | 1 + include/configs/omap3_zoom2.h | 56 +++++++-- include/configs/pleb2.h | 1 + include/configs/pm9263.h | 3 +- include/configs/pxa255_idp.h | 1 + include/configs/trizepsiv.h | 1 + include/configs/wepep250.h | 1 + include/configs/xaeniax.h | 1 + include/configs/xm250.h | 1 + include/configs/xsengine.h | 1 + include/configs/zylonite.h | 1 + include/serial.h | 7 + lib_arm/board.c | 5 +- lib_arm/interrupts.c | 13 ++ 158 files changed, 740 insertions(+), 3432 deletions(-) delete mode 100644 board/armadillo/u-boot.lds delete mode 100644 board/armltd/integratorap/u-boot.lds.template delete mode 100644 board/armltd/integratorcp/u-boot.lds.template delete mode 100644 board/armltd/versatile/u-boot.lds delete mode 100644 board/atmel/at91rm9200dk/u-boot.lds delete mode 100644 board/atmel/at91rm9200ek/u-boot.lds delete mode 100644 board/cerf250/u-boot.lds delete mode 100644 board/cm4008/u-boot.lds delete mode 100644 board/cm41xx/u-boot.lds delete mode 100644 board/cmc_pu2/u-boot.lds delete mode 100644 board/cradle/u-boot.lds delete mode 100644 board/csb226/u-boot.lds delete mode 100644 board/csb637/u-boot.lds delete mode 100644 board/dave/B2/u-boot.lds delete mode 100644 board/davedenx/qong/u-boot.lds delete mode 100644 board/delta/u-boot.lds delete mode 100644 board/dnp1110/u-boot.lds delete mode 100644 board/ep7312/u-boot.lds delete mode 100644 board/evb4510/u-boot.lds delete mode 100644 board/gcplus/u-boot.lds delete mode 100644 board/impa7/u-boot.lds delete mode 100644 board/imx31_litekit/u-boot.lds delete mode 100644 board/imx31_phycore/u-boot.lds delete mode 100644 board/innokom/u-boot.lds delete mode 100644 board/kb9202/u-boot.lds delete mode 100644 board/lart/u-boot.lds delete mode 100644 board/logodl/u-boot.lds delete mode 100644 board/lpc2292sodimm/u-boot.lds delete mode 100644 board/lubbock/u-boot.lds delete mode 100644 board/m501sk/u-boot.lds delete mode 100644 board/modnet50/u-boot.lds delete mode 100644 board/mp2usb/u-boot.lds delete mode 100644 board/mpl/vcma9/u-boot.lds delete mode 100644 board/mx1ads/u-boot.lds delete mode 100644 board/netstar/u-boot.lds delete mode 100644 board/ns9750dev/u-boot.lds delete mode 100644 board/omap1510inn/u-boot.lds delete mode 100644 board/omap1610inn/u-boot.lds delete mode 100644 board/omap2420h4/u-boot.lds create mode 100644 board/omap3/zoom2/led.c create mode 100644 board/omap3/zoom2/zoom2_serial.c create mode 100644 board/omap3/zoom2/zoom2_serial.h delete mode 100644 board/pleb2/u-boot.lds delete mode 100644 board/prodrive/pdnb3/u-boot.lds delete mode 100644 board/samsung/smdk2400/u-boot.lds delete mode 100644 board/samsung/smdk2410/u-boot.lds delete mode 100644 board/sbc2410x/u-boot.lds delete mode 100644 board/shannon/u-boot.lds delete mode 100644 board/siemens/SMN42/u-boot.lds delete mode 100644 board/sx1/u-boot.lds delete mode 100644 board/trizepsiv/u-boot.lds delete mode 100644 board/voiceblue/u-boot.lds delete mode 100644 board/wepep250/u-boot.lds delete mode 100644 board/xaeniax/u-boot.lds delete mode 100644 board/xsengine/u-boot.lds delete mode 100644 board/zylonite/u-boot.lds rename cpu/arm1136/omap24xx/{start.S => reset.S} (100%) rename {board/apollon => cpu/arm1136}/u-boot.lds (94%) rename {board/omap5912osk => cpu/arm1176}/u-boot.lds (96%) rename {board/scb9328 => cpu/arm720t}/u-boot.lds (92%) rename {board/xm250 => cpu/arm920t}/u-boot.lds (84%) rename {board/lpd7a40x => cpu/arm925t}/u-boot.lds (91%) rename board/actux4/u-boot.lds => cpu/arm926ejs/at91/reset.c (56%) delete mode 100644 cpu/arm926ejs/at91/u-boot.lds copy {board/st/nmdk8815 => cpu/arm926ejs}/u-boot.lds (92%) rename {board/omap730p2 => cpu/arm946es}/u-boot.lds (96%) rename cpu/arm_cortexa8/{omap3 => }/u-boot.lds (100%) rename cpu/{arm926ejs/davinci => arm_intcm}/u-boot.lds (96%) rename {board/ixdp425 => cpu/ixp}/u-boot.lds (94%) rename {board/st/nmdk8815 => cpu/lh7a40x}/u-boot.lds (96%) rename {board/pxa255_idp => cpu/pxa}/u-boot.lds (96%) rename {board/mx1fs2 => cpu/s3c44b0}/u-boot.lds (96%) rename {board/assabet => cpu/sa1100}/u-boot.lds (95%) rename cpu/lh7a40x/serial.c => drivers/serial/serial_lh7a40x.c (100%) rename cpu/pxa/serial.c => drivers/serial/serial_pxa.c (100%) Best Regards, J.

2 3

[U-Boot] Please pull u-boot-coldfire next
by Liew Tsi Chung-R5AAHP 03 Jun '09

03 Jun '09

Hi Wolfgang, Please pull this change for u-boot-coldfire/next into your next branch: The following changes since commit 9f2b981c3b47a12f8e2691b68776c4fbe0fb1394: Stefan Roese (1): ppc4xx: Remove PCI async bootup message if PCI is not used are available in the git repository at: git://www.denx.de/git/u-boot-coldfire.git next Richard Retanubun (3): Adds WATCHDOG_RESET() function call to lib_m68k dtimer_interrupt. Compier warning cleanup Coldfire M5271: Activate u-boot system timer interrupt. include/asm-m68k/immap.h | 2 +- lib_m68k/board.c | 3 +-- lib_m68k/time.c | 13 ++++++++++++- 3 files changed, 14 insertions(+), 4 deletions(-) Thanks. Regards, TsiChung

2 1

[U-Boot] Pull request u-boot-blackfin.git
by Mike Frysinger 03 Jun '09

03 Jun '09

The following changes since commit 5520ab1f7685721314dcfb7cdcc7c15e6571473f: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-blackfin are available in the git repository at: git://www.denx.de/git/u-boot-blackfin.git master Mike Frysinger (2): Blackfin: fix if() logic in bootrom evt1 check Blackfin: spi: fix pin handling of SPI0 SSEL4 drivers/spi/bfin_spi.c | 2 +- include/asm-blackfin/blackfin-config-pre.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

2 1

Re: [U-Boot] [PATCH 2/3] ZOOM2 detect the version of the zoom2
by Tom Rix 03 Jun '09

03 Jun '09

Jean-Christophe, Based on your review I have made the changes you asked for. Tom > @@ -60,6 +61,46 @@ static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { > 0x1D0904C4, 0 > }; > > +/* Used to track the revision of the board */ > +int zoom2_revision = ZOOM2_REVISION_UNKNOWN; add static and as the beagle provide a function to get the current version > + Tom : Ok added See +/* Used to track the revision of the board */ +static ZOOM2_REVISION zoom2_revision = ZOOM2_REVISION_UNKNOWN; + +/* + * Routine: zoom2_get_revision + * Description: Return the revision of the Zoom2 this code is running on. + */ +ZOOM2_REVISION zoom2_get_revision(void) +{ + return zoom2_revision; +} ------------------------------------------------------------------- > + printf("Board revision "); > + if (ZOOM2_REVISION_PRODUCTION == zoom2_revision) > + printf("Production\n"); > + else if (ZOOM2_REVISION_BETA == zoom2_revision) > + printf("Beta\n"); > + else > + printf("Unknown\n"); please use switch > +} Tom : Ok done. See + switch (zoom2_revision) { + case (ZOOM2_REVISION_PRODUCTION): + printf("Production\n"); + break; + case (ZOOM2_REVISION_BETA): + printf("Beta\n"); + break; + default: + printf("Unknown\n"); + break; + } +} ------------------------------------------------------- > +#define ZOOM2_REVISION_UNKNOWN 0 > +#define ZOOM2_REVISION_ALPHA 1 > +#define ZOOM2_REVISION_BETA 2 > +#define ZOOM2_REVISION_PRODUCTION 3 please use an emum Tom : Ok See +typedef enum { + ZOOM2_REVISION_UNKNOWN = 0, + ZOOM2_REVISION_ALPHA, + ZOOM2_REVISION_BETA, + ZOOM2_REVISION_PRODUCTION +} ZOOM2_REVISION; ---------------------------------------------------------- Also changed this comment in beagle.c /* * Routine: beagle_get_revision - * Description: Return revision of the BeagleBoard this code is running on. + * Description: Return the revision of the BeagleBoard this code is running on.

3 8

[U-Boot] OMAP3, Zoom2 Initializing GPIO bank clocks
by Tom Rix 03 Jun '09

03 Jun '09

In OMAP3, the GPIO bank clocks should only be turned on as needed. This is done at the config file level. Zoom2 uses GPIO so it must turn on the GPIO bank clocks it needs.

2 4

[U-Boot] Zoom2, Beagle board revision detection.
by Tom Rix 03 Jun '09

03 Jun '09

This is against the arm/next branch Zoom2 has two meaningful board revisions : production and beta. This change will allow the board differences to be handled at runtime. The Zoom2 change is based on how the Beagle Board does its board revision but since it is newer, it uses the OMAP3 GPIO API that was recently added. This was run tested on Zoom2 beta and production boards. Since I was taking a close look at the Beagle code, I updated it to also use the OMAP3 GPIO API. This was run tested on a Beagle B7 board. A version C board was not available for testing. It would be good if someone verified the Beagle change with a versioin C board. Tom

4 7

[U-Boot] [PATCH-ARM] Add support for Embest SBC2440-II Board
by kevin.morfitt＠fearnside-systems.co.uk 03 Jun '09

03 Jun '09

Implementation based on the existing u-boot support for S3C2410-based boards. u-boot programmed into NOR flash. Tested on an SBC2440-II Board using tftp to copy the files from a server and programming them into NAND flash. MAKEALL used to build all LIST_ARM9 targets only - no other architectures built as the changes only affect ARM9-based boards. Signed-off-by: Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> --- MAKEALL | 1 + Makefile | 3 + board/embest/sbc2440ii/Makefile | 55 +++++++ board/embest/sbc2440ii/config.mk | 25 +++ board/embest/sbc2440ii/lowlevel_init.S | 219 +++++++++++++++++++++++++++ board/embest/sbc2440ii/sbc2440ii.c | 127 ++++++++++++++++ board/embest/sbc2440ii/u-boot.lds | 56 +++++++ common/serial.c | 4 +- cpu/arm920t/s3c24x0/speed.c | 83 ++++++++--- cpu/arm920t/s3c24x0/timer.c | 6 +- cpu/arm920t/s3c24x0/usb.c | 6 +- cpu/arm920t/s3c24x0/usb_ohci.c | 2 + cpu/arm920t/start.S | 35 ++++- drivers/i2c/s3c24x0_i2c.c | 18 +++ drivers/mtd/nand/Makefile | 2 +- drivers/mtd/nand/s3c2410_nand.c | 223 +++++++++++++++++++++++----- drivers/rtc/s3c24x0_rtc.c | 2 + drivers/serial/serial_s3c24x0.c | 2 + include/common.h | 3 +- include/configs/sbc2440ii.h | 252 ++++++++++++++++++++++++++++++++ include/s3c2440.h | 231 +++++++++++++++++++++++++++++ include/s3c24x0.h | 83 +++++++++++ 22 files changed, 1362 insertions(+), 76 deletions(-) create mode 100644 board/embest/sbc2440ii/Makefile create mode 100644 board/embest/sbc2440ii/config.mk create mode 100644 board/embest/sbc2440ii/lowlevel_init.S create mode 100644 board/embest/sbc2440ii/sbc2440ii.c create mode 100644 board/embest/sbc2440ii/u-boot.lds create mode 100644 include/configs/sbc2440ii.h create mode 100644 include/s3c2440.h diff --git a/MAKEALL b/MAKEALL index c98d03a..e7235e4 100755 --- a/MAKEALL +++ b/MAKEALL @@ -515,6 +515,7 @@ LIST_ARM9=" \ omap5912osk \ omap730p2 \ sbc2410x \ + sbc2440ii \ scb9328 \ smdk2400 \ smdk2410 \ diff --git a/Makefile b/Makefile index 81a5cd0..38f79c2 100644 --- a/Makefile +++ b/Makefile @@ -2876,6 +2876,9 @@ omap730p2_cs3boot_config : unconfig sbc2410x_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 +sbc2440ii_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t sbc2440ii embest s3c24x0 + scb9328_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx diff --git a/board/embest/sbc2440ii/Makefile b/board/embest/sbc2440ii/Makefile new file mode 100644 index 0000000..85a56fa --- /dev/null +++ b/board/embest/sbc2440ii/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by: +# (C) Copyright 2009 +# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sbc2440ii.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/embest/sbc2440ii/config.mk b/board/embest/sbc2440ii/config.mk new file mode 100644 index 0000000..def11d8 --- /dev/null +++ b/board/embest/sbc2440ii/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# +# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by: +# (C) Copyright 2009 +# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + +# +# SBC2440-II has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3800'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# +# we load ourself to 33F8'0000 +# +# download area is 3000'0000 + +TEXT_BASE = 0x33F80000 diff --git a/board/embest/sbc2440ii/lowlevel_init.S b/board/embest/sbc2440ii/lowlevel_init.S new file mode 100644 index 0000000..90de392 --- /dev/null +++ b/board/embest/sbc2440ii/lowlevel_init.S @@ -0,0 +1,219 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +/* + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar(a)sec.samsung.com> + */ + +#define BWSCON 0x48000000 + +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1 << 2) +#define UBLB (0x1 << 3) + +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) +#define BWSCON_VAL ((B1_BWSCON << 4) + (B2_BWSCON << 8) + \ + (B3_BWSCON << 12) + (B4_BWSCON << 16) + \ + (B5_BWSCON << 20) + (B6_BWSCON << 24) + \ + (B7_BWSCON << 28)) + +#define B0_TACS 0x0 +#define B0_TCOS 0x0 +#define B0_TACC 0x7 +#define B0_TCOH 0x0 +#define B0_TAH 0x0 +#define B0_TACP 0x0 +#define B0_PMC 0x0 +#define BANKCON0_VAL ((B0_TACS << 13) + (B0_TCOS << 11) + (B0_TACC << 8) + \ + (B0_TCOH << 6) + (B0_TAH << 4) + (B0_TACP << 2) + \ + B0_PMC) + +#define B1_TACS 0x0 +#define B1_TCOS 0x0 +#define B1_TACC 0x7 +#define B1_TCOH 0x0 +#define B1_TAH 0x0 +#define B1_TACP 0x0 +#define B1_PMC 0x0 +#define BANKCON1_VAL ((B1_TACS << 13) + (B1_TCOS << 11) + (B1_TACC << 8) + \ + (B1_TCOH << 6) + (B1_TAH << 4) + (B1_TACP << 2) + \ + B1_PMC) + +#define B2_TACS 0x0 +#define B2_TCOS 0x0 +#define B2_TACC 0x7 +#define B2_TCOH 0x0 +#define B2_TAH 0x0 +#define B2_TACP 0x0 +#define B2_PMC 0x0 +#define BANKCON2_VAL ((B2_TACS << 13) + (B2_TCOS << 11) + (B2_TACC << 8) + \ + (B2_TCOH << 6) + (B2_TAH << 4) + (B2_TACP << 2) + \ + B2_PMC) + +#define B3_TACS 0x0 /* 0clk */ +#define B3_TCOS 0x3 /* 4clk */ +#define B3_TACC 0x7 /* 14clk */ +#define B3_TCOH 0x1 /* 1clk */ +#define B3_TAH 0x3 /* 4clk */ +#define B3_TACP 0x3 /* 6clk */ +#define B3_PMC 0x0 /* 16data */ +#define BANKCON3_VAL ((B3_TACS << 13) + (B3_TCOS << 11) + (B3_TACC << 8) + \ + (B3_TCOH << 6) + (B3_TAH << 4) + (B3_TACP << 2) + \ + B3_PMC) + +#define B4_TACS 0x0 +#define B4_TCOS 0x0 +#define B4_TACC 0x7 +#define B4_TCOH 0x0 +#define B4_TAH 0x0 +#define B4_TACP 0x0 +#define B4_PMC 0x0 +#define BANKCON4_VAL ((B4_TACS << 13) + (B4_TCOS << 11) + (B4_TACC << 8) + \ + (B4_TCOH << 6) + (B4_TAH << 4) + (B4_TACP << 2) + \ + B4_PMC) + +#define B5_TACS 0x0 +#define B5_TCOS 0x0 +#define B5_TACC 0x7 +#define B5_TCOH 0x0 +#define B5_TAH 0x0 +#define B5_TACP 0x0 +#define B5_PMC 0x0 +#define BANKCON5_VAL ((B5_TACS << 13) + (B5_TCOS << 11) + (B5_TACC << 8) + \ + (B5_TCOH << 6) + (B5_TAH << 4) + (B5_TACP << 2) + \ + B5_PMC) + +#define B6_MT 0x3 /* SDRAM */ +#define B6_TRCD 0x2 +#define B6_SCAN 0x1 /* 9bit */ +#define BANKCON6_VAL ((B6_MT << 15) + (B6_TRCD << 2) + B6_SCAN) + +#define B7_MT 0x3 /* SDRAM */ +#define B7_TRCD 0x2 /* 4clk */ +#define B7_SCAN 0x1 /* 9bit */ +#define BANKCON7_VAL ((B7_MT << 15) + (B7_TRCD << 2) + B7_SCAN) + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define TRP 0x0 /* 2clk */ +#define TRC 0x3 /* 7clk */ +#define TCHR 0x2 /* 3clk */ +#define REFCNT 1259 +#define REFRESH_VAL ((REFEN << 23) + (TREFMD << 22) + (TRP << 20) + \ + (TRC << 18) + (TCHR << 16) + REFCNT) + +/* BANKSIZE parameter */ +#define BURST_EN 1 /* Enable burst mode */ +#define SCKE_EN 1 /* Enable SDRAM power-down mode */ +#define SCLK_EN 1 /* SCLK is active only during the access */ +#define BK67MAP 2 /* 128M/128M */ +#define BANKSIZE_VAL ((BURST_EN << 7) + (SCKE_EN << 5) + \ + (SCLK_EN << 4) + BK67MAP) + +/* MRSRB6 parameter */ +#define WBL6 0 /* Burst */ +#define TM6 0 /* Modem register set */ +#define CL6 3 /* Latency is 3 clocks */ +#define BT6 0 /* Sequential */ +#define BL6 0 +#define MRSRB6_VAL ((WBL6 << 9) + (TM6 << 7) + (CL6 << 4) + \ + (BT6 << 3) + BL6) + +/* MRSRB7 parameter */ +#define WBL7 0 /* Burst */ +#define TM7 0 /* Modem register set */ +#define CL7 3 /* Latency is 3 clocks */ +#define BT7 0 /* Sequential */ +#define BL7 0 +#define MRSRB7_VAL ((WBL7 << 9) + (TM7 << 7) + (CL7 << 4) + \ + (BT7 << 3) + BL7) + +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word BWSCON_VAL + .word BANKCON0_VAL + .word BANKCON1_VAL + .word BANKCON2_VAL + .word BANKCON3_VAL + .word BANKCON4_VAL + .word BANKCON5_VAL + .word BANKCON6_VAL + .word BANKCON7_VAL + .word REFRESH_VAL + .word BANKSIZE_VAL + .word MRSRB6_VAL + .word MRSRB7_VAL diff --git a/board/embest/sbc2440ii/sbc2440ii.c b/board/embest/sbc2440ii/sbc2440ii.c new file mode 100644 index 0000000..e0599dd --- /dev/null +++ b/board/embest/sbc2440ii/sbc2440ii.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <s3c2440.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Configure the PLLs for MPLL = 400MHz, UPLL = 48MHz + The clock frequency ratios are set to 1:4:8 ie: + PCLK = 50MHz + HCLK = 100MHz + FCLK = 400MHz + */ +/* The MPLL values. */ +#define M_MDIV 0x5C +#define M_PDIV 1 +#define M_SDIV 1 + +/* The UPLL values. */ +#define U_MDIV 0x38 +#define U_PDIV 2 +#define U_SDIV 2 + +/* + * Miscellaneous platform dependent initialisations + */ + +static inline void pll_settle_delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +int board_init(void) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->LOCKTIME = 0xFFFFFFFF; + + /* configure UPLL */ + clk_power->UPLLCON = ((U_MDIV << 12) + (U_PDIV << 4) + U_SDIV); + + /* some delay between UPLL and MPLL */ + pll_settle_delay(8000); + + /* configure MPLL */ + clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* configure the GPIO */ + gpio->GPACON = 0x007FFFFF; + gpio->GPBCON = 0x00055555; + gpio->GPBUP = 0x000007FF; + gpio->GPBDAT = 0x000001C0; /* Switch on LED1. */ + gpio->GPCCON = 0xAAAAAAAA; + gpio->GPCUP = 0x0000FFFF; + gpio->GPDCON = 0xAAAAAAAA; + gpio->GPDUP = 0x0000FFFF; + gpio->GPECON = 0xAAAAA800; + gpio->GPEUP = 0x00001FFF; + gpio->GPFCON = 0x000055AA; + gpio->GPFUP = 0x000000FF; + gpio->GPGCON = 0xFD95FFBA; + gpio->GPGUP = 0x0000FFFF; + gpio->GPHCON = 0x0002FAAA; + gpio->GPHUP = 0x000007FF; + gpio->GPJCON = 0x02FAAAAA; + gpio->GPJUP = 0x00001FFF; + + gpio->EXTINT0 = 0x22222222; + gpio->EXTINT1 = 0x22222222; + gpio->EXTINT2 = 0x22222222; + gpio->EINTMASK = 0x00FFFFF0; + + /* arch number of SBC2440-II Board */ + gd->bd->bi_arch_number = MACH_TYPE_SBC2440II; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + icache_enable(); + dcache_enable(); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/embest/sbc2440ii/u-boot.lds b/board/embest/sbc2440ii/u-boot.lds new file mode 100644 index 0000000..3b79776 --- /dev/null +++ b/board/embest/sbc2440ii/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +} diff --git a/common/serial.c b/common/serial.c index 09385d0..fe8799c 100644 --- a/common/serial.c +++ b/common/serial.c @@ -58,7 +58,7 @@ struct serial_device *__default_serial_console (void) #else return &serial0_device; #endif -#elif defined(CONFIG_S3C2410) +#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) #if defined(CONFIG_SERIAL1) return &s3c24xx_serial0_device; #elif defined(CONFIG_SERIAL2) @@ -131,7 +131,7 @@ void serial_initialize (void) #if defined (CONFIG_STUART) serial_register(&serial_stuart_device); #endif -#if defined(CONFIG_S3C2410) +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) serial_register(&s3c24xx_serial0_device); serial_register(&s3c24xx_serial1_device); serial_register(&s3c24xx_serial2_device); diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c index e0dca62..064e22e 100644 --- a/cpu/arm920t/s3c24x0/speed.c +++ b/cpu/arm920t/s3c24x0/speed.c @@ -30,12 +30,15 @@ */ #include <common.h> -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ + defined(CONFIG_S3C2440) || defined(CONFIG_TRAB) #if defined(CONFIG_S3C2400) #include <s3c2400.h> #elif defined(CONFIG_S3C2410) #include <s3c2410.h> +#elif defined(CONFIG_S3C2440) +#include <s3c2440.h> #endif #define MPLL 0 @@ -53,49 +56,81 @@ static ulong get_PLLCLK(int pllreg) { - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - ulong r, m, p, s; - - if (pllreg == MPLL) - r = clk_power->MPLLCON; - else if (pllreg == UPLL) - r = clk_power->UPLLCON; - else - hang(); - - m = ((r & 0xFF000) >> 12) + 8; - p = ((r & 0x003F0) >> 4) + 2; - s = r & 0x3; - - return((CONFIG_SYS_CLK_FREQ * m) / (p << s)); + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + ulong r, m, p, s; + + if (pllreg == MPLL) + r = clk_power->MPLLCON; + else if (pllreg == UPLL) + r = clk_power->UPLLCON; + else + hang(); + + m = ((r & 0xFF000) >> 12) + 8; + p = ((r & 0x003F0) >> 4) + 2; + s = r & 0x3; + +#ifdef CONFIG_S3C2440 + if (pllreg == MPLL) + return (2 * CONFIG_SYS_CLK_FREQ * m) / (p << s); + else + return (CONFIG_SYS_CLK_FREQ * m) / (p << s); +#else + return (CONFIG_SYS_CLK_FREQ * m) / (p << s); +#endif } /* return FCLK frequency */ ulong get_FCLK(void) { - return(get_PLLCLK(MPLL)); + return get_PLLCLK(MPLL); } /* return HCLK frequency */ ulong get_HCLK(void) { - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - - return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK()); + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + +#ifdef CONFIG_S3C2440 + switch (clk_power->CLKDIVN & 0x6) { + default: + case 0: + return get_FCLK(); + case 2: + return get_FCLK()/2; + case 4: + return (clk_power->CAMDIVN & (1<<9)) ? + get_FCLK()/8 : get_FCLK()/4; + case 6: + return (clk_power->CAMDIVN & (1<<8)) ? + get_FCLK()/6 : get_FCLK()/3; + } +#else + return (clk_power->CLKDIVN & 0x2) ? + get_FCLK()/2 : get_FCLK(); +#endif } /* return PCLK frequency */ ulong get_PCLK(void) { - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK()); + return (clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK(); } /* return UCLK frequency */ ulong get_UCLK(void) { - return(get_PLLCLK(UPLL)); +#ifdef CONFIG_S3C2440 + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + + return (clk_power->CLKDIVN & (1<<3)) ? + get_PLLCLK(UPLL)/2 : get_PLLCLK(UPLL); +#else + return get_PLLCLK(UPLL); +#endif } -#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \ + defined (CONFIG_S3C2440) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index f0a09cd..134d644 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -30,12 +30,15 @@ */ #include <common.h> -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ + defined(CONFIG_S3C2440) || defined(CONFIG_TRAB) #if defined(CONFIG_S3C2400) #include <s3c2400.h> #elif defined(CONFIG_S3C2410) #include <s3c2410.h> +#elif defined(CONFIG_S3C2440) +#include <s3c2440.h> #endif int timer_load_val = 0; @@ -177,6 +180,7 @@ ulong get_tbclk (void) tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \ + defined(CONFIG_SBC2440II) || \ defined(CONFIG_VCMA9) tbclk = CONFIG_SYS_HZ; #else diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index 9ccf575..962ef0d 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -24,12 +24,16 @@ #include <common.h> #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) +# if defined(CONFIG_S3C2400) || \ + defined(CONFIG_S3C2410) || \ + defined(CONFIG_S3C2440) #if defined(CONFIG_S3C2400) # include <s3c2400.h> #elif defined(CONFIG_S3C2410) # include <s3c2410.h> +#elif defined(CONFIG_S3C2440) +#include <s3c2440.h> #endif int usb_cpu_init (void) diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 7838014..6a46eed 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -42,6 +42,8 @@ #include <s3c2400.h> #elif defined(CONFIG_S3C2410) #include <s3c2410.h> +#elif defined(CONFIG_S3C2440) +#include <s3c2440.h> #endif #include <malloc.h> diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 475cdaf..7e9e6f8 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -132,20 +132,30 @@ copyex: bne copyex #endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) +#if defined(CONFIG_S3C2400) || \ + defined(CONFIG_S3C2410) || \ + defined(CONFIG_S3C2440) /* turn off the watchdog */ # if defined(CONFIG_S3C2400) -# define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define pWTCON 0x15300000 +# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ # define CLKDIVN 0x14800014 /* clock divisor register */ #else -# define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define pWTCON 0x53000000 +# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ # define INTSUBMSK 0x4A00001C # define CLKDIVN 0x4C000014 /* clock divisor register */ # endif +# if defined(CONFIG_S3C2440) +# define INTSMASK 0xffff +# define CLKDIVVAL 0x5 +#else +# define INTSMASK 0x3ff +# define CLKDIVVAL 0x3 +# endif + ldr r0, =pWTCON mov r1, #0x0 str r1, [r0] @@ -156,8 +166,8 @@ copyex: mov r1, #0xffffffff ldr r0, =INTMSK str r1, [r0] -# if defined(CONFIG_S3C2410) - ldr r1, =0x3ff +# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + ldr r1, =INTSMASK ldr r0, =INTSUBMSK str r1, [r0] # endif @@ -165,9 +175,16 @@ copyex: /* FCLK:HCLK:PCLK = 1:2:4 */ /* default FCLK is 120 MHz ! */ ldr r0, =CLKDIVN - mov r1, #3 + mov r1, #CLKDIVVAL str r1, [r0] -#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ + +#ifdef CONFIG_S3C2440 + /* Set asynchronous bus mode */ + mrc p15, 0, r1, c1, c0, 0 /* read ctrl register */ + orr r1, r1, #0xc0000000 /* Asynchronous */ + mcr p15, 0, r1, c1, c0, 0 /* write ctrl register */ +#endif /* CONFIG_S3C2440 */ +#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */ /* * we do sys-critical inits only at reboot, diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index f0c1aa3..28bf314 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -31,6 +31,8 @@ #include <s3c2400.h> #elif defined(CONFIG_S3C2410) #include <s3c2410.h> +#elif defined(CONFIG_S3C2440) +#include <s3c2440.h> #endif #include <i2c.h> @@ -66,6 +68,9 @@ static int GetI2CSDA(void) #ifdef CONFIG_S3C2400 return (gpio->PGDAT & 0x0020) >> 5; #endif +#ifdef CONFIG_S3C2440 + return (gpio->GPEDAT & 0x8000) >> 15; +#endif } #if 0 @@ -85,6 +90,9 @@ static void SetI2CSCL(int x) #ifdef CONFIG_S3C2400 gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; #endif +#ifdef CONFIG_S3C2440 + gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; +#endif } @@ -142,6 +150,9 @@ void i2c_init (int speed, int slaveadd) #ifdef CONFIG_S3C2400 ulong old_gpecon = gpio->PGCON; #endif +#ifdef CONFIG_S3C2440 + ulong old_gpecon = gpio->GPECON; +#endif /* bus still busy probably by (most) previously interrupted transfer */ #ifdef CONFIG_S3C2410 @@ -152,6 +163,10 @@ void i2c_init (int speed, int slaveadd) /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000; #endif +#ifdef CONFIG_S3C2440 + /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ + gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; +#endif /* toggle I2CSCL until bus idle */ SetI2CSCL (0); @@ -174,6 +189,9 @@ void i2c_init (int speed, int slaveadd) #ifdef CONFIG_S3C2400 gpio->PGCON = old_gpecon; #endif +#ifdef CONFIG_S3C2440 + gpio->GPECON = old_gpecon; +#endif } /* calculate prescaler and divisor values */ diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 471cd6b..190abeb 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -41,7 +41,7 @@ COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o -COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c +COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o endif diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index d27a625..8438a89 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -20,46 +20,93 @@ #include <common.h> -#if 0 -#define DEBUGN printf +#include <nand.h> +#ifndef CONFIG_S3C2440 + #include <s3c2410.h> #else -#define DEBUGN(x, args ...) {} + #include <s3c2440.h> #endif - -#include <nand.h> -#include <s3c2410.h> #include <asm/io.h> #define __REGb(x) (*(volatile unsigned char *)(x)) #define __REGi(x) (*(volatile unsigned int *)(x)) +#define __REGl(x) (*(volatile unsigned long *)(x)) #define NF_BASE 0x4e000000 #define NFCONF __REGi(NF_BASE + 0x0) -#define NFCMD __REGb(NF_BASE + 0x4) -#define NFADDR __REGb(NF_BASE + 0x8) -#define NFDATA __REGb(NF_BASE + 0xc) -#define NFSTAT __REGb(NF_BASE + 0x10) -#define NFECC0 __REGb(NF_BASE + 0x14) -#define NFECC1 __REGb(NF_BASE + 0x15) -#define NFECC2 __REGb(NF_BASE + 0x16) - -#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) + +#ifdef CONFIG_S3C2440 + #define NFCONT __REGb(NF_BASE + 0x4) + #define NFCMD __REGb(NF_BASE + 0x8) + #define NFADDR __REGb(NF_BASE + 0xc) + #define NFDATA __REGb(NF_BASE + 0x10) + #define NFSTAT __REGb(NF_BASE + 0x20) + #define NFMECC0 __REGl(NF_BASE + 0x2c) + + #define S3C2440_NFCONT_EN (1<<0) + #define S3C2440_NFCONT_nFCE (1<<1) + #define S3C2440_NFCONT_INITECC (1<<4) + #define S3C2440_NFCONT_MAINECCLOCK (1<<5) + #define S3C2440_NFCONT_SPAREECCLOCK (1<<6) + #define S3C2440_NFCONT_RNBMODE (1<<8) + #define S3C2440_NFCONT_RNBINT (1<<9) + #define S3C2440_NFCONT_ILLEGALINT (1<<10) + #define S3C2440_NFCONT_SOFTLOCK (1<<12) + #define S3C2440_NFCONT_LOCKTIGHT (1<<13) + + #define S3C2440_NFCONF_TACLS(x) ((x)<<12) + #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) + #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) +#else + #define NFCMD __REGb(NF_BASE + 0x4) + #define NFADDR __REGb(NF_BASE + 0x8) + #define NFDATA __REGb(NF_BASE + 0xc) + #define NFSTAT __REGb(NF_BASE + 0x10) + #define NFECC0 __REGb(NF_BASE + 0x14) + #define NFECC1 __REGb(NF_BASE + 0x15) + #define NFECC2 __REGb(NF_BASE + 0x16) + + #define S3C2410_NFCONF_EN (1<<15) + #define S3C2410_NFCONF_512BYTE (1<<14) + #define S3C2410_NFCONF_4STEP (1<<13) + #define S3C2410_NFCONF_INITECC (1<<12) + #define S3C2410_NFCONF_nFCE (1<<11) + #define S3C2410_NFCONF_TACLS(x) ((x)<<8) + #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) + #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) +#endif #define S3C2410_ADDR_NALE 4 #define S3C2410_ADDR_NCLE 8 + +#ifdef CONFIG_S3C2410_NAND_HWECC +/* new oob placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob = { + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {8, 8} } +}; +#endif + +static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) +{ + if (chip == -1) { + debugX(1, "Negating nFCE\n"); + NFCONT |= S3C2440_NFCONT_nFCE; + } else { + debugX(1, "Asserting nFCE\n"); + NFCONT &= ~S3C2440_NFCONT_nFCE; + } +} + +#ifndef CONFIG_S3C2440 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; - DEBUGN("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); + debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = NF_BASE; @@ -80,27 +127,58 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W); } +#else +static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) { + debugX(1, "NFCMD = 0x%08X\n", cmd); + NFCMD = cmd; + } + + if (ctrl & NAND_ALE) { + debugX(1, "NFADDR = 0x%08X\n", cmd); + NFADDR = cmd; + } +} +#endif static int s3c2410_dev_ready(struct mtd_info *mtd) { - DEBUGN("dev_ready\n"); + debugX(1, "dev_ready\n"); return (NFSTAT & 0x01); } #ifdef CONFIG_S3C2410_NAND_HWECC void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { - DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); + debugX(2, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); +#ifndef CONFIG_S3C2440 NFCONF |= S3C2410_NFCONF_INITECC; +#else + NFCONT |= S3C2440_NFCONT_INITECC; +#endif } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { +#ifndef CONFIG_S3C2440 ecc_code[0] = NFECC0; ecc_code[1] = NFECC1; ecc_code[2] = NFECC2; - DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", +#else + unsigned long ecc = NFMECC0; + + ecc_code[0] = ecc; + ecc_code[1] = ecc >> 8; + ecc_code[2] = ecc >> 16; +#endif + debugX(2, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); return 0; @@ -109,12 +187,53 @@ static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { - if (read_ecc[0] == calc_ecc[0] && - read_ecc[1] == calc_ecc[1] && - read_ecc[2] == calc_ecc[2]) - return 0; + unsigned int diff0, diff1, diff2; + unsigned int bit, byte; + + debugX(2, "s3c2410_nand_correct_data:\n"); + + diff0 = read_ecc[0] ^ calc_ecc[0]; + diff1 = read_ecc[1] ^ calc_ecc[1]; + diff2 = read_ecc[2] ^ calc_ecc[2]; + + debugX(3, "rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n", + read_ecc[0], read_ecc[1], read_ecc[2], + calc_ecc[0], calc_ecc[1], calc_ecc[2], + diff0, diff1, diff2); + + if (diff0 == 0 && diff1 == 0 && diff2 == 0) + return 0; /* ECC is ok */ + + /* Can we correct this ECC (ie, one row and column change). + * Note, this is similar to the 256 error code on smartmedia */ + + if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && + ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && + ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { + /* calculate the bit position of the error */ + + bit = ((diff2 >> 3) & 1) | + ((diff2 >> 4) & 2) | + ((diff2 >> 5) & 4); + + /* calculate the byte position of the error */ + byte = ((diff2 << 7) & 0x100) | + ((diff1 << 0) & 0x80) | + ((diff1 << 1) & 0x40) | + ((diff1 << 2) & 0x20) | + ((diff1 << 3) & 0x10) | + ((diff0 >> 4) & 0x08) | + ((diff0 >> 3) & 0x04) | + ((diff0 >> 2) & 0x02) | + ((diff0 >> 1) & 0x01); + + debugX(2, "correcting error bit %d, byte %d\n", bit, byte); + + dat[byte] ^= (1 << bit); + return 1; + } - printf("s3c2410_nand_correct_data: not implemented\n"); + debugX(2, "Failed to correct ECC error\n"); return -1; } #endif @@ -125,11 +244,12 @@ int board_nand_init(struct nand_chip *nand) u_int8_t tacls, twrph0, twrph1; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - DEBUGN("board_nand_init()\n"); + debugX(1, "board_nand_init()\n"); clk_power->CLKCON |= (1 << 4); /* initialize hardware */ +#ifndef CONFIG_S3C2440 twrph0 = 3; twrph1 = 0; tacls = 0; cfg = S3C2410_NFCONF_EN; @@ -141,20 +261,49 @@ int board_nand_init(struct nand_chip *nand) /* initialize nand_chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e00000c; +#else + twrph0 = 3; twrph1 = 1; tacls = 0; + + cfg = S3C2440_NFCONF_TACLS(tacls); + cfg |= S3C2440_NFCONF_TWRPH0(twrph0); + cfg |= S3C2440_NFCONF_TWRPH1(twrph1); + NFCONF = cfg; + + cfg = S3C2440_NFCONT_EN; + cfg |= S3C2440_NFCONT_nFCE; + NFCONT = cfg; + + /* initialize nand_chip data structure */ + nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e000010; +#endif /* read_buf and write_buf are default */ /* read_byte and write_byte are default */ + nand->select_chip = s3c2410_nand_select_chip; + nand->chip_delay = 50; + /* hwcontrol always must be implemented */ nand->cmd_ctrl = s3c2410_hwcontrol; nand->dev_ready = s3c2410_dev_ready; #ifdef CONFIG_S3C2410_NAND_HWECC - nand->ecc.hwctl = s3c2410_nand_enable_hwecc; - nand->ecc.calculate = s3c2410_nand_calculate_ecc; - nand->ecc.correct = s3c2410_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW3_512; + nand->ecc.correct = s3c2410_nand_correct_data; + nand->ecc.hwctl = s3c2410_nand_enable_hwecc; + nand->ecc.calculate = s3c2410_nand_calculate_ecc; + nand->ecc.mode = NAND_ECC_HW; + /* change the behaviour depending on whether we are using + * the large or small page nand device */ + if (nand->page_shift > 10) { + nand->ecc.size = 256; + nand->ecc.bytes = 3; + } else { + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.layout = &nand_hw_eccoob; + } + debugX(2, "ecc: size: %d bytes: %d\n", nand->ecc.size, nand->ecc.bytes); #else nand->ecc.mode = NAND_ECC_SOFT; #endif @@ -165,7 +314,7 @@ int board_nand_init(struct nand_chip *nand) nand->options = 0; #endif - DEBUGN("end of nand_init\n"); + debugX(1, "end of nand_init\n"); return 0; } diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 0d3372f..8f7559b 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -34,6 +34,8 @@ #include <s3c2400.h> #elif defined(CONFIG_S3C2410) #include <s3c2410.h> +#elif defined(CONFIG_S3C2440) +#include <s3c2440.h> #endif #include <rtc.h> diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 6d69c43..52d5895 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -23,6 +23,8 @@ #include <s3c2400.h> #elif defined(CONFIG_S3C2410) #include <s3c2410.h> +#elif defined(CONFIG_S3C2440) +#include <s3c2440.h> #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/include/common.h b/include/common.h index 30fff7d..161277f 100644 --- a/include/common.h +++ b/include/common.h @@ -490,7 +490,8 @@ ulong get_OPB_freq (void); ulong get_PCI_freq (void); #endif #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ - defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400) + defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400) || \ + defined(CONFIG_S3C2440) void s3c2410_irq(void); #define ARM920_IRQ_CALLBACK s3c2410_irq ulong get_FCLK (void); diff --git a/include/configs/sbc2440ii.h b/include/configs/sbc2440ii.h new file mode 100644 index 0000000..4836769 --- /dev/null +++ b/include/configs/sbc2440ii.h @@ -0,0 +1,252 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * Gary Jennejohn <gj(a)denx.de> + * David Mueller <d.mueller(a)elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * Configuation settings for the friendly-arm SBC-2410X board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +#define CONFIG_IDENT_STRING " for Embest SBC2440-II" + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ +#define CONFIG_SBC2440II 1 /* on an Embest SBC-2440-II Board */ + +/* + * input clock of PLL - the SBC2440-II has 12MHz input clock + */ +#define CONFIG_SYS_CLK_FREQ 12000000 + + +#define USE_920T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +/* + * size in bytes reserved for initial data + */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x19000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2440-II */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_JFFS2_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=sbc2440-II-nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=sbc2440-II-nand:2m(kernel),62m(rootfs)" +#define CONFIG_EXTRA_ENV_SETTINGS "autostart=yes" + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS \ +"noinitrd root=/dev/mtdblock1 rootfstype=jffs2 init=/linuxrc console=ttySAC0" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.69 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.70 +#define CONFIG_ROOTPATH FRNSIDE-1/netshared +#define CONFIG_LOADADDR 30008000 +/*#define CONFIG_BOOTFILE "elinos-lart" */ +#define CONFIG_BOOTCOMMAND "nboot 30008000 0 0" +/*#define CONFIG_NFSBOOTCOMMAND NFS_BOOTARGS*/ + +#if defined(CONFIG_CMD_KGDB) +/* + * speed to run kgdb serial port + */ +#define CONFIG_KGDB_BAUDRATE 115200 +/* + * which serial port to use + */ +#define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "[ SBC2440-II ]# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x30000000 +#define CONFIG_SYS_MEMTEST_END 0x33F00000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ + +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +#define CONFIG_SYS_HZ 1562500 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +/*----------------------------------------------------------------------- + * FLASH and environment and organization + */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x00200000 /* 2MB */ +#define CONFIG_SYS_MAX_FLASH_SECT (35) +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) + +/*----------------------------------------------------------------------- + * NAND flash settings + */ +#if defined(CONFIG_CMD_NAND) + #define CONFIG_NAND_S3C2410 + #define CONFIG_SYS_NAND_BASE 0x4e00000c + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define SECTORSIZE 512 +/* #define CONFIG_S3C2410_NAND_HWECC*/ +#endif /* CONFIG_CMD_NAND */ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#else +#define CONFIG_AUTO_COMPLETE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/s3c2440.h b/include/s3c2440.h new file mode 100644 index 0000000..df2eb7a --- /dev/null +++ b/include/s3c2440.h @@ -0,0 +1,231 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller(a)elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2440.h + * Version : 24.10.2008 + * + * Based on S3C2440X User's manual Rev 1.3 + ************************************************/ + +#ifndef __S3C2440_H__ +#define __S3C2440_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2410 only supports 512 Byte HW ECC */ +#define S3C2410_ECCSIZE 512 +#define S3C2410_ECCBYTES 3 + +typedef enum { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +} S3C24X0_UARTS_NR; + +/* S3C2440 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2440_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2410_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2410_SDI_BASE 0x5A000000 + + +/* include common stuff */ +#include <s3c24x0.h> + + +static inline S3C24X0_MEMCTL *S3C24X0_GetBase_MEMCTL(void) +{ + return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; +} +static inline S3C24X0_USB_HOST *S3C24X0_GetBase_USB_HOST(void) +{ + return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; +} +static inline S3C24X0_INTERRUPT *S3C24X0_GetBase_INTERRUPT(void) +{ + return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; +} +static inline S3C24X0_DMAS *S3C24X0_GetBase_DMAS(void) +{ + return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; +} +static inline S3C24X0_CLOCK_POWER *S3C24X0_GetBase_CLOCK_POWER(void) +{ + return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; +} +static inline S3C24X0_LCD *S3C24X0_GetBase_LCD(void) +{ + return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; +} +static inline S3C2440_NAND *S3C2440_GetBase_NAND(void) +{ + return (S3C2440_NAND * const)S3C2440_NAND_BASE; +} +static inline S3C24X0_UART *S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) +{ + return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); +} +static inline S3C24X0_TIMERS *S3C24X0_GetBase_TIMERS(void) +{ + return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; +} +static inline S3C24X0_USB_DEVICE *S3C24X0_GetBase_USB_DEVICE(void) +{ + return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; +} +static inline S3C24X0_WATCHDOG *S3C24X0_GetBase_WATCHDOG(void) +{ + return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; +} +static inline S3C24X0_I2C *S3C24X0_GetBase_I2C(void) +{ + return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; +} +static inline S3C24X0_I2S *S3C24X0_GetBase_I2S(void) +{ + return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; +} +static inline S3C24X0_GPIO *S3C24X0_GetBase_GPIO(void) +{ + return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; +} +static inline S3C24X0_RTC *S3C24X0_GetBase_RTC(void) +{ + return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; +} +static inline S3C2410_ADC *S3C2410_GetBase_ADC(void) +{ + return (S3C2410_ADC * const)S3C2410_ADC_BASE; +} +static inline S3C24X0_SPI *S3C24X0_GetBase_SPI(void) +{ + return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; +} +static inline S3C2410_SDI *S3C2410_GetBase_SDI(void) +{ + return (S3C2410_SDI * const)S3C2410_SDI_BASE; +} + + +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__S3C2440_H__*/ diff --git a/include/s3c24x0.h b/include/s3c24x0.h index 71f35a5..c51d58e 100644 --- a/include/s3c24x0.h +++ b/include/s3c24x0.h @@ -126,6 +126,9 @@ typedef struct { S3C24X0_REG32 CLKCON; S3C24X0_REG32 CLKSLOW; S3C24X0_REG32 CLKDIVN; +#ifdef CONFIG_S3C2440 + S3C24X0_REG32 CAMDIVN; +#endif } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER; @@ -154,6 +157,7 @@ typedef struct { } /*__attribute__((__packed__))*/ S3C24X0_LCD; +#ifdef CONFIG_S3C2410 /* NAND FLASH (see S3C2410 manual chapter 6) */ typedef struct { S3C24X0_REG32 NFCONF; @@ -163,6 +167,27 @@ typedef struct { S3C24X0_REG32 NFSTAT; S3C24X0_REG32 NFECC; } /*__attribute__((__packed__))*/ S3C2410_NAND; +#elif defined CONFIG_S3C2440 +/* NAND FLASH (see S3C2440 manual chapter 6 ) */ +typedef struct { + S3C24X0_REG32 NFCONF; + S3C24X0_REG32 NFCONT; + S3C24X0_REG32 NFCMD; + S3C24X0_REG32 NFADDR; + S3C24X0_REG32 NFDATA; + S3C24X0_REG32 NFMECCD0; + S3C24X0_REG32 NFMECCD1; + S3C24X0_REG32 NFSECCD; + S3C24X0_REG32 NFSTAT; + S3C24X0_REG32 NFESTAT0; + S3C24X0_REG32 NFESTAT1; + S3C24X0_REG32 NFMECC0; + S3C24X0_REG32 NFMECC1; + S3C24X0_REG32 NFSECC; + S3C24X0_REG32 NFSBLOCK; + S3C24X0_REG32 NFEBLOCK; +} /*__attribute__((__packed__))*/ S3C2440_NAND; +#endif /* UART (see manual chapter 11) */ @@ -451,6 +476,64 @@ typedef struct { S3C24X0_REG32 GSTATUS3; S3C24X0_REG32 GSTATUS4; #endif +#ifdef CONFIG_S3C2440 + S3C24X0_REG32 GPACON; + S3C24X0_REG32 GPADAT; + S3C24X0_REG32 res1[2]; + S3C24X0_REG32 GPBCON; + S3C24X0_REG32 GPBDAT; + S3C24X0_REG32 GPBUP; + S3C24X0_REG32 res2; + S3C24X0_REG32 GPCCON; + S3C24X0_REG32 GPCDAT; + S3C24X0_REG32 GPCUP; + S3C24X0_REG32 res3; + S3C24X0_REG32 GPDCON; + S3C24X0_REG32 GPDDAT; + S3C24X0_REG32 GPDUP; + S3C24X0_REG32 res4; + S3C24X0_REG32 GPECON; + S3C24X0_REG32 GPEDAT; + S3C24X0_REG32 GPEUP; + S3C24X0_REG32 res5; + S3C24X0_REG32 GPFCON; + S3C24X0_REG32 GPFDAT; + S3C24X0_REG32 GPFUP; + S3C24X0_REG32 res6; + S3C24X0_REG32 GPGCON; + S3C24X0_REG32 GPGDAT; + S3C24X0_REG32 GPGUP; + S3C24X0_REG32 res7; + S3C24X0_REG32 GPHCON; + S3C24X0_REG32 GPHDAT; + S3C24X0_REG32 GPHUP; + S3C24X0_REG32 res8; + + S3C24X0_REG32 MISCCR; + S3C24X0_REG32 DCLKCON; + S3C24X0_REG32 EXTINT0; + S3C24X0_REG32 EXTINT1; + S3C24X0_REG32 EXTINT2; + S3C24X0_REG32 EINTFLT0; + S3C24X0_REG32 EINTFLT1; + S3C24X0_REG32 EINTFLT2; + S3C24X0_REG32 EINTFLT3; + S3C24X0_REG32 EINTMASK; + S3C24X0_REG32 EINTPEND; + S3C24X0_REG32 GSTATUS0; + S3C24X0_REG32 GSTATUS1; + S3C24X0_REG32 GSTATUS2; + S3C24X0_REG32 GSTATUS3; + S3C24X0_REG32 GSTATUS4; + S3C24X0_REG32 res9; + + S3C24X0_REG32 DSC0; + S3C24X0_REG32 DSC1; + S3C24X0_REG32 MSLCON; + S3C24X0_REG32 GPJCON; + S3C24X0_REG32 GPJDAT; + S3C24X0_REG32 GPJUP; +#endif } /*__attribute__((__packed__))*/ S3C24X0_GPIO; -- 1.6.0.6

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[U-Boot] USB gadget interface from cdc branch into mainline
by Ragha 03 Jun '09

03 Jun '09

Hello, The gadget interface at cdc branch [1] sounds good. Any plans for merging it into mainline? Regards, -Ragha [1] http://git.denx.de/?p=u-boot/u-boot-usb.git;a=shortlog;h=refs/heads/cdc

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