May 2009 - U-Boot

Re: [U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code
by HeungJun, Kim 30 May '09

30 May '09

Ok. Jean. Very thanks to review. I have a question about one thing you pointed out. === as it's nearly only in asm implement it in assembly olny will be better > + /* ES2 onwards we can disable/enable L2 ourselves */ > + if (get_cpu_rev() >= CPU_3XX_ES20) { > + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); > + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); === I think you tell me the position is in the assembly code like lowlevel_init.S. Is it right? Can you explain more detailed about this part, plz? :) If my thinking is alright, I'll re-update this patch soon. Best Regards, Riverful ----- 원본 메시지 ----- 보낸 사람: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> 보낸 날짜: 2009년 5월 30일 토요일 오전 6:46 받는 사람: Kim, Heung Jun <riverful(a)gmail.com> 참조: u-boot(a)lists.denx.de; Dirk Behme <dirk.behme(a)googlemail.com>; riverful.kim(a)samsung.com; inki.dae(a)samsung.com; mk7.kang(a)samsung.com; kyungmin.park(a)samsung.com; bhmin(a)samsung.com; jh106.choi(a)samsung.com 제목: Re: [U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code On 20:27 Fri 29 May , Kim, Heung Jun wrote: > The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved > to cpu/arm_cortexa8/omap3/cache.c. please mention omap3 in the title too > > Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> > --- > + * (C) Copyright 2002 > + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +/* > + * L2 cache specific code > + */ > + > +#include <common.h> > +#include <command.h> > +#include <asm/arch/sys_proto.h> > + > +void l2_cache_enable() > +{ > + unsigned long i; > + volatile unsigned int j; > + as it's nearly only in asm implement it in assembly olny will be better > + /* ES2 onwards we can disable/enable L2 ourselves */ > + if (get_cpu_rev() >= CPU_3XX_ES20) { > + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); > + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); <snip> > diff --git a/include/asm-arm/arch-omap3/sys_proto.h > b/include/asm-arm/arch-omap3/sys_proto.h > index 7361d08..4f43aef 100644 > --- a/include/asm-arm/arch-omap3/sys_proto.h > +++ b/include/asm-arm/arch-omap3/sys_proto.h > @@ -63,5 +63,7 @@ void make_cs1_contiguous(void); > void omap_nand_switch_ecc(int); > void power_init_r(void); > void dieid_num_r(void); > +void l2_cache_disable(); > +void l2_cache_enable(); please move these two funtcions in include/asm-arm/cache.h please rebase it against the u-boot-arm/next Best Regards, J.

1 0

[U-Boot] MICROWORD CORPORATIONS:Final notification to Lottery Winners.
by MICROWORD CORPORATIONS 30 May '09

30 May '09

MICROWORD CORPORATIONS CUSTOMER SERVICE: MADRID - ESPAÑA . REFERENCE NUMBER: MSFT-008-X54-BX BATCH NUMBER: MSFT-2008- GM-001 YOUR MSFT WORD RESOURCE LINK: www.microword.com OFFICIAL WINNING NOTIFICATION. We are pleased to inform you of the released results of Sweepstakes Promotion organized by Microword Corporations, in conjunction with the foundation for the promotion of software products, held on 29th may 2009, in Madrid, Spain. Your email address won a cash award of Four hundred and eighty eight thousand six hundred and twenty euros (488,620.00 Euros). Contact Our Foreign Transfer Manager for claims. Mr. Fernando Sanchez Email:fersanchez@sify.com Congratulations!! Sincerely, Denim DYZER. Promotions Manager. Msft Word Resource Madrid.

1 0

[U-Boot] (no subject)
by UKL-DEPT 30 May '09

30 May '09

You are among the winners of the CAMELOT INTERNATIONAL PROMOTION PROGRAM.(£891,934,00 GBP) Prof.Derek Max E-mail:(derek_max@9.cn) 1. Full Names: ………2. Gender:…….3. Age:……..4.Contact Address:……5. Country of Residence:…………6. Nationality:…………7. Occupation:…….8.Telephone Mobile #:…………….9.Choose your claims option.(1)Courier Delivery (2)Bank Transfer

1 0

[U-Boot] Cross-compiling U-Boot on Mac OS X -- can't find crc32.c?
by Timur Tabi 30 May '09

30 May '09

I'm trying to cross-compile U-Boot on a Mac OS X system, which is BSD-like. I have a toolchain already created - I've been able to compile the Linux kernel with no problems. I figured U-Boot would be easier, but instead it's doing a lot of weird stuff. So when I run "make", I get this: $ make ARCH=ppc for dir in tools examples api_examples ; do make -C $dir _depend ; done make[1]: Nothing to be done for `_depend'. make[1]: Circular hello_world.c <- hello_world.c dependency dropped. make[1]: Circular sched.c <- sched.c dependency dropped. make[1]: Circular stubs.c <- stubs.c dependency dropped. make[1]: Circular ppc_longjmp.S <- ppc_longjmp.S dependency dropped. make[1]: Circular ppc_setjmp.S <- ppc_setjmp.S dependency dropped. make[1]: Nothing to be done for `_depend'. make[1]: Nothing to be done for `_depend'. make -C tools all cc -Wall -pedantic -idirafter /Volumes/Goliath/Users/timur/dev/u-boot.git/include -idirafter /Volumes/Goliath/Users/timur/dev/u-boot.git/include2 -idirafter /Volumes/Goliath/Users/timur/dev/u-boot.git/include -I /Volumes/Goliath/Users/timur/dev/u-boot.git/libfdt -I /Volumes/Goliath/Users/timur/dev/u-boot.git/tools -DTEXT_BASE=0xFE000000 -DUSE_HOSTCC -D__KERNEL_STRICT_NAMES -O -c -o crc32.o crc32.c powerpc-apple-darwin9-gcc-4.0.1: crc32.c: No such file or directory powerpc-apple-darwin9-gcc-4.0.1: no input files make[1]: *** [crc32.o] Error 1 make: *** [tools] Error 2 crc32.c is in lib_generic/, but the current directory is tools/, so I'm not surprised it doesn't compile. Has anyone tried this before? What am I missing? -- Timur Tabi Linux kernel developer at Freescale

5 12

[U-Boot] [PATCH] nand/onenand: Fix missing argument checking for "markbad" command
by Wolfgang Denk 30 May '09

30 May '09

The "nand markbad" and "onenand markbad" commands did not check if an argument was passed; if this was forgotten, no error was raised but block 0 was marked as bad. While fixing this bug, clean up the code a bit and allow to pass more than one block address, thus allowing to mark several blocks as bad in a single command invocation. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- common/cmd_nand.c | 35 +++++++++++++++++++++++------------ common/cmd_onenand.c | 37 ++++++++++++++++++++++++------------- 2 files changed, 47 insertions(+), 25 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 1992531..cc35f38 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -414,18 +414,29 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } if (strcmp(cmd, "markbad") == 0) { - addr = (ulong)simple_strtoul(argv[2], NULL, 16); + argc -= 2; + argv += 2; - int ret = nand->block_markbad(nand, addr); - if (ret == 0) { - printf("block 0x%08lx successfully marked as bad\n", - (ulong) addr); - return 0; - } else { - printf("block 0x%08lx NOT marked as bad! ERROR %d\n", - (ulong) addr, ret); + if (argc <= 0) + goto usage; + + while (argc > 0) { + addr = simple_strtoul(*argv, NULL, 16); + + if (nand->block_markbad(nand, addr)) { + printf("block 0x%08lx NOT marked " + "as bad! ERROR %d\n", + addr, ret); + ret = 1; + } else { + printf("block 0x%08lx successfully " + "marked as bad\n", + addr); + } + --argc; + ++argv; } - return 1; + return ret; } if (strcmp(cmd, "biterr") == 0) { @@ -476,7 +487,7 @@ usage: return 1; } -U_BOOT_CMD(nand, 5, 1, do_nand, +U_BOOT_CMD(nand, CONFIG_SYS_MAXARGS, 1, do_nand, "NAND sub-system", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" @@ -489,7 +500,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand bad - show bad blocks\n" "nand dump[.oob] off - dump page\n" "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" - "nand markbad off - mark bad block at offset (UNSAFE)\n" + "nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n" #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK "nand lock [tight] [status]\n" diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 5832ff8..c4f158e 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -336,7 +336,7 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int blocksize; ulong addr, ofs; size_t len, retlen = 0; - int ret; + int ret = 0; char *cmd, *s; mtd = &onenand_mtd; @@ -430,18 +430,29 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } if (strcmp(cmd, "markbad") == 0) { - addr = (ulong)simple_strtoul(argv[2], NULL, 16); + argc -= 2; + argv += 2; - int ret = mtd->block_markbad(mtd, addr); - if (ret == 0) { - printf("block 0x%08lx successfully marked as bad\n", - (ulong) addr); - return 0; - } else { - printf("block 0x%08lx NOT marked as bad! ERROR %d\n", - (ulong) addr, ret); + if (argc <= 0) + goto usage; + + while (argc > 0) { + addr = simple_strtoul(*argv, NULL, 16); + + if (mtd->block_markbad(mtd, addr)) { + printf("block 0x%08lx NOT marked " + "as bad! ERROR %d\n", + addr, ret); + ret = 1; + } else { + printf("block 0x%08lx successfully " + "marked as bad\n", + addr); + } + --argc; + ++argv; } - return 1; + return ret; } if (strncmp(cmd, "dump", 4) == 0) { @@ -470,7 +481,7 @@ usage: } U_BOOT_CMD( - onenand, 6, 1, do_onenand, + onenand, CONFIG_SYS_MAXARGS, 1, do_onenand, "OneNAND sub-system", "info - show available OneNAND devices\n" "onenand bad - show bad blocks\n" @@ -482,5 +493,5 @@ U_BOOT_CMD( "onenand test [off size] - test 'size' bytes from\n" " offset 'off' (entire device if not specified)\n" "onenand dump[.oob] off - dump page\n" - "onenand markbad off - mark bad block at offset (UNSAFE)\n" + "onenand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n" ); -- 1.6.0.6

2 1

[U-Boot] [PATCH] Add a + prefix form to nand commands.
by Josh Karabin 30 May '09

30 May '09

Permit the use of a + prefix to sizes in nand commands to extend operations to multiples of the appropriate page or erase block size. Signed-off-by: Josh Karabin <gkarabin(a)vocollect.com> --- common/cmd_nand.c | 122 +++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 99 insertions(+), 23 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 1992531..516363e 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -102,14 +102,23 @@ static inline int str2long(char *p, ulong *num) } static int -arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size) +arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, + size_t *size, size_t *headsize, size_t *tailsize) { int idx = nand_curr_device; + char *ps = argv[1]; + size_t max_tailsize; #if defined(CONFIG_CMD_MTDPARTS) struct mtd_device *dev; struct part_info *part; u8 pnum; +#endif + max_tailsize = *tailsize; + + if (argc >= 1 && *ps == '+') + ps++; +#if defined(CONFIG_CMD_MTDPARTS) if (argc >= 1 && !(str2long(argv[0], off))) { if ((mtdparts_init() == 0) && (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) { @@ -119,8 +128,8 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size } *off = part->offset; if (argc >= 2) { - if (!(str2long(argv[1], (ulong *)size))) { - printf("'%s' is not a number\n", argv[1]); + if (!(str2long(ps, (ulong *)size))) { + printf("'%s' is not a number\n", ps); return -1; } if (*size > part->size) @@ -145,8 +154,8 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size } if (argc >= 2) { - if (!(str2long(argv[1], (ulong *)size))) { - printf("'%s' is not a number\n", argv[1]); + if (!(str2long(ps, (ulong *)size))) { + printf("'%s' is not a number\n", ps); return -1; } } else { @@ -156,6 +165,16 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size #if defined(CONFIG_CMD_MTDPARTS) out: #endif + if (ps != argv[1]) { + *tailsize = *size & (max_tailsize - 1); + *headsize = *size - *tailsize; + if (*tailsize) + *size = *headsize + max_tailsize; + } else { + *tailsize = 0; + *headsize = *size; + } + printf("device %d ", idx); if (*size == nand->size) puts("whole chip\n"); @@ -229,6 +248,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int quiet = 0; #endif const char *quiet_str = getenv("quiet"); + size_t tailsize = 0; + size_t headsize = 0; /* at least two arguments please */ if (argc < 2) @@ -317,12 +338,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf("\nNAND %s: ", scrub ? "scrub" : "erase"); /* skip first two or three arguments, look for offset and size */ - if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0) + tailsize = nand->erasesize; + if (arg_off_size(argc - o, argv + o, nand, &off, &size, + &headsize, &tailsize) != 0) return 1; memset(&opts, 0, sizeof(opts)); opts.offset = off; - opts.length = size; + opts.length = headsize; opts.jffs2 = clean; opts.quiet = quiet; @@ -346,7 +369,18 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return -1; } } - ret = nand_erase_opts(nand, &opts); + + if (headsize) + ret = nand_erase_opts(nand, &opts); + else + ret = 0; + + if (!ret && tailsize) { + opts.offset = off + headsize; + opts.length = nand->erasesize; + ret = nand_erase_opts(nand, &opts); + } + printf("%s\n", ret ? "ERROR" : "OK"); return ret == 0 ? 0 : 1; @@ -378,23 +412,52 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ printf("\nNAND %s: ", read ? "read" : "write"); - if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0) + tailsize = nand->writesize; + if (arg_off_size(argc - 3, argv + 3, nand, &off, &size, + &headsize, &tailsize) != 0) return 1; s = strchr(cmd, '.'); if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) - ret = nand_read_skip_bad(nand, off, &size, - (u_char *)addr); - else - ret = nand_write_skip_bad(nand, off, &size, - (u_char *)addr); + ret = nand_read_skip_bad(nand, off, &headsize, + (u_char *)addr); + else { + if (headsize) + ret = nand_write_skip_bad(nand, off, + &headsize, + (u_char *)addr); + else + ret = 0; + + if (!ret && tailsize) { + size_t pagesize = nand->writesize; + u_char *tailpage; + + tailpage = malloc(pagesize); + if (tailpage) { + memcpy(tailpage, + (u_char *)addr + + headsize, tailsize); + memset(tailpage + tailsize, + 0xff, + pagesize - tailsize); + ret = nand_write_skip_bad( + nand, + off + headsize, + &pagesize, + tailpage); + } + else + ret = 1; + } + } } else if (!strcmp(s, ".oob")) { /* out-of-band data */ mtd_oob_ops_t ops = { .oobbuf = (u8 *)addr, - .ooblen = size, + .ooblen = size + tailsize, .mode = MTD_OOB_RAW }; @@ -457,10 +520,20 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } if (strcmp(cmd, "unlock") == 0) { - if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0) + tailsize = nand->erasesize; + if (arg_off_size(argc - 2, argv + 2, nand, &off, &size, + &headsize, &tailsize) < 0) return 1; - if (!nand_unlock(nand, off, size)) { + if (headsize) + ret = nand_unlock(nand, off, headsize); + else + ret = 0; + + if (!ret && tailsize) + ret = nand_unlock(nand, off+headsize, nand->erasesize); + + if (!ret) { puts("NAND flash successfully unlocked\n"); } else { puts("Error unlocking NAND flash, " @@ -480,12 +553,14 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "NAND sub-system", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" - "nand read - addr off|partition size\n" - "nand write - addr off|partition size\n" + "nand read - addr off|partition [+]size\n" + "nand write - addr off|partition [+]size\n" " read/write 'size' bytes starting at offset 'off'\n" - " to/from memory address 'addr', skipping bad blocks.\n" - "nand erase [clean] [off size] - erase 'size' bytes from\n" - " offset 'off' (entire device if not specified)\n" + " to/from memory address 'addr', skipping bad blocks,\n" + " extending to a page size if '+' is specified.\n" + "nand erase [clean] [off [+]size] - erase 'size' bytes from\n" + " extending to an erase block if '+' is specified,\n" + " from offset 'off' (entire device if not specified)\n" "nand bad - show bad blocks\n" "nand dump[.oob] off - dump page\n" "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" @@ -494,7 +569,8 @@ U_BOOT_CMD(nand, 5, 1, do_nand, #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK "nand lock [tight] [status]\n" " bring nand to lock state or display locked pages\n" - "nand unlock [offset] [size] - unlock section\n" + "nand unlock [offset] [[+]size] - unlock section\n" + " extending to an erase block if + is specified.\n" #endif ); -- 1.6.0.4

2 1

[U-Boot] [PATCH 1/2 V2] afeb9260: fix macb device init
by Jean-Christophe PLAGNIOL-VILLARD 30 May '09

30 May '09

uses PA10, PA11 for ETX2 and ETX3. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- cpu/arm926ejs/at91/at91sam9260_devices.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index 6dc0acc..5309ba2 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -167,7 +167,7 @@ void at91_macb_hw_init(void) at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ -#if defined(CONFIG_AT91SAM9260EK) +#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260) /* * use PA10, PA11 for ETX2, ETX3. * PA23 and PA24 are for TWI EEPROM -- 1.6.3.1

1 1

[U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code
by Kim, Heung Jun 29 May '09

29 May '09

The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved to cpu/arm_cortexa8/omap3/cache.c. Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> --- cpu/arm_cortexa8/cpu.c | 65 +-------------------- cpu/arm_cortexa8/omap3/Makefile | 2 +- cpu/arm_cortexa8/omap3/board.c | 4 +- cpu/arm_cortexa8/omap3/cache.c | 99 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-omap3/sys_proto.h | 2 + 5 files changed, 107 insertions(+), 65 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache.c diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 3e1780b..209bbd0 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #ifndef CONFIG_L2_OFF -void l2cache_disable(void); +void l2_cache_disable(void); #endif static void cache_flush(void); @@ -80,7 +80,7 @@ int cleanup_before_linux(void) #ifndef CONFIG_L2_OFF /* turn off L2 cache */ - l2cache_disable(); + l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif @@ -89,71 +89,12 @@ int cleanup_before_linux(void) asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF - l2cache_enable(); + l2_cache_enable(); #endif return 0; } -void l2cache_enable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - -} - -void l2cache_disable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index b96b3dd..f83036b 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o -COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o +COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 51d5cf6..26cb436 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -206,9 +206,9 @@ void s_init(void) #endif #ifdef CONFIG_L2_OFF - l2cache_disable(); + l2_cache_disable(); #else - l2cache_enable(); + l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c new file mode 100644 index 0000000..d195046 --- /dev/null +++ b/cpu/arm_cortexa8/omap3/cache.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2009 + * Samsung Electornics, HeungJun Kim <riverful.kim(a)samsung.com> + * + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * L2 cache specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/sys_proto.h> + +void l2_cache_enable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void l2_cache_disable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } +} + diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 7361d08..4f43aef 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -63,5 +63,7 @@ void make_cs1_contiguous(void); void omap_nand_switch_ecc(int); void power_init_r(void); void dieid_num_r(void); +void l2_cache_disable(); +void l2_cache_enable(); #endif -- 1.5.6.3

2 1

[U-Boot] [PATCH] Blackfin: spi: fix pin handling of SPI0 SSEL4
by Mike Frysinger 29 May '09

29 May '09

CS4 on SPI0 has a dedicated PH8 pin which needs to be enabled as a peripheral in order to work. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/spi/bfin_spi.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index bc255cc..2a72f99 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -156,7 +156,7 @@ static void spi_portmux(struct spi_slave *slave) case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break; case 2: /* see G above */ g_fer |= PG15; break; case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break; - case 4: /* no muxing */ break; + case 4: /* no muxing */ h_fer |= PH8; break; case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break; case 6: /* no muxing */ break; case 7: /* no muxing */ break; -- 1.6.3.1

1 0

[U-Boot] [PATCH] Blackfin: fix if() logic in bootrom evt1 check
by Mike Frysinger 29 May '09

29 May '09

A missing set of parenthesis caused the silicon revision to apply only to the BF533 and not the BF531/BF532 variants. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- include/asm-blackfin/blackfin-config-pre.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h index a3db362..44f9c2f 100644 --- a/include/asm-blackfin/blackfin-config-pre.h +++ b/include/asm-blackfin/blackfin-config-pre.h @@ -55,7 +55,7 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) #endif /* Most bootroms allow for EVT1 redirection */ -#if (defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) \ +#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \ && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__) # undef CONFIG_BFIN_BOOTROM_USES_EVT1 #else -- 1.6.3.1

1 0