May 2009 - U-Boot

[U-Boot] [PATCH] ARM DaVinci: Adding new Header file
by s-paulraj＠ti.com 03 Jun '09

03 Jun '09

Patch moves the device init functions to new header file devices.h. This will enable us to use the MACROS in hardware.h in the config files for the various DaVinci SOC's Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- board/davinci/dm355evm/dm355evm.c | 1 + board/davinci/dvevm/dvevm.c | 1 + board/davinci/schmoogie/schmoogie.c | 1 + board/davinci/sffsdr/sffsdr.c | 1 + board/davinci/sonata/sonata.c | 1 + cpu/arm926ejs/davinci/cpu.c | 2 +- cpu/arm926ejs/davinci/dm355.c | 2 +- cpu/arm926ejs/davinci/dm644x.c | 2 +- cpu/arm926ejs/davinci/psc.c | 1 + drivers/i2c/davinci_i2c.c | 1 + include/asm-arm/arch-davinci/devices.h | 45 ++++++++++++++++++++++++++++++ include/asm-arm/arch-davinci/emac_defs.h | 2 +- include/asm-arm/arch-davinci/emif_defs.h | 1 + include/asm-arm/arch-davinci/hardware.h | 14 --------- 14 files changed, 57 insertions(+), 18 deletions(-) create mode 100644 include/asm-arm/arch-davinci/devices.h diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c index 398f527..1b98136 100644 --- a/board/davinci/dm355evm/dm355evm.c +++ b/board/davinci/dm355evm/dm355evm.c @@ -22,6 +22,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/nand_defs.h> +#include <asm/arch/devices.h> #include "../common/misc.h" diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index 8f38633..2cc9f3e 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -27,6 +27,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> +#include <asm/arch/devices.h> #include "../common/misc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 6e0f591..cee2c7b 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -27,6 +27,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> +#include <asm/arch/devices.h> #include "../common/misc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index 7f4ee36..deb8cb1 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -30,6 +30,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> +#include <asm/arch/devices.h> #include "../common/misc.h" #define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index a0bea05..56f5f37 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -26,6 +26,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/devices.h> #include "../common/misc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c index 29aead6..c30a44e 100644 --- a/cpu/arm926ejs/davinci/cpu.c +++ b/cpu/arm926ejs/davinci/cpu.c @@ -22,7 +22,7 @@ #include <common.h> #include <asm/arch/hardware.h> - +#include <asm/arch/devices.h> /* offsets from PLL controller base */ #define PLLC_PLLCTL 0x100 diff --git a/cpu/arm926ejs/davinci/dm355.c b/cpu/arm926ejs/davinci/dm355.c index bc45b67..346831b 100644 --- a/cpu/arm926ejs/davinci/dm355.c +++ b/cpu/arm926ejs/davinci/dm355.c @@ -23,7 +23,7 @@ #include <common.h> #include <asm/arch/hardware.h> - +#include <asm/arch/devices.h> void davinci_enable_uart0(void) { diff --git a/cpu/arm926ejs/davinci/dm644x.c b/cpu/arm926ejs/davinci/dm644x.c index bb105b5..cee0511 100644 --- a/cpu/arm926ejs/davinci/dm644x.c +++ b/cpu/arm926ejs/davinci/dm644x.c @@ -25,7 +25,7 @@ #include <common.h> #include <asm/arch/hardware.h> - +#include <asm/arch/devices.h> #define PINMUX0_EMACEN (1 << 31) #define PINMUX0_AECS5 (1 << 11) diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c index 5bb972f..967ebc9 100644 --- a/cpu/arm926ejs/davinci/psc.c +++ b/cpu/arm926ejs/davinci/psc.c @@ -25,6 +25,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/devices.h> /* * The PSC manages three inputs to a "module" which may be a peripheral or diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index eee1cbd..ba489a4 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -27,6 +27,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> +#include <asm/arch/devices.h> #include <asm/arch/i2c_defs.h> #define CHECK_NACK() \ diff --git a/include/asm-arm/arch-davinci/devices.h b/include/asm-arm/arch-davinci/devices.h new file mode 100644 index 0000000..fd7f6d0 --- /dev/null +++ b/include/asm-arm/arch-davinci/devices.h @@ -0,0 +1,45 @@ +/* + * + * Copyright (C) 2009 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_DEVICES_H +#define __ASM_ARCH_DEVICES_H + +#include <asm/sizes.h> + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +void lpsc_on(unsigned int id); +void dsp_on(void); + +void davinci_enable_uart0(void); +void davinci_enable_emac(void); +void davinci_enable_i2c(void); +void davinci_errata_workarounds(void); + +#endif /* __ASM_ARCH_DEVICES_H */ diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h index c11161f..4a5e79d 100644 --- a/include/asm-arm/arch-davinci/emac_defs.h +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -37,7 +37,7 @@ #define _DM644X_EMAC_H_ #include <asm/arch/hardware.h> - +#include <asm/arch/devices.h> #define EMAC_BASE_ADDR (0x01c80000) #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) #define EMAC_WRAPPER_RAM_ADDR (0x01c82000) diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index 646fc77..53e84f6 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -23,6 +23,7 @@ #define _EMIF_DEFS_H_ #include <asm/arch/hardware.h> +#include <asm/arch/devices.h> typedef struct { dv_reg ERCSR; diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index 313b3f3..0a685a7 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -36,12 +36,6 @@ #include <config.h> #include <asm/sizes.h> -#define REG(addr) (*(volatile unsigned int *)(addr)) -#define REG_P(addr) ((volatile unsigned int *)(addr)) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int * dv_reg_p; - /* * Base register addresses * @@ -153,14 +147,6 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_LPSC_GEM 39 #define DAVINCI_LPSC_IMCOP 40 -void lpsc_on(unsigned int id); -void dsp_on(void); - -void davinci_enable_uart0(void); -void davinci_enable_emac(void); -void davinci_enable_i2c(void); -void davinci_errata_workarounds(void); - /* Some PSC defines */ #define PSC_CHP_SHRTSW (0x01c40038) #define PSC_GBLCTL (0x01c41010) -- 1.6.0.4

2 1

[U-Boot] [PATCH] mmc: Fix decoding of SCR & function switch data on little-endian machines
by Yauhen Kharuzhy 03 Jun '09

03 Jun '09

SCR & switch data are read from card as big-endian words and should be converted to CPU byte order. Signed-off-by: Yauhen Kharuzhy <jekhor(a)gmail.com> --- drivers/mmc/mmc.c | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b4814d2..596e052 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -487,8 +487,8 @@ retry_scr: return err; } - mmc->scr[0] = scr[0]; - mmc->scr[1] = scr[1]; + mmc->scr[0] = __be32_to_cpu(scr[0]); + mmc->scr[1] = __be32_to_cpu(scr[1]); switch ((mmc->scr[0] >> 24) & 0xf) { case 0: @@ -518,7 +518,7 @@ retry_scr: return err; /* The high-speed function is busy. Try again */ - if (!switch_status[7] & SD_HIGHSPEED_BUSY) + if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) break; } @@ -526,7 +526,7 @@ retry_scr: mmc->card_caps |= MMC_MODE_4BIT; /* If high-speed isn't supported, we return */ - if (!(switch_status[3] & SD_HIGHSPEED_SUPPORTED)) + if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) return 0; err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)&switch_status); @@ -534,8 +534,10 @@ retry_scr: if (err) return err; - if ((switch_status[4] & 0x0f000000) == 0x01000000) + if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) { mmc->card_caps |= MMC_MODE_HS; + printf("Switched to HS mode\n"); + } return 0; } -- 1.6.2.3

3 2

[U-Boot] [PATCH] mmc: Remove return from mmc_init for non SD 2.0 compatible cards.
by Yauhen Kharuzhy 03 Jun '09

03 Jun '09

Cards which are not compatible with SD 2.0 standard, cat return response for CMD8 command, but it will be invalid in terms of SD 2.0. We should accept this case as admissible. Signed-off-by: Yauhen Kharuzhy <jekhor(a)gmail.com> --- drivers/mmc/mmc.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 596e052..b284030 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -870,10 +870,6 @@ int mmc_init(struct mmc *mmc) /* Test for SD version 2 */ err = mmc_send_if_cond(mmc); - /* If we got an error other than timeout, we bail */ - if (err && err != TIMEOUT) - return err; - /* Now try to get the SD card's operating condition */ err = sd_send_op_cond(mmc); -- 1.6.2.4

2 3

[U-Boot] [PATCH 0/8] hwconfig and some its users (was: Re: [PATCH 2/6] Add FSL "Can use" framework)
by Anton Vorontsov 03 Jun '09

03 Jun '09

On Thu, Feb 19, 2009 at 08:56:50PM +0100, Wolfgang Denk wrote: > Dear Anton Vorontsov, > > In message <20090219154545.GB26618(a)oksana.dev.rtsoft.ru> you wrote: > > So far it's used for specifying whether we want to use FSL DR USB or > > FSL eSDHC devices on MPC837X processors. > > > > There are two more candidates for future use: > > 1. USB ULPI PHY vs. TSEC1 on MPC8315E-RDB boards; > > 2. Marvell vs. Vitesse PHYs on MPC8313E-RDB boards. > > If you know that might need to be extended, than better plan for it > right from the beginning. OK. Done. > > diff --git a/board/freescale/common/fsl_can_use.c b/board/freescale/common/fsl_can_use.c > > new file mode 100644 > > index 0000000..17cc20f > > --- /dev/null > > +++ b/board/freescale/common/fsl_can_use.c > > That's a very strange name for a function, IMHO. I would expect that > it has something to do with using a CAN controller... > > > +int __fsl_can_use_dr_usb(void) > > If you plan to make this extendable, please use a more generic name. > For example: fsl_hwconfig() [note that leading __ is reserved]. > > > + const char *usb_or_esdhc = getenv("usb_or_esdhc"); > > Please make it extendable, use a more generic name for one (and only > one) environment variable. It makes littel sense to pollyte the > envrionment with N additional variables. For example, call it > "hwconfig". Allow that this variable holds a list of config settings, > separated for example by comma or colon or ... > > > + if (!usb_or_esdhc || !strcmp(usb_or_esdhc, "usb")) > > + return 1; > > + > > + if (!strcmp(usb_or_esdhc, "esdhc")) > > + return 0; > > This doesn't scale as well. Use a table of known strings and (static > inline) function pointers - this is much easier to extend when new > options need to get added. > > > Once we've reached this point, we might even lean back and think which > part of this is FSL specific. None, tight? So make this a generic > feature and look around which other code can be replaced by it. > > We can probably define both the content of option name / handler > function pointer table and the respective handler functions in a board > specific file - eventually even the board config file. > > That would make for a flexible solution. Here it is, patches on the way. It's very simple. Just an environment variable, but it should be enough to do what we need currently. I should write some documentation though. Thanksб -- Anton Vorontsov email: cbouatmailru(a)gmail.com irc://irc.freenode.net/bd2

4 16

[U-Boot] [PATCH] 85xx: Fix the wrong SYS_CLK_IN for 8569MDS
by Dave Liu 02 Jun '09

02 Jun '09

The SYS_CLK_IN of MPC8569MDS is 66.66MHz, The DDR_CLK_IN is same with SYS_CLK_IN in 8569 processor. so, change the SYS_CLK_IN from 66MHz to 66.66MHz. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/configs/MPC8569MDS.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 7fd2b56..c501b17 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -55,8 +55,8 @@ extern unsigned long get_clock_freq(void); #endif /* Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_DDR_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ /* * These can be toggled for performance analysis, otherwise use default. -- 1.5.4

3 2

[U-Boot] [PATCH] 85xx: Fix the wrong BCSR address of 8569MDS
by Dave Liu 02 Jun '09

02 Jun '09

The BCSR17[7] = 1 will unlock the write protect of FLASH. The WP# pin only controls the write protect of top/bottom sector, That is why we can save env, but we can't write the first sector before the patch. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- board/freescale/mpc8569mds/bcsr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index 5adffc2..f462597 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -27,7 +27,7 @@ void enable_8569mds_flash_write() { - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR17_FLASH_nWP); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); } void disable_8569mds_flash_write() -- 1.5.4

2 1

[U-Boot] PATCH: bugfix for reading maximum TLB size on mpc85xx
by Fredrik Arnerup 02 Jun '09

02 Jun '09

The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits. This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum (256 MB) which made u-boot hang in board_init_f() when trying to create a new stack in RAM. I have an mpc8540 with one 1GB dimm. Signed-off-by: Fredrik Arnerup <fredrik.arnerup(a)edgeware.tv> --- ../tmp/u-boot-2009.03/cpu/mpc85xx/tlb.c 2009-03-21 22:04:41.000000000 +0100 +++ cpu/mpc85xx/tlb.c 2009-05-14 19:26:17.000000000 +0200 @@ -134,7 +134,7 @@ unsigned int tlb_size; unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; - unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff; + unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20; size = min(memsize, CONFIG_MAX_MEM_MAPPED);

3 2

[U-Boot] [PATCH] 85xx: Add P2020DS support
by Kumar Gala 02 Jun '09

02 Jun '09

From: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> The patch adds support for P2020DS reference platform. DDR3 interface uses hard-coded initialization rather than SPD for now and was tested at 667Mhz. Some PIXIS register definitions and associated code sections need to be fixed. TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all tested under u-boot. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- MAKEALL | 2 + Makefile | 9 + board/freescale/p2020ds/Makefile | 54 +++ board/freescale/p2020ds/config.mk | 32 ++ board/freescale/p2020ds/ddr.c | 130 +++++++ board/freescale/p2020ds/law.c | 42 ++ board/freescale/p2020ds/p2020ds.c | 634 ++++++++++++++++++++++++++++++ board/freescale/p2020ds/tlb.c | 95 +++++ board/freescale/p2020ds/u-boot.lds | 143 +++++++ include/configs/P2020DS.h | 741 ++++++++++++++++++++++++++++++++++++ 10 files changed, 1882 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p2020ds/Makefile create mode 100644 board/freescale/p2020ds/config.mk create mode 100644 board/freescale/p2020ds/ddr.c create mode 100644 board/freescale/p2020ds/law.c create mode 100644 board/freescale/p2020ds/p2020ds.c create mode 100644 board/freescale/p2020ds/tlb.c create mode 100644 board/freescale/p2020ds/u-boot.lds create mode 100644 include/configs/P2020DS.h diff --git a/MAKEALL b/MAKEALL index 854f303..85558e8 100755 --- a/MAKEALL +++ b/MAKEALL @@ -379,6 +379,8 @@ LIST_85xx=" \ MPC8569MDS \ MPC8572DS \ MPC8572DS_36BIT \ + P2020DS \ + P2020DS_36BIT \ PM854 \ PM856 \ sbc8540 \ diff --git a/Makefile b/Makefile index f857641..38d98a6 100644 --- a/Makefile +++ b/Makefile @@ -2453,6 +2453,15 @@ MPC8572DS_config: unconfig fi @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale +P2020DS_36BIT_config \ +P2020DS_config: unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _36BIT_,$@)" ] ; then \ + echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ + $(XECHO) "... enabling 36-bit physical addressing." ; \ + fi + @$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale + PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile new file mode 100644 index 0000000..41032ac --- /dev/null +++ b/board/freescale/p2020ds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p2020ds/config.mk b/board/freescale/p2020ds/config.mk new file mode 100644 index 0000000..18bdc86 --- /dev/null +++ b/board/freescale/p2020ds/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# p2020ds board +# +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_P2020=1 diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c new file mode 100644 index 0000000..b9c0cb2 --- /dev/null +++ b/board/freescale/p2020ds/ddr.c @@ -0,0 +1,130 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ + + +/* XXX: these values need to be checked for all interleaving modes. */ +/* XXX: No reliable dual-rank 800 MHz setting has been found. It may + * seem reliable, but errors will appear when memory intensive + * program is run. */ +/* XXX: Single rank at 800 MHz is OK. */ +const board_specific_parameters_t board_specific_parameters[][20] = { + { + /* memory controller 0 */ + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 2, 6, 7, 3, 0}, + {334, 400, 2, 6, 9, 3, 0}, + {401, 549, 2, 6, 11, 3, 0}, + {550, 680, 2, 1, 10, 5, 0}, + {681, 850, 2, 1, 12, 5, 1}, + { 0, 333, 1, 6, 7, 3, 0}, + {334, 400, 1, 6, 9, 3, 0}, + {401, 549, 1, 6, 11, 3, 0}, + {550, 680, 1, 1, 10, 5, 0}, + {681, 850, 1, 1, 12, 5, 0} + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &(board_specific_parameters[ctrl_num][0]); + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / + sizeof(board_specific_parameters[0][0]); + u32 i; + ulong ddr_freq; + + /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i&1) { /* odd CS */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 0; + } else { /* even CS */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 4; + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + popts->cs_local_opts[i].odt_rd_cfg = 3; + popts->cs_local_opts[i].odt_wr_cfg = 3; + } + } + } + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm->n_ranks == pbsp->n_ranks) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + } + pbsp++; + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c new file mode 100644 index 0000000..da297c5 --- /dev/null +++ b/board/freescale/p2020ds/law.c @@ -0,0 +1,42 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c new file mode 100644 index 0000000..6b72d61 --- /dev/null +++ b/board/freescale/p2020ds/p2020ds.c @@ -0,0 +1,634 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <asm/mp.h> + +#include "../common/pixis.h" +#include "../common/sgmii_riser.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t fixed_sdram(void); + +int checkboard(void) +{ + puts("Board: P2020DS "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + printf("Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", + in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), + in8(PIXIS_BASE + PIXIS_PVER)); + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + +#ifdef CONFIG_SPD_EEPROM + dram_size = fsl_ddr_sdram(); +#else + dram_size = fixed_sdram(); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + dram_size, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + uint d_init; + + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; + ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL; + ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL; + ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1; + ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4; + ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5; + + if (!strcmp("performance", getenv("perf_mode"))) { + /* Performance Mode Values */ + + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF; + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; + + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF; + } else { + /* Stable Mode Values */ + + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + + /* ECC will be assumed in stable mode */ + ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; + ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; + ddr->err_sbe = CONFIG_SYS_DDR_SBE; + + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; + } + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR - 1st controller: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) + udelay(1000); + debug("DDR: memory initialized\n\n"); + asm("sync; isync"); + udelay(500); +#endif + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} + +#endif + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +int first_free_busno = 0; + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + volatile ccsr_fsl_pci_t *pci; + struct pci_controller *hose; + int pcie_ep, pcie_configured; + struct pci_region *r; +/* u32 temp32; */ + + debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + printf(" eTSEC2 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf(" eTSEC3 is in sgmii mode.\n"); + +#ifdef CONFIG_PCIE2 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; + hose = &pcie2_hose; + pcie_ep = (host_agent == 2) || (host_agent == 4) || + (host_agent == 6) || (host_agent == 0); + pcie_configured = (io_sel == 0x2) || (io_sel == 0xe); + r = hose->regions; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + printf("\n PCIE2 connected to ULI as %s (base addr %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BUS, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BUS, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno = hose->last_busno+1; + printf(" PCIE2 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + + /* + * The workaround doesn't work on p2020 because the location + * we try and read isn't valid on p2020, fix this later + */ +#if 0 + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + * Device 1d has the first on-board memory BAR. + */ + + pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0), + PCI_BASE_ADDRESS_1, &temp32); + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { + void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), + temp32, 4, 0); + debug(" uli1575 read to %p\n", p); + in_be32(p); + } +#endif + } else { + printf(" PCIE2: disabled\n"); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; + hose = &pcie3_hose; + pcie_ep = (host_agent == 0) || (host_agent == 3) || + (host_agent == 5) || (host_agent == 6); + pcie_configured = (io_sel == 0x2) || (io_sel == 0x4); + r = hose->regions; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BUS, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BUS, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno+1; + printf(" PCIE3 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + + } else { + printf(" PCIE3: disabled\n"); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif + +#ifdef CONFIG_PCIE1 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; + hose = &pcie1_hose; + pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); + pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF); + r = hose->regions; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BUS, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BUS, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + hose->first_busno = first_free_busno; + + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + + } else { + printf(" PCIE1: disabled\n"); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = 2; + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +#ifdef CONFIG_GET_CLK_FROM_ICS307 +/* decode S[0-2] to Output Divider (OD) */ +static unsigned char ics307_S_to_OD[] = { + 10, 2, 8, 4, 5, 7, 3, 6 +}; + +/* Calculate frequency being generated by ICS307-02 clock chip based upon + * the control bytes being programmed into it. */ +/* XXX: This function should probably go into a common library */ +static unsigned long +ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2) +{ + const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; + unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); + unsigned long RDW = cw2 & 0x7F; + unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; + unsigned long freq; + + /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ + + /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 + * cw1: V8 V7 V6 V5 V4 V3 V2 V1 + * cw2: V0 R6 R5 R4 R3 R2 R1 R0 + * + * R6:R0 = Reference Divider Word (RDW) + * V8:V0 = VCO Divider Word (VDW) + * S2:S0 = Output Divider Select (OD) + * F1:F0 = Function of CLK2 Output + * TTL = duty cycle + * C1:C0 = internal load capacitance for cyrstal + */ + + /* Adding 1 to get a "nicely" rounded number, but this needs + * more tweaking to get a "properly" rounded number. */ + + freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); + + debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, + freq); + return freq; +} + +unsigned long get_board_sys_clk(ulong dummy) +{ + return gd->bus_clk; +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + return gd->mem_clk; +} + +unsigned long +calculate_board_sys_clk(ulong dummy) +{ + ulong val; + val = ics307_clk_freq( + in8(PIXIS_BASE + PIXIS_VSYSCLK0), + in8(PIXIS_BASE + PIXIS_VSYSCLK1), + in8(PIXIS_BASE + PIXIS_VSYSCLK2)); + debug("sysclk val = %lu\n", val); + return val; +} + +unsigned long +calculate_board_ddr_clk(ulong dummy) +{ + ulong val; + val = ics307_clk_freq( + in8(PIXIS_BASE + PIXIS_VDDRCLK0), + in8(PIXIS_BASE + PIXIS_VDDRCLK1), + in8(PIXIS_BASE + PIXIS_VDDRCLK2)); + debug("ddrclk val = %lu\n", val); + return val; +} +#else +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x07; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + + return val; +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x38; + i >>= 3; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + return val; +} +#endif + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[4]; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_init(tsec_info, num); +#endif + + tsec_eth_init(bis, tsec_info, num); + + return 0; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); +#endif +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#endif +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#endif +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif +} +#endif + +#ifdef CONFIG_MP +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c new file mode 100644 index 0000000..b2e562a --- /dev/null +++ b/board/freescale/p2020ds/tlb.c @@ -0,0 +1,95 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), + + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2020ds/u-boot.lds b/board/freescale/p2020ds/u-boot.lds new file mode 100644 index 0000000..d6e22a7 --- /dev/null +++ b/board/freescale/p2020ds/u-boot.lds @@ -0,0 +1,143 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h new file mode 100644 index 0000000..a39ff26 --- /dev/null +++ b/include/configs/P2020DS.h @@ -0,0 +1,741 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * p2020ds board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_P2020 1 +#define CONFIG_P2020DS 1 +#define CONFIG_MP 1 /* support multiple processors */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ + +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#ifndef __ASSEMBLY__ +extern unsigned long calculate_board_sys_clk(unsigned long dummy); +extern unsigned long calculate_board_ddr_clk(unsigned long dummy); +/* extern unsigned long get_board_sys_clk(unsigned long dummy); */ +/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ +#endif +#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ +#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq + from ICS307 instead of switches */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) + +/* DDR Setup */ +#define CONFIG_SYS_DDR_TLB_START 9 +#define CONFIG_VERY_BIG_RAM +#define CONFIG_FSL_DDR3 1 +#undef CONFIG_FSL_DDR_INTERACTIVE + +// #define CONFIG_DDR_ECC /* ECC will be enabled based on perf_mode environment variable */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ + +/* These are used when DDR doesn't use SPD. */ +//#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ +#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ + +/* Default settings for "stable" mode */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330804 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 +#define CONFIG_SYS_DDR_MODE_1 0x00421422 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x61800100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 +#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ +#define CONFIG_SYS_DDR_CONTROL2 0x24400011 +#define CONFIG_SYS_DDR_CDR1 0x00040000 +#define CONFIG_SYS_DDR_CDR2 0x00000000 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00010000 + +/* Settings that differ for "performance" mode */ +#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce +#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ + +/* + * The following set of values were tested for DDR2 + * with a DDR3 to DDR2 interposer + * +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 +#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 +#define CONFIG_SYS_DDR_MODE_1 0x00480432 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x06180100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 +#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 +#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC3008000 +#define CONFIG_SYS_DDR_CONTROL2 0x04400010 + * + */ + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 + +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_PWR 0x5 /* PIXIS Power status register */ +#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VSTAT 0x11 /* VELA Status Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ +#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ +#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ +#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ +#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ +#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ +#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ + +#define PIXIS_VWATCH 0x24 /* Watchdog Register */ +#define PIXIS_LED 0x25 /* LED Register */ + +/* old pixis referenced names */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 +#define PIXIS_VSPEED2_TSEC1SER 0x8 +#define PIXIS_VSPEED2_TSEC2SER 0x4 +#define PIXIS_VSPEED2_TSEC3SER 0x2 +#define PIXIS_VSPEED2_TSEC4SER 0x1 +#define PIXIS_VCFGEN1_TSEC1SER 0x20 +#define PIXIS_VCFGEN1_TSEC2SER 0x20 +#define PIXIS_VCFGEN1_TSEC3SER 0x20 +#define PIXIS_VCFGEN1_TSEC4SER 0x20 +#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ + | PIXIS_VSPEED2_TSEC2SER \ + | PIXIS_VSPEED2_TSEC3SER \ + | PIXIS_VSPEED2_TSEC4SER) +#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ + | PIXIS_VCFGEN1_TSEC2SER \ + | PIXIS_VCFGEN1_TSEC3SER \ + | PIXIS_VCFGEN1_TSEC4SER) + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ + CONFIG_SYS_NAND_BASE + 0x40000, \ + CONFIG_SYS_NAND_BASE + 0x80000,\ + CONFIG_SYS_NAND_BASE + 0xC0000} +#define CONFIG_SYS_MAX_NAND_DEVICE 4 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#if defined(CONFIG_PCI) + +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT + +/* video */ +#define CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_CONSOLE_CURSOR*/ +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#define CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + +#ifndef CONFIG_PCI_PNP + #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS + #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE +#endif /* SCSI */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define CONFIG_PIXIS_SGMII_CMD +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1b + +#ifdef CONFIG_FSL_SGMII_RISER +#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ +#endif + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_NET +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_EXT2 +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:02:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD +#endif + +#define CONFIG_IPADDR 192.168.1.254 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "perf_mode=stable\0" \ + "memctl_intlv_ctl=2\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p2020ds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p2020ds/p2020ds.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ -- 1.5.6.6

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[U-Boot] [PATCH] 85xx: Fix the clock adjust of mpc8569mds board
by Dave Liu 02 Jun '09

02 Jun '09

Currently the clk_adj is 6 (3/4 cycle), The settings will cause the DDR controller hang at the data init. Change the clk_adj from 6 to 4 (1/2 cycle), make the memory system stable. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- board/freescale/mpc8569mds/ddr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index c4e63fb..da1e675 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -56,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, * 0110 3/4 cycle late * 0111 7/8 cycle late */ - popts->clk_adjust = 6; + popts->clk_adjust = 4; /* * Factors to consider for CPO: -- 1.5.4

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[U-Boot] [patch] Add display cpuinfo for Atmel at91sam9261 Cores
by Remy Bohmer 02 Jun '09

02 Jun '09

This patch adds support for displaying CPU type information about Atmel AT91 cores during boot. It currently only configures it for the at91sam9261ek board, but it can easily be configured for all at91 based cores. This patch also provides at91_dbgu.h which is also used by the upcoming USB CDC-ethernet and USB-gadget support for this board. Signed-off-by: Remy Böhmer <linux(a)bohmer.net> --- cpu/arm926ejs/at91/Makefile | 1 cpu/arm926ejs/at91/cpuinfo.c | 83 ++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_dbgu.h | 69 +++++++++++++++++++++++ include/asm-arm/arch-at91/cpu.h | 99 ++++++++++++++++++++++++++++++++++ include/configs/at91sam9261ek.h | 2 5 files changed, 254 insertions(+) create mode 100644 cpu/arm926ejs/at91/cpuinfo.c create mode 100644 include/asm-arm/arch-at91/at91_dbgu.h create mode 100644 include/asm-arm/arch-at91/cpu.h Index: u-boot-usb.tmp/cpu/arm926ejs/at91/Makefile =================================================================== --- u-boot-usb.tmp.orig/cpu/arm926ejs/at91/Makefile 2009-05-02 21:43:41.000000000 +0200 +++ u-boot-usb.tmp/cpu/arm926ejs/at91/Makefile 2009-05-02 22:01:46.000000000 +0200 @@ -55,6 +55,7 @@ COBJS-y += at91sam9rl_serial.o COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9rl_spi.o endif COBJS-$(CONFIG_AT91_LED) += led.o +COBJS-$(CONFIG_DISPLAY_CPUINFO) +=cpuinfo.o COBJS-y += clock.o COBJS-y += cpu.o COBJS-y += timer.o Index: u-boot-usb.tmp/cpu/arm926ejs/at91/cpuinfo.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-usb.tmp/cpu/arm926ejs/at91/cpuinfo.c 2009-05-02 22:01:46.000000000 +0200 @@ -0,0 +1,83 @@ +#include <command.h> +#include <common.h> +#include <arm926ejs.h> +#include <asm/hardware.h> +#include <asm/arch/at91_dbgu.h> +#include <asm/arch/io.h> + +int print_cpuinfo(void) +{ + unsigned long cidr; + const char *txt; + + cidr = at91_sys_read(AT91_DBGU_CIDR); + + switch ((cidr & AT91_CIDR_EPROC) >> 5) { + case 0x1: txt = "ARM946ES"; break; + case 0x2: txt = "ARM7TDMI"; break; + case 0x4: txt = "ARM920T"; break; + case 0x5: txt = "ARM926EJS"; break; + default: txt = "undefined"; break; + } + printf("Embedded Processor: %s\n", txt); + + switch ((cidr & AT91_CIDR_ARCH) >> 20) { + case 0x19: txt = "AT91SAM9xx"; break; + case 0x29: txt = "AT91SAM9XExx"; break; + case 0x34: txt = "AT91x34"; break; + case 0x37: txt = "CAP7"; break; + case 0x39: txt = "CAP9"; break; + case 0x3B: txt = "CAP11"; break; + case 0x40: txt = "AT91x40"; break; + case 0x42: txt = "AT91x42"; break; + case 0x55: txt = "AT91x55"; break; + case 0x60: txt = "AT91SAM7Axx"; break; + case 0x61: txt = "AT91SAM7AQxx"; break; + case 0x63: txt = "AT91x63"; break; + case 0x70: txt = "AT91SAM7Sxx"; break; + case 0x71: txt = "AT91SAM7XCxx"; break; + case 0x72: txt = "AT91SAM7SExx"; break; + case 0x73: txt = "AT91SAM7Lxx"; break; + case 0x75: txt = "AT91SAM7Xxx"; break; + case 0x92: txt = "AT91x92"; break; + case 0xF0: txt = "AT75Cxx"; break; + default: txt = "undefined"; break; + } + printf("Architecture: %s Series\n", txt); + + printf("CPU-revision: %c\n", (char)('A' + (cidr & AT91_CIDR_VERSION))); + + switch ((cidr & AT91_CIDR_NVPTYP) >> 28) { + case 0x0: txt = "ROM"; break; + case 0x1: txt = "ROMless or onchip flash"; break; + case 0x2: txt = "Embedded flash memory"; break; + case 0x3: txt = "ROM and Embedded flash memory"; break; + case 0x4: txt = "SRAM emulating ROM"; break; + default: txt = "undefined"; break; + } + printf("NonVolatile Program Memory type: %s\n", txt); + + switch (cidr & AT91_CIDR_SRAMSIZ) { + case AT91_CIDR_SRAMSIZ_1K: txt = "1K"; break; + case AT91_CIDR_SRAMSIZ_2K: txt = "2K"; break; + case AT91_CIDR_SRAMSIZ_112K: txt = "112K"; break; + case AT91_CIDR_SRAMSIZ_4K: txt = "4K"; break; + case AT91_CIDR_SRAMSIZ_80K: txt = "80K"; break; + case AT91_CIDR_SRAMSIZ_160K: txt = "160K"; break; + case AT91_CIDR_SRAMSIZ_8K: txt = "8K"; break; + case AT91_CIDR_SRAMSIZ_16K: txt = "16K"; break; + case AT91_CIDR_SRAMSIZ_32K: txt = "32K"; break; + case AT91_CIDR_SRAMSIZ_64K: txt = "64K"; break; + case AT91_CIDR_SRAMSIZ_128K: txt = "128K"; break; + case AT91_CIDR_SRAMSIZ_256K: txt = "256K"; break; + case AT91_CIDR_SRAMSIZ_96K: txt = "96K"; break; + case AT91_CIDR_SRAMSIZ_512K: txt = "512K"; break; + default: txt = "undefined"; break; + } + printf("Internal SRAM size: %s\n", txt); + + if (cidr & AT91_CIDR_EXT) + printf("Extension ID: 0x%x\n", at91_sys_read(AT91_DBGU_EXID)); + + return 0; +} Index: u-boot-usb.tmp/include/asm-arm/arch-at91/at91_dbgu.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-usb.tmp/include/asm-arm/arch-at91/at91_dbgu.h 2009-05-02 22:01:46.000000000 +0200 @@ -0,0 +1,69 @@ +/* + * include/asm-arm/arch-at91/at91_dbgu.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Debug Unit (DBGU) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_DBGU_H +#define AT91_DBGU_H + +#ifdef AT91_DBGU +#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ +#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ +#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable */ +#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ +#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ +#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable */ +#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask */ +#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ +#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding */ +#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding */ +#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator */ + +#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ +#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension */ +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif /* AT91_DBGU */ + +/* + * Some AT91 parts that don't have full DEBUG units still support the ID + * and extensions register. + */ +#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ +#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ +#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program + Memory Size */ +#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile + Program Memory Size */ +#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ +#define AT91_CIDR_SRAMSIZ_1K (1 << 16) +#define AT91_CIDR_SRAMSIZ_2K (2 << 16) +#define AT91_CIDR_SRAMSIZ_112K (4 << 16) +#define AT91_CIDR_SRAMSIZ_4K (5 << 16) +#define AT91_CIDR_SRAMSIZ_80K (6 << 16) +#define AT91_CIDR_SRAMSIZ_160K (7 << 16) +#define AT91_CIDR_SRAMSIZ_8K (8 << 16) +#define AT91_CIDR_SRAMSIZ_16K (9 << 16) +#define AT91_CIDR_SRAMSIZ_32K (10 << 16) +#define AT91_CIDR_SRAMSIZ_64K (11 << 16) +#define AT91_CIDR_SRAMSIZ_128K (12 << 16) +#define AT91_CIDR_SRAMSIZ_256K (13 << 16) +#define AT91_CIDR_SRAMSIZ_96K (14 << 16) +#define AT91_CIDR_SRAMSIZ_512K (15 << 16) +#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Id */ +#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program + Memory Type */ +#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ + +#endif Index: u-boot-usb.tmp/include/asm-arm/arch-at91/cpu.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-usb.tmp/include/asm-arm/arch-at91/cpu.h 2009-05-02 22:01:46.000000000 +0200 @@ -0,0 +1,99 @@ +/* + * include/asm-arm/arch-at91/cpu.h + * + * Copyright (C) 2006 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_CPU_H +#define __ASM_ARCH_CPU_H + +#include <asm/hardware.h> +#include <asm/arch/at91_dbgu.h> +#include <asm/arch/io.h> + + +#define ARCH_ID_AT91RM9200 0x09290780 +#define ARCH_ID_AT91SAM9260 0x019803a0 +#define ARCH_ID_AT91SAM9261 0x019703a0 +#define ARCH_ID_AT91SAM9263 0x019607a0 +#define ARCH_ID_AT91SAM9RL64 0x019b03a0 +#define ARCH_ID_AT91CAP9 0x039A03A0 + +#define ARCH_ID_AT91SAM9XE128 0x329973a0 +#define ARCH_ID_AT91SAM9XE256 0x329a93a0 +#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 + +#define ARCH_ID_AT91M40800 0x14080044 +#define ARCH_ID_AT91R40807 0x44080746 +#define ARCH_ID_AT91M40807 0x14080745 +#define ARCH_ID_AT91R40008 0x44000840 + +static inline unsigned long at91_cpu_identify(void) +{ + return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); +} + + +#define ARCH_FAMILY_AT91X92 0x09200000 +#define ARCH_FAMILY_AT91SAM9 0x01900000 +#define ARCH_FAMILY_AT91SAM9XE 0x02900000 + +static inline unsigned long at91_arch_identify(void) +{ + return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); +} + + +#ifdef CONFIG_AT91RM9200 +/* no actual detection for this architecture */ +#define cpu_is_at91rm9200() (1) +#else +#define cpu_is_at91rm9200() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) +#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) \ + || cpu_is_at91sam9xe()) +#else +#define cpu_is_at91sam9xe() (0) +#define cpu_is_at91sam9260() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) +#else +#define cpu_is_at91sam9261() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) +#else +#define cpu_is_at91sam9263() (0) +#endif + +#ifdef CONFIG_AT91SAM9RL +#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#else +#define cpu_is_at91sam9rl() (0) +#endif + +#ifdef CONFIG_AT91CAP9 +#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) +#else +#define cpu_is_at91cap9() (0) +#endif + +/* + * Since this is ARM, we will never run on any AVR32 CPU. But these + * definitions may reduce clutter in common drivers. + */ +#define cpu_is_at32ap7000() (0) + +#endif Index: u-boot-usb.tmp/include/configs/at91sam9261ek.h =================================================================== --- u-boot-usb.tmp.orig/include/configs/at91sam9261ek.h 2009-05-02 21:48:36.000000000 +0200 +++ u-boot-usb.tmp/include/configs/at91sam9261ek.h 2009-05-02 22:01:46.000000000 +0200 @@ -45,6 +45,8 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_DISPLAY_CPUINFO 1 + /* * Hardware drivers */ --

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