May 2009 - U-Boot

[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.
by Kim, Heung Jun 28 May '09

28 May '09

The cpu.c under cpu/arm_cortexa8 has a dependency of omap3. The part of cache in cpu.c is moved in the omap3/board.c, because the functions about controlling cache seems to be different with a lot of processors. Signed-off-by: root <root(a)riverbuntu.(none)> --- cpu/arm_cortexa8/cpu.c | 55 +------------------------ cpu/arm_cortexa8/omap3/board.c | 68 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-omap3/sys_proto.h | 3 + 3 files changed, 74 insertions(+), 52 deletions(-) diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 3e1780b..046a89e 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -97,64 +97,15 @@ int cleanup_before_linux(void) void l2cache_enable() { - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - + board_l2cache_enable(); } void l2cache_disable() { - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } + board_l2cache_disable(); } static void cache_flush(void) { - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + board_cache_flush(); } diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 51d5cf6..a594fc9 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -52,6 +52,74 @@ static inline void delay(unsigned long loops) } /****************************************************************************** + * Routine: board_l2cache_enable() / disable() / flush() + * Description: cache enable / disable / flush + *****************************************************************************/ +void board_l2cache_enable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void board_l2cache_disable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2" : "=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : "=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12" : "=r"(j)); + __asm__ __volatile__("mov %0, r0" : "=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0" : "=r"(i)); + __asm__ __volatile__("mov r12, %0" : "=r"(j)); + } +} + +void board_cache_flush(void) +{ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); +} + +/****************************************************************************** * Routine: secure_unlock * Description: Setup security registers for access * (GP Device only) diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 7361d08..06a0d8a 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -63,5 +63,8 @@ void make_cs1_contiguous(void); void omap_nand_switch_ecc(int); void power_init_r(void); void dieid_num_r(void); +void board_l2cache_enable(); +void board_l2cache_disable(); +void board_cache_flush(); #endif -- 1.5.6.3

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[U-Boot] Net: UEC: Question about (R)TBI interface initialization in u-boot.
by Richard Retanubun 28 May '09

28 May '09

Hello, I am working on an 8360e platform, bringing up a RTBI interface on UCC1 connected as a FIXED_PHY_PORT (smi addr 8) to a switch chip port. Question 1a =========== In uec.c::uec_startup, there is this logic if (enet_interface == ENET_1000_TBI || enet_interface == ENET_1000_RTBI) { utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT; } else { utbipar |= (0x10 + uec_info->uf_info.ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT; } With UCC1 (devnum = 0) I am hitting a bug here I think, because I am using UCC1 (devnum 0) my utbipar is set to (8+0) which is the same as my fixed-port phy. The tbi controller (see section 30.11.7 on the 8360 reference manual) returns 0x0000 on its ID registers (register offset 2 and 3). This prevents the fixed-phy-port detection to finish and I got detected as a generic MII instead. If the intent here is to make utibipar and the actual phy address different, can the logic be: utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num + 1) << UTBIPAR_PHY_ADDRESS_SHIFT; to handle the case when ucc_num = 0 -----------------------------^ Question 1b =========== on the else cause, when the interface is NOT (R)TBI, why is utbipar set at 0x10 offset from the UCC_num ? Since the tbi controller is internal per UEC and responds in-precedent to any external PHY, keeping it at 0x1F (the default) will make sure it stays out of everyone's way and not impose additional PHY address selection restrictions (other than NOT being 0x1F) on the HW design, no? Question 2 ========== I got my RTBI interface working after modifying the TBICON register to match our hardware, now I am looking for a way to add support for it. Is this a good approach?: in uccf.h, make: ================================= typedef struct ucc_tbireg { unsigned short cr, unsigned short sr, ... } ucc_tbireg_t; ================================= then add it as a member for typedef struct uec_info in uec.h ================================= then fill it in during the initialization of the static UEC instantiation: static uec_info_t eth2_uec_info = { #if (CONFIG_SYS_UEC2_INTERFACE_MODE == ENET_1000_RTBI) || (CONFIG_SYS_UEC2_INTERFACE_MODE == ENET_1000_TBI) .tbi_info = { .cr = CONFIG_SYS_UEC2_TBI_CR, .ana = CONFIG_SYS_UEC2_TBI_ANA, .... }, #endif ================================= Then process it during uec_startup, with values of "0x0" meaning do-not-modify (we can even add bitmasks to mpc83xx.h a'la DDRCDR or so). ================================= If any of these have a hope of being mainlined, I can work out a patch (I can only test for RTBI though, since that is the only connection I got) but the TBI registers should apply regardless. Thanks very much for everyone's time! - Richard.

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[U-Boot] [RFC] initcall mechanism introduction
by Jean-Christophe PLAGNIOL-VILLARD 27 May '09

27 May '09

Hi all, Linux Kernel has for a long time a well-optimized mechanism for for calling initiallisation code. Import the the same functionnality to U-Boot. Evenif it will increase a few U-Boot (999 bytes) as show in PATCH 3/3 if we convert the NET_MULTI it will decrease of 2212 bytes at the end Best Regards, J.

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[U-Boot] itoa(), base of 16
by Drasko DRASKOVIC 27 May '09

27 May '09

Hi all, how do we use itoa() fnc in U-Boot? I can seem to find it (there is simple_strtoul(), but I need inverse of this). BR, Drasko

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[U-Boot] [U-BOOT] nand merge problem
by xiangfu_gmail 27 May '09

27 May '09

Hi I have try to merge Ingenic U-boot (1.1.6) with upstream. but I have some problem 1. there is no -- NAND_CTL_SETNCE: NAND_CTL_CLRNCE: NAND_CTL_SETCLE: NAND_CTL_CLRCLE: NAND_CTL_SETALE: NAND_CTL_CLRALE: instead of : -- NAND_NCE: NAND_CLE: NAND_ALE: NAND_CTRL_CLE: NAND_CTRL_ALE: NAND_CTRL_CHANGE: I use the NAND_CTL_SETNCE... in the jz_hwcontrol function. i use "nand->hwcontrol = jz_hwcontrol" in the u-boot 1.1.6 but in the U-boot V2009-06 the nand_chip structure does not have "hwcontrol" function. what am I gonna do? thanks for help. -- Best Regards Xiangfu Liu jabber : xiangfu.z(a)gmail.com skype : xiangfu.z Please avoid sending me Word or PowerPoint attachments. See http://www.gnu.org/philosophy/no-word-attachments.html

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[U-Boot] Problem with u-boot debugging
by mouse1 27 May '09

27 May '09

Hi! I would like to port the U-Boot to a custom developed port with an Au1200 chip. I'm using the ELDK as toolchain. I successfully compiled the U-Boot. I'm trying to debug it with a BDI-3000, through GDB. But anywhere I put a breakpoint (e.g. to the board_init_f), the program stops at line 234 in the start.s: mtc0 zero, CP0_WATCHLO, and it writes out: Program received signal SIGABRT, Aborted. reset () at start.S:234 234 mtc0 zero, CP0_WATCHLO After I continue program running, the BDI writes out: *** TARGET: all hardware breakpoints in use and the gdb: (gdb) c Continuing. Warning: Cannot insert breakpoint 2. Error accessing memory address 0xbfc01030: Unknown error 4294967295. Contrarily, I can use the BDI's TI command, so from terminal, I can single step the program. Any idea? Here's the full gdb output: (gdb) target remote bdi:2001 Remote debugging using bdi:2001 _start () at start.S:64 64 RVECENT(reset,0) /* U-boot entry point */ (gdb) b board_init_f Note: breakpoint 2 also set at pc 0xbfc01030. Breakpoint 3 at 0xbfc01030: file board.c, line 202. (gdb) c Continuing. Program received signal SIGABRT, Aborted. reset () at start.S:234 234 mtc0 zero, CP0_WATCHLO (gdb) c Continuing. Warning: Cannot insert breakpoint -5. Error accessing memory address 0xbfc00000: Ismeretlen hiba 4294967295.

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[U-Boot] [PATCH] ppc4xx: Remove PCI async bootup message if PCI is not used
by Stefan Roese 27 May '09

27 May '09

Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 9a6a8d7..06f44ad 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -597,7 +597,7 @@ int checkcpu (void) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif -#if defined(PCI_ASYNC) +#if defined(CONFIG_PCI) && defined(PCI_ASYNC) if (pci_async_enabled()) { printf (", PCI async ext clock used"); } else { -- 1.6.2.5

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27 May '09

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[U-Boot] Axiom MCF5282 help
by Mark Giacobbe 27 May '09

27 May '09

Hi All - I'm new to u-boot and I am running into some issues. I an using the Axiom 5282lite board and I cannot get the ethernet working. I have u-boot flashed onto the board, and when I connect the board to my Linksys WRT54G router, the Link LED on the board constantly flashes, as does the LED for that port on the router. I assigned an IP to the board, outside the DHCP range, but I cannot ping the board, and the board cannot ping anything, including the router. Any ideas? Speaking of DHCP, does the code support DHCP for the 5282? Any help you be appreciated. Thanks Mark

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[U-Boot] Important Proposal
by Mr. Song Lile 27 May '09

27 May '09

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