November 2009 - U-Boot

[U-Boot] Cute Kid of the Year - enter to win $25,000
by TheCuteKid＠iammyownboss.co.uk 14 Nov '09

14 Nov '09

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[U-Boot] [PATCH] Initial support for Orion5x SoC and EDMini board
by Albert Aribaud 14 Nov '09

14 Nov '09

This patch adds initial u-boot support for the Marvell orion5x SoC and the LAcie ED Mini V2 board--support is limited to serial, flash and environment. Further support will be added as devices common with kirkwood are made useable across SoCs. Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- Makefile | 3 + board/Marvell/edminiv2/Makefile | 51 +++++ board/Marvell/edminiv2/config.mk | 25 +++ board/Marvell/edminiv2/edminiv2.c | 165 ++++++++++++++++ board/Marvell/edminiv2/edminiv2.h | 39 ++++ cpu/arm926ejs/orion5x/Makefile | 52 +++++ cpu/arm926ejs/orion5x/cpu.c | 339 ++++++++++++++++++++++++++++++++ cpu/arm926ejs/orion5x/dram.c | 61 ++++++ cpu/arm926ejs/orion5x/mpp.c | 88 ++++++++ cpu/arm926ejs/orion5x/timer.c | 171 ++++++++++++++++ drivers/serial/serial.c | 3 + include/asm-arm/arch-orion5x/88f5182.h | 40 ++++ include/asm-arm/arch-orion5x/cpu.h | 213 ++++++++++++++++++++ include/asm-arm/arch-orion5x/gpio.h | 53 +++++ include/asm-arm/arch-orion5x/mpp.h | 122 ++++++++++++ include/asm-arm/arch-orion5x/orion5x.h | 67 +++++++ include/configs/edminiv2.h | 158 +++++++++++++++ 17 files changed, 1650 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/edminiv2/Makefile create mode 100644 board/Marvell/edminiv2/config.mk create mode 100644 board/Marvell/edminiv2/edminiv2.c create mode 100644 board/Marvell/edminiv2/edminiv2.h create mode 100644 cpu/arm926ejs/orion5x/Makefile create mode 100644 cpu/arm926ejs/orion5x/cpu.c create mode 100644 cpu/arm926ejs/orion5x/dram.c create mode 100644 cpu/arm926ejs/orion5x/mpp.c create mode 100644 cpu/arm926ejs/orion5x/timer.c create mode 100644 include/asm-arm/arch-orion5x/88f5182.h create mode 100644 include/asm-arm/arch-orion5x/cpu.h create mode 100644 include/asm-arm/arch-orion5x/gpio.h create mode 100644 include/asm-arm/arch-orion5x/mpp.h create mode 100644 include/asm-arm/arch-orion5x/orion5x.h create mode 100644 include/configs/edminiv2.h diff --git a/Makefile b/Makefile index bcb3fe9..60f9140 100644 --- a/Makefile +++ b/Makefile @@ -2951,6 +2951,9 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci +edminiv2_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell orion5x + imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 diff --git a/board/Marvell/edminiv2/Makefile b/board/Marvell/edminiv2/Makefile new file mode 100644 index 0000000..2e6d305 --- /dev/null +++ b/board/Marvell/edminiv2/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := edminiv2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/edminiv2/config.mk b/board/Marvell/edminiv2/config.mk new file mode 100644 index 0000000..a4ea769 --- /dev/null +++ b/board/Marvell/edminiv2/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00600000 diff --git a/board/Marvell/edminiv2/edminiv2.c b/board/Marvell/edminiv2/edminiv2.c new file mode 100644 index 0000000..f23de0e --- /dev/null +++ b/board/Marvell/edminiv2/edminiv2.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/orion5x.h> +#include <asm/arch/mpp.h> +#include "edminiv2.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_FLASH_CFI_LEGACY) +#include <flash.h> +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; + int sect; + + if (base != CONFIG_SYS_FLASH_BASE) + return 0; + + info->size = 0; + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + for (sect=0; sect<CONFIG_SYS_MAX_FLASH_SECT; sect++) { + info->start[sect] = base+info->size; + info->size += sectsz[sect]; + } + info->flash_id = 0x01000000; + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->buffer_size = 32; + info->erase_blk_tout = 16384; + info->write_tout = 2; + info->buffer_write_tout = 5; + info->vendor = CFI_CMDSET_AMD_LEGACY; + info->cmd_reset= 0xF0; + info->interface= FLASH_CFI_X8; + info->legacy_unlock = 0; + info->manufacturer_id = 0xC2; + info->device_id = 0xBA; + info->device_id2= 0; + + info->ext_addr = 0; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0000; + info->addr_unlock1 = 0x00000555; + info->addr_unlock2 = 0x000002AA; + info->name = "MX29LV400CB"; + + return 1; +} +#endif /* CONFIG_SYS_FLASH_CFI */ + +int board_init(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + orion5x_config_gpio(EDMINIV2_OE_VAL_LOW, EDMINIV2_OE_LOW); + + /* Multi-Purpose Pins Functionality configuration */ + u32 edminiv2_mpp_config[] = { + MPP0_GPIO, + MPP1_GPIO, + MPP2_GPIO, + MPP3_GPIO, + MPP4_GPIO, + MPP5_GPIO, + MPP6_GPIO, + MPP7_GPIO, + MPP8_GPIO, + MPP9_GPIO, + MPP10_GPIO, + MPP11_GPIO, + MPP12_SATA0_PRESENTn, + MPP13_SATA1_PRESENTn, + MPP14_SATA0_ACTn, + MPP15_SATA1_ACTn, + MPP16_GPIO, + MPP17_GPIO, + MPP18_GPIO, + MPP19_GPIO, + 0 + }; + orion5x_mpp_conf(edminiv2_mpp_config); + + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = orion5x_sdram_bar(0) + 0x100; + + return 0; +} + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); + gd->bd->bi_dram[i].size = orion5x_sdram_bs(i); + } + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/edminiv2/edminiv2.h b/board/Marvell/edminiv2/edminiv2.h new file mode 100644 index 0000000..77a108e --- /dev/null +++ b/board/Marvell/edminiv2/edminiv2.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __EDMINIV2_H +#define __EDMINIV2_H + +#define EDMINIV2_OE_LOW (~(0)) +#define EDMINIV2_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __EDMINIV2_H */ diff --git a/cpu/arm926ejs/orion5x/Makefile b/cpu/arm926ejs/orion5x/Makefile new file mode 100644 index 0000000..4b506a7 --- /dev/null +++ b/cpu/arm926ejs/orion5x/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2009 Albert ARIBAUD <albrt.aribaud(a)free.fr> +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = dram.o +COBJS-y += cpu.o +COBJS-y += mpp.o +COBJS-y += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/orion5x/cpu.c b/cpu/arm926ejs/orion5x/cpu.c new file mode 100644 index 0000000..50ca724 --- /dev/null +++ b/cpu/arm926ejs/orion5x/cpu.c @@ -0,0 +1,339 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/cache.h> +#include <u-boot/md5.h> +#include <asm/arch/orion5x.h> +#include <hush.h> + +#define BUFLEN 16 + +void reset_cpu(unsigned long ignored) +{ + struct orion5x_cpu_registers *cpureg = + (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; + + writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + &cpureg->rstoutn_mask); + writel(readl(&cpureg->sys_soft_rst) | 1, + &cpureg->sys_soft_rst); + while (1) ; +} + +/* + * Window Size + * Used with the Base register to set the address window size and location. + * Must be programmed from LSB to MSB as sequence of ones followed by + * sequence of zeros. The number of ones specifies the size of the window in + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). + * NOTE: A value of 0x0 specifies 64-KByte size. + */ +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) +{ + int i; + unsigned int j = 0; + u32 val = sizeval >> 1; + + for (i = 0; val > 0x10000; i++) { + j |= (1 << i); + val = val >> 1; + } + return (0x0000ffff & j); +} + +/* + * orion5x_config_adr_windows - Configure address Windows + * + * There are 8 address windows supported by Orion5x Soc to addess different + * devices. Each window can be configured for size, BAR and remap addr + * Below configuration is standard for most of the cases + * + * If remap function not used, remap_lo must be set as base + * + * Reference Documentation: + * Mbus-L to Mbus Bridge Registers Configuration. + * (Sec 25.1 and 25.3 of Datasheet) + */ +int orion5x_config_adr_windows(void) +{ + struct orion5x_win_registers *winregs = + (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; + + /* Window 0: PCIE MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM, ORION5X_TARGET_PCIE, + ORION5X_ATTR_PCIE_MEM, ORION5X_WIN_ENABLE), &winregs[0].ctrl); + writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); + + /* Window 1: PCIE IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO, ORION5X_TARGET_PCIE, + ORION5X_ATTR_PCIE_IO, ORION5X_WIN_ENABLE), &winregs[1].ctrl); + writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); + + /* Window 2: PCI MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM, ORION5X_TARGET_PCI, + ORION5X_ATTR_PCI_MEM, ORION5X_WIN_ENABLE), &winregs[2].ctrl); + writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base); + + /* Window 3: PCI IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO, ORION5X_TARGET_PCI, + ORION5X_ATTR_PCI_IO, ORION5X_WIN_ENABLE), &winregs[3].ctrl); + writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base); + + /* Window 4: DEV_CS0 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0, ORION5X_TARGET_DEVICE, + ORION5X_ATTR_DEV_CS0, ORION5X_WIN_ENABLE), &winregs[4].ctrl); + writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base); + + /* Window 5: DEV_CS1 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1, ORION5X_TARGET_DEVICE, + ORION5X_ATTR_DEV_CS1, ORION5X_WIN_ENABLE), &winregs[5].ctrl); + writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base); + + /* Window 6: DEV_CS2 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2, ORION5X_TARGET_DEVICE, + ORION5X_ATTR_DEV_CS2, ORION5X_WIN_ENABLE), &winregs[6].ctrl); + writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base); + + /* Window 7: BOOT Memory address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM, ORION5X_TARGET_DEVICE, + ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[7].ctrl); + writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base); + + return 0; +} + +/* + * orion5x_config_gpio - GPIO configuration + */ +void orion5x_config_gpio(u32 gpp_oe_val, u32 gpp_oe) +{ + struct orion5x_gpio_registers *gpioreg = + (struct orion5x_gpio_registers *)ORION5X_GPIO_BASE; + + /* Init GPIOS to default values as per board requirement */ + writel(gpp_oe_val, &gpioreg->dout); + writel(gpp_oe, &gpioreg->oe); +} + +/* + * orion5x_config_mpp - Multi-Purpose Pins Functionality configuration + * + * Each MPP can be configured to different functionality through + * MPP control register, ref (sec 6.1 of Orion5x h/w specification) + * + * There are maximum 64 Multi-Pourpose Pins on Orion5x + * Each MPP functionality can be configuration by a 4bit value + * of MPP control reg, the value and associated functionality depends + * upon used SoC varient + */ +int orion5x_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23) +{ + u32 *mppreg = (u32 *) ORION5X_MPP_BASE; + + /* program mpp registers */ + writel(mpp0_7, &mppreg[0]); + writel(mpp8_15, &mppreg[1]); + writel(mpp16_23, &mppreg[2]); + return 0; +} + +/* Orion5x identification is done through PCIE space. + * As long as there is no Orion5x support for PCIE, + * We'll define the ID and revision PCIE registers + * here. + */ +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) +u32 orion5x_device_id(void) +{ + return readl(PCIE_DEV_ID_OFF) >> 16; +} + +u32 orion5x_device_rev(void) +{ + return readl(PCIE_DEV_REV_OFF) & 0xff; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) + +int print_cpuinfo(void) +{ + char dev_str[] = "0x0000"; + char *dev_name = dev_str; + char rev_str[] = "0x00"; + char *rev_name = rev_str; + + u32 dev = orion5x_device_id(); + u32 rev = orion5x_device_rev(); + + if (dev == MV88F5181_DEV_ID) { + dev_name = "MV88F5181"; + if (rev == MV88F5181_REV_B1) { + rev_name = "B1"; + } else if (rev == MV88F5181L_REV_A1) { + dev_name = "MV88F5181L"; + rev_name = "A1"; + } else if (rev == MV88F5181L_REV_A0) { + dev_name = "MV88F5181L"; + rev_name = "A0"; + } else { + sprintf(rev_str,"0x%02x", rev); + } + } else if (dev == MV88F5182_DEV_ID) { + dev_name = "MV88F5182"; + if (rev == MV88F5182_REV_A2) { + rev_name = "A2"; + } else { + sprintf(rev_str,"0x%02x", rev); + } + } else if (dev == MV88F5281_DEV_ID) { + dev_name = "MV88F5281"; + if (rev == MV88F5281_REV_D2) { + rev_name = "D2"; + } else if (rev == MV88F5281_REV_D1) { + rev_name = "D1"; + } else if (rev == MV88F5281_REV_D0) { + rev_name = "D0"; + } else { + sprintf(rev_str,"0x%02x", rev); + } + } else if (dev == MV88F6183_DEV_ID) { + dev_name = "MV88F6183"; + if (rev == MV88F6183_REV_B0) { + rev_name = "B0"; + } else { + sprintf(rev_str,"0x%02x", rev); + } + } else { + sprintf(dev_str,"0x%04x", rev); + sprintf(rev_str,"0x%02x", rev); + } + + printf("SoC: Orion5x %s-%s\n", dev_name, rev_name); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + struct orion5x_cpu_registers *cpureg = + (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; + + /* Linux expects` the internal registers to be at 0xf1000000 */ + writel(ORION5X_REGS_PHY_BASE, ORION5X_OFFSET_REG); + + /* Enable and invalidate L2 cache in write through mode */ + writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); + invalidate_l2_cache(); + + orion5x_config_adr_windows(); + +#ifdef CONFIG_ORION5X_RGMII_PAD_1V8 + /* + * Configures the I/O voltage of the pads connected to Egigabit + * Ethernet interface to 1.8V + * By defult it is set to 3.3V + */ + reg = readl(ORION5X_REG_MPP_OUT_DRV_REG); + reg |= (1 << 7); + writel(reg, ORION5X_REG_MPP_OUT_DRV_REG); +#endif +#ifdef CONFIG_ORION5X_EGIGA_INIT + /* + * Set egiga port0/1 in normal functional mode + * This is required becasue on Orion5x by default ports are in reset mode + * OS egiga driver may not have provision to set them in normal mode + * and if u-boot is build without network support, network may fail at OS level + */ + reg = readl(ORION5XGBE_PORT_SERIAL_CONTROL1_REG(0)); + reg &= ~(1 << 4); /* Clear PortReset Bit */ + writel(reg, (ORION5XGBE_PORT_SERIAL_CONTROL1_REG(0))); + reg = readl(ORION5XGBE_PORT_SERIAL_CONTROL1_REG(1)); + reg &= ~(1 << 4); /* Clear PortReset Bit */ + writel(reg, (ORION5XGBE_PORT_SERIAL_CONTROL1_REG(1))); +#endif +#ifdef CONFIG_ORION5X_PCIE_INIT + /* + * Enable PCI Express Port0 + */ + reg = readl(&cpureg->ctrl_stat); + reg |= (1 << 0); /* Set PEX0En Bit */ + writel(reg, &cpureg->ctrl_stat); +#endif + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + volatile u32 temp; + + /*CPU streaming & write allocate */ + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 28); /* disable wr alloc */ + writefr_extra_feature_reg(temp); + + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 29); /* streaming disabled */ + writefr_extra_feature_reg(temp); + + /* L2Cache settings */ + temp = readfr_extra_feature_reg(); + /* Disable L2C pre fetch - Set bit 24 */ + temp |= (1 << 24); + /* enable L2C - Set bit 22 */ + temp |= (1 << 22); + writefr_extra_feature_reg(temp); + + icache_enable(); + /* Change reset vector to address 0x0 */ + temp = get_cr(); + set_cr(temp & ~CR_V); + + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ + +#ifdef CONFIG_ORION5X_EGIGA +int cpu_eth_init(bd_t *bis) +{ + orion5x_egiga_initialize(bis); + return 0; +} +#endif diff --git a/cpu/arm926ejs/orion5x/dram.c b/cpu/arm926ejs/orion5x/dram.c new file mode 100644 index 0000000..69aec26 --- /dev/null +++ b/cpu/arm926ejs/orion5x/dram.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <config.h> +#include <asm/arch/orion5x.h> + +#define ORION5X_REG_CPUCS_WIN_BAR(x) (ORION5X_REGISTER(0x1500) + (x * 0x08)) +#define ORION5X_REG_CPUCS_WIN_SZ(x) (ORION5X_REGISTER(0x1504) + (x * 0x08)) +/* + * orion5x_sdram_bar - reads SDRAM Base Address Register + */ +u32 orion5x_sdram_bar(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + + result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank)); + return result; +} + +/* + * orion5x_sdram_bs - reads SDRAM Bank size + */ +u32 orion5x_sdram_bs(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + result = 0xff000000 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + result += 0x01000000; + return result; +} diff --git a/cpu/arm926ejs/orion5x/mpp.c b/cpu/arm926ejs/orion5x/mpp.c new file mode 100644 index 0000000..1b1e7fa --- /dev/null +++ b/cpu/arm926ejs/orion5x/mpp.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support + * + * arch/arm/mach-orion5x/mpp.c + * + * MPP functions for Marvell Kirorion5xood SoCs + * Referenced from Linux kernel source + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <common.h> +#include <asm/arch/orion5x.h> +#include <asm/arch/mpp.h> + +static u32 orion5x_variant(void) +{ + switch (orion5x_device_id()) { + case MV88F5181_DEV_ID: + return 0; + case MV88F5182_DEV_ID: + return MPP_F5182_MASK; + case MV88F5281_DEV_ID: + return MPP_F5281_MASK; + case MV88F6183_DEV_ID: + return 0; + default: + debug("MPP setup: unknown Orion5x variant\n"); + return 0; + } +} + +#define MPP_CTRL(i) (ORION5X_MPP_BASE + (i* 4)) +#define MPP_NR_REGS (1 + MPP_MAX/8) + +void orion5x_mpp_conf(u32 *mpp_list) +{ + u32 mpp_ctrl[MPP_NR_REGS]; + unsigned int variant_mask; + int i; + + variant_mask = orion5x_variant(); + if (!variant_mask) + return; + + debug( "initial MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + mpp_ctrl[i] = readl(MPP_CTRL(i)); + debug(" %08x", mpp_ctrl[i]); + } + debug("\n"); + + + while (*mpp_list) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift; + + if (num > MPP_MAX) { + debug("orion5x_mpp_conf: invalid MPP " + "number (%u)\n", num); + continue; + } + if (!(*mpp_list & variant_mask)) { + debug("orion5x_mpp_conf: requested MPP%u config " + "unavailable on this hardware\n", num); + continue; + } + + shift = (num & 7) << 2; + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + + mpp_list++; + } + + debug(" final MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + writel(mpp_ctrl[i], MPP_CTRL(i)); + debug(" %08x", mpp_ctrl[i]); + } + debug("\n"); + +} diff --git a/cpu/arm926ejs/orion5x/timer.c b/cpu/arm926ejs/orion5x/timer.c new file mode 100644 index 0000000..80fee75 --- /dev/null +++ b/cpu/arm926ejs/orion5x/timer.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * Copyright (C) Marvell International Ltd. and its affiliates + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/orion5x.h> + +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ + +/* Timer reload and current value registers */ +struct orion5x_tmr_val { + u32 reload; /* Timer reload reg */ + u32 val; /* Timer value reg */ +}; + +/* Timer registers */ +struct orion5x_tmr_registers { + u32 ctrl; /* Timer control reg */ + u32 pad[3]; + struct orion5x_tmr_val tmr[2]; + u32 wdt_reload; + u32 wdt_val; +}; + +struct orion5x_tmr_registers *orion5x_tmr_regs = (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE; + +/* + * ARM Timers Registers Map + */ +#define CNTMR_CTRL_REG &orion5x_tmr_regs->ctrl +#define CNTMR_RELOAD_REG(tmrnum) &orion5x_tmr_regs->tmr[tmrnum].reload +#define CNTMR_VAL_REG(tmrnum) &orion5x_tmr_regs->tmr[tmrnum].val + +/* + * ARM Timers Control Register + * CPU_TIMERS_CTRL_REG (CTCR) + */ +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + +/* + * ARM Timer\Watchdog Reload Register + * CNTMR_RELOAD_REG (TRR) + */ +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* + * ARM Timer\Watchdog Register + * CNTMR_VAL_REG (TVRG) + */ +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff +#define TIMER_LOAD_VAL 0xffffffff + +#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \ + (CONFIG_SYS_TCLK / 1000)) + +static ulong timestamp; +static ulong lastdec; + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER; + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + + (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + } + lastdec = now; + + return timestamp; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + uint current; + ulong delayticks; + + current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); + delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + + if (current < delayticks) { + delayticks -= current; + while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; + while ((TIMER_LOAD_VAL - delayticks) < + readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; + } else { + while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > + (current - delayticks)) ; + } +} + +/* + * init the counter + */ +int timer_init(void) +{ + unsigned int cntmrctrl; + + /* load value into timer */ + writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + + /* enable timer in auto reload mode */ + cntmrctrl = readl(CNTMR_CTRL_REG); + cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); + cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); + writel(cntmrctrl, CNTMR_CTRL_REG); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index dd5f332..18686a2 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -30,6 +30,9 @@ #ifdef CONFIG_KIRKWOOD #include <asm/arch/kirkwood.h> #endif +#ifdef CONFIG_ORION5X +#include <asm/arch/orion5x.h> +#endif #if defined (CONFIG_SERIAL_MULTI) #include <serial.h> diff --git a/include/asm-arm/arch-orion5x/88f5182.h b/include/asm-arm/arch-orion5x/88f5182.h new file mode 100644 index 0000000..1dfdb24 --- /dev/null +++ b/include/asm-arm/arch-orion5x/88f5182.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood 88F6182 support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * Header file for Feroceon CPU core 88F5182 SOC. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_88F5182_H +#define _CONFIG_88F5182_H + +/* SOC specific definations */ +#define F88F5182_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE + +/* TCLK Core Clock defination */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +#endif /* _CONFIG_88F5182_H */ diff --git a/include/asm-arm/arch-orion5x/cpu.h b/include/asm-arm/arch-orion5x/cpu.h new file mode 100644 index 0000000..7078d2e --- /dev/null +++ b/include/asm-arm/arch-orion5x/cpu.h @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirorion5x_ood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ORION5X_CPU_H +#define _ORION5X_CPU_H + +#include <asm/system.h> + +#ifndef __ASSEMBLY__ + +#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) + +#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ + ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) + +#define ORION5X_REG_DEVICE_ID (ORION5X_MPP_BASE + 0x34) +#define ORION5X_REG_SYSRST_CNT (ORION5X_MPP_BASE + 0x50) +#define SYSRST_CNT_1SEC_VAL (25*1000000) +#define ORION5X_REG_MPP_OUT_DRV_REG (ORION5X_MPP_BASE + 0xE0) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum orion5x_cpu_winen { + ORION5X_WIN_DISABLE, + ORION5X_WIN_ENABLE +}; + +enum orion5x_cpu_target { + ORION5X_TARGET_DRAM = 0, + ORION5X_TARGET_DEVICE = 1, + ORION5X_TARGET_PCI = 3, + ORION5X_TARGET_PCIE = 4, + ORION5X_TARGET_SASRAM = 9 +}; + +enum orion5x_cpu_attrib { + ORION5X_ATTR_DRAM_CS0 = 0x0e, + ORION5X_ATTR_DRAM_CS1 = 0x0d, + ORION5X_ATTR_DRAM_CS2 = 0x0b, + ORION5X_ATTR_DRAM_CS3 = 0x07, + ORION5X_ATTR_PCI_MEM = 0x59, + ORION5X_ATTR_PCI_IO = 0x51, + ORION5X_ATTR_PCIE_MEM = 0x59, + ORION5X_ATTR_PCIE_IO = 0x51, + ORION5X_ATTR_SASRAM = 0x00, + ORION5X_ATTR_DEV_CS0 = 0x1e, + ORION5X_ATTR_DEV_CS1 = 0x1d, + ORION5X_ATTR_DEV_CS2 = 0x1b, + ORION5X_ATTR_BOOTROM = 0x0f +}; + +/* + * Default Device Address MAP BAR values + */ +#define ORION5X_DEFADR_PCIE_MEM 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCIE_IO 0xf0000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_IO (64*1024) + +#define ORION5X_DEFADR_PCI_MEM 0x98000000 +#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCI_IO 0xf0100000 +#define ORION5X_DEFSZ_PCI_IO (64*1024) + +#define ORION5X_DEFADR_DEV_CS0 0xfa000000 +#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024) + +#define ORION5X_DEFADR_DEV_CS1 0xf8000000 +#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024) + +#define ORION5X_DEFADR_DEV_CS2 0xfa800000 +#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024) + +#define ORION5X_DEFADR_BOOTROM 0xFFF80000 +#define ORION5X_DEFSZ_BOOTROM (512*1024) + +/* Constants for known devices and revisions + * + */ + +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3 + +/* + * read feroceon/sheeva core extra feature register + * using co-proc instruction + */ +static inline unsigned int readfr_extra_feature_reg(void) +{ + unsigned int val; + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); + return val; +} + +/* + * write feroceon/sheeva core extra feature register + * using co-proc instruction + */ +static inline void writefr_extra_feature_reg(unsigned int val) +{ + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); + isb(); +} + +/* + * MBus-L to Mbus Bridge Registers + * Ref: Datasheet sec:A.3 + */ +struct orion5x_win_registers { + u32 ctrl; + u32 base; + u32 remap_lo; + u32 remap_hi; +}; + +/* + * CPU control and status Registers + * Ref: Datasheet sec:A.3.2 + */ +struct orion5x_cpu_registers { + u32 config; /*0x20100 */ + u32 ctrl_stat; /*0x20104 */ + u32 rstoutn_mask; /* 0x20108 */ + u32 sys_soft_rst; /* 0x2010C */ + u32 ahb_mbus_cause_irq; /* 0x20110 */ + u32 ahb_mbus_mask_irq; /* 0x20114 */ + u32 pad1[2]; + u32 ftdll_config; /* 0x20120 */ + u32 pad2; + u32 l2_cfg; /* 0x20128 */ +}; + +/* + * GPIO Registers + * Ref: Datasheet sec:A.19 + */ +struct orion5x_gpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 irq_cause; + u32 irq_mask; + u32 irq_level; +}; + +/* + * functions + */ +void reset_cpu(unsigned long ignored); +u32 orion5x_device_id(void); +u32 orion5x_device_rev(void); +unsigned int orion5x_sdram_bar(enum memory_bank bank); +unsigned int orion5x_sdram_bs(enum memory_bank bank); +int orion5x_config_adr_windows(void); +void orion5x_config_gpio(unsigned int gpp_oe_val, unsigned int gpp_oe); +int orion5x_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23); +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); +#endif /* __ASSEMBLY__ */ +#endif /* _ORION5X_CPU_H */ diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h new file mode 100644 index 0000000..40fe2e0 --- /dev/null +++ b/include/asm-arm/arch-orion5x/gpio.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on arch/asm-arm/mach-kirkwood/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. + * Removed kernel level irq handling. Took some macros from kernel to + * allow build. + * + * Dieter Kiermaier dk-arm-linux(a)gmx.de + */ + +#ifndef __ORION5X_GPIO_H +#define __ORION5X_GPIO_H + +/* got from kernel include/linux/bitops.h */ +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) + +#define GPIO_MAX 50 +#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) +#define GPIO_OUT(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) + +/* + * Kirorion5xood-specific GPIO API + */ + +void orion5x_gpio_set_valid(unsigned pin, int mode); +int orion5x_gpio_is_valid(unsigned pin, int mode); +int orion5x_gpio_direction_input(unsigned pin); +int orion5x_gpio_direction_output(unsigned pin, int value); +int orion5x_gpio_get_value(unsigned pin); +void orion5x_gpio_set_value(unsigned pin, int value); +void orion5x_gpio_set_blink(unsigned pin, int blink); +void orion5x_gpio_set_unused(unsigned pin); + +#define GPIO_INPUT_OK (1 << 0) +#define GPIO_OUTPUT_OK (1 << 1) + +#endif diff --git a/include/asm-arm/arch-orion5x/mpp.h b/include/asm-arm/arch-orion5x/mpp.h new file mode 100644 index 0000000..a03eb8e --- /dev/null +++ b/include/asm-arm/arch-orion5x/mpp.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * Copyright 2009: Marvell Technology Group Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ORION5X_MPP_H +#define __ORION5X_MPP_H + +#define MPP(_num, _sel, _in, _out, _F5182, _F5281) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on F5182 */ ((!!(_F5182)) << 14) | \ + /* available on F5281 */ ((!!(_F5182)) << 15)) + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + + /* num sel i o 5182 5281 */ + +#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0 ) +#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0 ) + +#define MPP_F5182_MASK MPP( 0, 0x0, 0, 0, 1, 0 ) +#define MPP_F5281_MASK MPP( 0, 0x0, 0, 0, 0, 1 ) + +#define MPP0_PEX_RST_OUTn MPP( 0, 0x0, 0, 1, 1, 1 ) +#define MPP0_PCI_REQ2n MPP( 0, 0x2, 1, 0, 1, 1 ) +#define MPP0_GPIO MPP( 0, 0x3, 1, 1, 1, 1 ) + +#define MPP1_GPIO MPP( 1, 0x0, 1, 1, 1, 1 ) +#define MPP1_PCI_GNT2n MPP( 1, 0x2, 0, 1, 1, 1 ) + +#define MPP2_GPIO MPP( 2, 0x0, 1, 1, 1, 1 ) +#define MPP2_PCI_REQ3n MPP( 2, 0x2, 1, 0, 1, 1 ) +#define MPP2_PMEn MPP( 2, 0x3, 0, 1, 1, 1 ) + +#define MPP3_GPIO MPP( 3, 0x0, 1, 1, 1, 1 ) +#define MPP3_PCI_GNT3nO MPP( 3, 0x2, 0, 1, 1, 1 ) + +#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1 ) +#define MPP4_PCI_REQ4n MPP( 4, 0x2, 1, 0, 1, 1 ) +#define MPP4_BOOT_NAND_FLASH_REn MPP( 4, 0x4, 0, 0, 1, 1 ) +#define MPP4_SATA0_PRESENTn MPP( 4, 0x5, 0, 1, 1, 0 ) + +#define MPP5_GPIO MPP( 5, 0x0, 1, 1, 1, 1 ) +#define MPP5_PCI_GNT4n MPP( 5, 0x2, 0, 1, 1, 1 ) +#define MPP5_BOOT_NAND_FLASH_WEn MPP( 5, 0x4, 0, 0, 1, 1 ) +#define MPP5_SATA1_PRESENTn MPP( 5, 0x5, 0, 1, 1, 0 ) + +#define MPP6_GPIO MPP( 6, 0x0, 1, 1, 1, 1 ) +#define MPP6_PCI_REQ5n MPP( 6, 0x2, 1, 0, 1, 1 ) +#define MPP6_NAND_FLASH_RE0n MPP( 6, 0x4, 0, 0, 1, 1 ) +#define MPP6_SATA0_ACTn MPP( 6, 0x5, 0, 1, 1, 0 ) + +#define MPP7_GPIO MPP( 7, 0x0, 1, 1, 1, 1 ) +#define MPP7_PCI_GNT5n MPP( 7, 0x2, 0, 1, 1, 1 ) +#define MPP7_NAND_FLASH_WE0n MPP( 7, 0x4, 0, 0, 1, 1 ) +#define MPP7_SATA1_ACTn MPP( 7, 0x5, 0, 1, 1, 0 ) + +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1 ) +#define MPP8_GE_COL MPP( 8, 0x1, 1, 0, 1, 1 ) + +#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1 ) +#define MPP9_GE_RXERR MPP( 9, 0x1, 1, 0, 1, 1 ) + +#define MPP10_GPIO MPP( 10, 0x0, 1, 1, 1, 1 ) +#define MPP10_GE_CRS MPP( 10, 0x1, 1, 0, 1, 1 ) + +#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1 ) +#define MPP11_GE_TXERR MPP( 11, 0x1, 0, 1, 1, 1 ) + +#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 1, 1 ) +#define MPP12_GE_TXD4 MPP( 12, 0x1, 0, 1, 1, 1 ) +#define MPP12_NAND_FLASH_RE1n MPP( 12, 0x4, 1, 1, 1, 1 ) +#define MPP12_SATA0_PRESENTn MPP( 12, 0x5, 0, 1, 1, 0 ) + +#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1 ) +#define MPP13_GE_TXD5 MPP( 13, 0x1, 0, 1, 1, 1 ) +#define MPP13_NAND_FLASH_WE1n MPP( 13, 0x4, 0, 1, 1, 1 ) +#define MPP13_SATA1_PRESENTn MPP( 13, 0x5, 0, 1, 1, 0 ) + +#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1 ) +#define MPP14_GE_TXD6 MPP( 14, 0x1, 0, 1, 1, 1 ) +#define MPP14_NAND_FLASH_RE2n MPP( 14, 0x4, 1, 1, 1, 1 ) +#define MPP14_SATA0_ACTn MPP( 14, 0x5, 0, 1, 1, 0 ) + +#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1 ) +#define MPP15_GE_TXD7 MPP( 15, 0x1, 0, 1, 1, 1 ) +#define MPP15_NAND_FLASH_WE2n MPP( 15, 0x4, 0, 1, 1, 1 ) +#define MPP15_SATA1_ACTn MPP( 15, 0x5, 0, 1, 1, 0 ) + +#define MPP16_UART1_RXD MPP( 16, 0x0, 1, 0, 1, 1 ) +#define MPP16_GE_RXD4 MPP( 16, 0x1, 1, 0, 1, 1 ) +#define MPP16_BOOT_NAND_FLASH_REn MPP( 16, 0x4, 0, 0, 1, 1 ) +#define MPP16_GPIO MPP( 16, 0x5, 1, 1, 1, 0 ) + +#define MPP17_UART1_TXD MPP( 17, 0x0, 0, 1, 1, 1 ) +#define MPP17_GE_RXD5 MPP( 17, 0x1, 1, 0, 1, 1 ) +#define MPP17_BOOT_NAND_FLASH_WEn MPP( 17, 0x4, 0, 0, 1, 1 ) +#define MPP17_GPIO MPP( 17, 0x5, 1, 1, 1, 0 ) + +#define MPP18_UART1_CTSn MPP( 18, 0x0, 1, 0, 1, 1 ) +#define MPP18_GE_RXD6 MPP( 18, 0x1, 1, 0, 1, 1 ) +#define MPP18_GPIO MPP( 18, 0x5, 1, 1, 1, 0 ) + +#define MPP19_UART1_RTSn MPP( 19, 0x0, 0, 1, 1, 1 ) +#define MPP19_GE_RXD7 MPP( 19, 0x1, 1, 0, 1, 1 ) +#define MPP19_GPIO MPP( 19, 0x5, 1, 1, 1, 0 ) + +#define MPP_MAX 19 + +void orion5x_mpp_conf(unsigned int *mpp_list); + +#endif diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 0000000..76cb927 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * Header file for Marvell's Orion SoC with Feroceon CPU core. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_ORION5X_H +#define _ASM_ARCH_ORION5X_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <asm/io.h> +#endif /* __ASSEMBLY__ */ + +#if defined (CONFIG_FEROCEON) +#include <asm/arch/cpu.h> + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) +#define ORION5X_OFFSET_REG (INTREG_BASE + 0x20080) + +/* Documented registers */ +#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) +#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) +#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) +#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) +#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) +#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) +#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) +#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) +#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) +#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) +#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) +#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) +#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) + +#if defined (CONFIG_88F5182) +#include <asm/arch/88f5182.h> +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_FEROCEON */ +#endif /* _ASM_ARCH_ORION5X_H */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h new file mode 100644 index 0000000..a8036dd --- /dev/null +++ b/include/configs/edminiv2.h @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_EDMINIV2_H +#define _CONFIG_EDMINIV2_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING " Lacie ED Mini V2" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_EDMINIV2 1 /* Machine type */ + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* + * FLASH configuration + */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_FLASH_CFI_LEGACY + +//#define CONFIG_SYS_FLASH_LEGACY_512Kx8 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xfff80000 +#define CONFIG_SYS_FLASH_SECTSZ {16384,8192,8192,32768,65536,65536,65536,65536,65536,65536,65536} + +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration + */ +/* + * Disabling many default commands for staggered bring-up + */ +#if 0 +#include <config_cmd_default.h> +#else +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_EDITENV /* editenv */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVEENV /* saveenv */ +#define CONFIG_CMD_SOURCE /* "source" command support */ +#endif +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_ENV + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +#endif /* _CONFIG_EDMINIV2_H */ -- 1.6.4.4

4 5

[U-Boot] SDCARD Support - MPC8315e
by Marcos Cunha 14 Nov '09

14 Nov '09

Dears, Is there a SDCARD support for MPC8315e? Best Regards. -- cid:image002.gif@01C8B04F.DE139770 *Marcos Aurélio pinto cunha, PMP Engenheiro eletricista / electrical engineer *** cid:image002.gif@01C8B04F.DE139770 cid:image003.gif@01C8B04F.DE139770 Fone: +55 (85) 3216.7934 Fax: +55 (85) 3216.7864 Skype: marcos.cunha.ufc *ISO 9001 : 2000 - CMMI3*** *www.atlantico.com.br <http://www.atlantico.com.br>***

3 4

[U-Boot] Help command broken on AT91SAM9G10-EK
by Justin Waters 13 Nov '09

13 Nov '09

It looks like the "help" command is broken on the AT91SAM9G10-EK on 2009.11-rc1. I get the following message any time I try to run it: Unknown command 'help' - try 'help' I've bisected the issue, and it looks like it started with the addition of the "editenv" command (commit 246c69225c7b962d5c93e92282b78ca9fc5fefee). After some further digging, I found some weirdness with the help command beginning with the lead-up work to the editenv commit. Strange characters where being printed to the console whenever the help command was run. This issue started with commit ecc5500ee487170d8af6ff893fd1e0082380a01a, readline(): Add ability to modify a string buffer. I've also tested the AT91SAM9263-EK, and everything looks great. I believe the difference is related to the fact that the 9G10 does not use hush, while the 9263 does. Indeed, if you look at the main loop, non-hush systems use "readline" (which is indirectly modified by the aforementioned commits), while hush systems do not. I'm not really sure what would be the best way to fix this. Any ideas? -Justin Waters

3 8

[U-Boot] [PATCH 1/4] ppc/85xx: Add tracking of TLB CAM usage
by Kumar Gala 13 Nov '09

13 Nov '09

We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/cpu_init.c | 1 + cpu/mpc85xx/tlb.c | 62 +++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/config.h | 7 ++++ include/asm-ppc/global_data.h | 3 ++ include/asm-ppc/mmu.h | 2 + 5 files changed, 75 insertions(+), 0 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 16ce82c..006f36e 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -246,6 +246,7 @@ void cpu_init_f (void) #ifdef CONFIG_FSL_CORENET corenet_tb_init(); #endif + init_used_tlb_cams(); } diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index ea5deb2..54339c4 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -56,12 +56,72 @@ void init_tlbs(void) } #ifndef CONFIG_NAND_SPL +static inline void use_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->used_tlb_cams[i] |= (1 << bit); +} + +static inline void free_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->used_tlb_cams[i] &= ~(1 << bit); +} + +void init_used_tlb_cams(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) + gd->used_tlb_cams[i] = 0; + + /* walk all the entries */ + for (i = 0; i < num_cam; i++) { + u32 _mas1; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); + + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + /* if the entry isn't valid skip it */ + if ((_mas1 & MAS1_VALID)) + use_tlb_cam(i); + } +} + +int find_free_tlbcam(void) +{ + int i; + u32 idx; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) { + idx = ffz(gd->used_tlb_cams[i]); + + if (idx == 32) + continue; + } + + if (idx >= CONFIG_SYS_NUM_TLBCAMS) + return -1; + + return idx; +} + void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, u8 ts, u8 esel, u8 tsize, u8 iprot) { u32 _mas0, _mas1, _mas2, _mas3, _mas7; + if (tlb == 1) + use_tlb_cam(esel); + _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); _mas2 = FSL_BOOKE_MAS2(epn, wimge); @@ -80,6 +140,8 @@ void disable_tlb(u8 esel) { u32 _mas0, _mas1, _mas2, _mas3, _mas7; + free_tlb_cam(esel); + _mas0 = FSL_BOOKE_MAS0(1, esel, 0); _mas1 = 0; _mas2 = 0; diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index d5f82b4..796707e 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -63,6 +63,13 @@ #define CONFIG_TSECV2 #endif +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500MC) +#define CONFIG_SYS_NUM_TLBCAMS 64 +#elif defined(CONFIG_E500) +#define CONFIG_SYS_NUM_TLBCAMS 16 +#endif + /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 55e7e20..3f11918 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { #if defined(CONFIG_FSL_LAW) u32 used_laws; #endif +#if defined(CONFIG_E500) + u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; +#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index ec22a50..fd10249 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -479,6 +479,8 @@ extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); extern int find_tlb_idx(void *addr, u8 tlbsel); +extern void init_used_tlb_cams(void); +extern int find_free_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); -- 1.6.0.6

1 3

[U-Boot] [PATCH] ppc/85xx: Fix how we determine the number of CAM entries
by Kumar Gala 13 Nov '09

13 Nov '09

We were incorrectly use the max CAM size as the number of entries in the array for setting up the addrmap. We should be using the NENTRY field which is the low 12-bits of TLB1CFG. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/tlb.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 6e94c23..ea5deb2 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -132,10 +132,10 @@ int find_tlb_idx(void *addr, u8 tlbsel) void init_addr_map(void) { int i; - unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; /* walk all the entries */ - for (i = 0; i < max_cam; i++) { + for (i = 0; i < num_cam; i++) { unsigned long epn; u32 tsize, _mas1; phys_addr_t rpn; -- 1.6.0.6

1 0

[U-Boot] Please pull u-boot-ppc4xx/next
by Stefan Roese 13 Nov '09

13 Nov '09

Hi Wolfgang, please pull some updates for "next". Thanks. The following changes since commit cd12f615e4dd1dd24caab93f4157894783c6c1c0: Wolfgang Grandegger (1): mpc52xx: add support for the IPEK01 board are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git next Matthias Fuchs (1): ppc4xx: Add UBI support to PLU405 boards Stefan Roese (11): mkconfig: Create board directory (CONFIG_BOARDDIR) in include/config.h ppc4xx: sc3: Remove unreferenced external declarations from sc3.h ppc4xx: Fix problems in some ppc4xx board Makefiles ppc4xx: Add custom linker script to board/*/config.mk ppc4xx: Add common ppc4xx linker script ppc4xx: Remove board specific linker scripts from most PPC4xx boards ppc4xx: Consolidate 4xx PCIe board specific configuration ppc4xx: Remove duplicated is_pci_host() functions ppc4xx: Fix NAND booting targets after 4xx linker script consolidation ppc4xx: Switch to I2C bus numer 0 for chip_config command ppc4xx: Katmai: Add chip_config command board/amcc/acadia/config.mk | 4 + board/amcc/acadia/u-boot.lds | 134 ------------------ board/amcc/bamboo/bamboo.c | 23 --- board/amcc/bamboo/config.mk | 4 + board/amcc/bamboo/u-boot.lds | 143 ------------------- board/amcc/bubinga/u-boot.lds | 134 ------------------ board/amcc/canyonlands/canyonlands.c | 93 +------------ board/amcc/canyonlands/config.mk | 4 + board/amcc/canyonlands/u-boot.lds | 141 ------------------- board/amcc/ebony/ebony.c | 23 --- board/amcc/ebony/u-boot.lds | 141 ------------------- board/amcc/katmai/Makefile | 4 +- board/amcc/katmai/chip_config.c | 55 +++++++ board/amcc/katmai/cmd_katmai.c | 218 ----------------------------- board/amcc/katmai/katmai.c | 95 +------------- board/amcc/katmai/u-boot.lds | 138 ------------------ board/amcc/kilauea/config.mk | 4 + board/amcc/kilauea/kilauea.c | 77 +--------- board/amcc/kilauea/u-boot.lds | 134 ------------------ board/amcc/luan/luan.c | 23 --- board/amcc/luan/u-boot.lds | 141 ------------------- board/amcc/makalu/makalu.c | 67 --------- board/amcc/makalu/u-boot.lds | 134 ------------------ board/amcc/ocotea/ocotea.c | 24 --- board/amcc/ocotea/u-boot.lds | 141 ------------------- board/amcc/redwood/u-boot.lds | 145 ------------------- board/amcc/sequoia/config.mk | 4 + board/amcc/sequoia/sequoia.c | 21 --- board/amcc/sequoia/u-boot.lds | 142 ------------------- board/amcc/taihu/u-boot.lds | 134 ------------------ board/amcc/taishan/taishan.c | 23 --- board/amcc/taishan/u-boot.lds | 141 ------------------- board/amcc/walnut/u-boot.lds | 135 ------------------ board/amcc/yosemite/u-boot.lds | 141 ------------------- board/amcc/yosemite/yosemite.c | 23 --- board/amcc/yucca/u-boot.lds | 141 ------------------- board/amcc/yucca/yucca.c | 212 ++++------------------------ board/amirix/ap1000/config.mk | 3 + board/cray/L1/u-boot.lds | 150 -------------------- board/csb272/u-boot.lds | 151 -------------------- board/csb472/u-boot.lds | 151 -------------------- board/dave/PPChameleonEVB/u-boot.lds | 153 -------------------- board/eric/Makefile | 2 +- board/eric/u-boot.lds | 150 -------------------- board/esd/adciop/u-boot.lds | 132 ----------------- board/esd/apc405/u-boot.lds | 132 ----------------- board/esd/ar405/u-boot.lds | 132 ----------------- board/esd/ash405/u-boot.lds | 131 ----------------- board/esd/canbt/u-boot.lds | 132 ----------------- board/esd/cms700/u-boot.lds | 132 ----------------- board/esd/cpci2dp/u-boot.lds | 132 ----------------- board/esd/cpci405/u-boot.lds | 132 ----------------- board/esd/cpciiser4/u-boot.lds | 132 ----------------- board/esd/dasa_sim/config.mk | 3 + board/esd/dp405/u-boot.lds | 132 ----------------- board/esd/du405/u-boot.lds | 132 ----------------- board/esd/du440/du440.c | 21 --- board/esd/du440/u-boot.lds | 139 ------------------ board/esd/hh405/u-boot.lds | 132 ----------------- board/esd/hub405/u-boot.lds | 131 ----------------- board/esd/ocrtc/u-boot.lds | 147 ------------------- board/esd/pci405/u-boot.lds | 132 ----------------- board/esd/plu405/u-boot.lds | 131 ----------------- board/esd/pmc405/u-boot.lds | 131 ----------------- board/esd/pmc405de/u-boot.lds | 132 ----------------- board/esd/pmc440/pmc440.c | 2 +- board/esd/pmc440/u-boot.lds | 139 ------------------ board/esd/voh405/u-boot.lds | 132 ----------------- board/esd/vom405/u-boot.lds | 132 ----------------- board/esd/wuh405/u-boot.lds | 131 ----------------- board/exbitgen/u-boot.lds | 149 -------------------- board/g2000/u-boot.lds | 132 ----------------- board/gdsys/dlvision/u-boot.lds | 131 ----------------- board/gdsys/gdppc440etx/gdppc440etx.c | 22 --- board/gdsys/gdppc440etx/u-boot.lds | 141 ------------------- board/gdsys/intip/intip.c | 21 --- board/gdsys/intip/u-boot.lds | 143 ------------------- board/gdsys/neo/u-boot.lds | 129 ----------------- board/jse/Makefile | 2 +- board/jse/u-boot.lds | 140 ------------------ board/korat/korat.c | 21 --- board/korat/u-boot.lds | 142 ------------------- board/lwmon5/lwmon5.c | 23 --- board/lwmon5/u-boot.lds | 142 ------------------- board/ml2/Makefile | 2 +- board/ml2/config.mk | 3 + board/mpl/mip405/Makefile | 2 +- board/mpl/mip405/u-boot.lds | 154 -------------------- board/mpl/pip405/Makefile | 2 +- board/mpl/pip405/u-boot.lds | 149 -------------------- board/netstal/hcu4/u-boot.lds | 137 ------------------ board/netstal/hcu5/hcu5.c | 19 --- board/netstal/hcu5/u-boot.lds | 141 ------------------- board/netstal/mcu25/u-boot.lds | 137 ------------------ board/pcs440ep/pcs440ep.c | 23 --- board/prodrive/alpr/alpr.c | 2 +- board/prodrive/alpr/u-boot.lds | 141 ------------------- board/prodrive/p3p440/p3p440.c | 2 +- board/prodrive/p3p440/u-boot.lds | 141 ------------------- board/quad100hd/u-boot.lds | 131 ----------------- board/sandburst/common/sb_common.c | 13 -- board/sandburst/karef/u-boot.lds | 156 --------------------- board/sandburst/metrobox/u-boot.lds | 156 --------------------- board/sbc405/u-boot.lds | 147 ------------------- board/w7o/u-boot.lds | 132 ----------------- board/xes/xpedite1000/u-boot.lds | 151 -------------------- board/xes/xpedite1000/xpedite1000.c | 2 + board/xilinx/ml300/config.mk | 3 + board/zeus/u-boot.lds | 130 ----------------- cpu/ppc4xx/4xx_pci.c | 20 +++ cpu/ppc4xx/4xx_pcie.c | 123 ++++++++++++++++ cpu/ppc4xx/cmd_chip_config.c | 6 + cpu/ppc4xx/config.mk | 3 + {board/pcs440ep => cpu/ppc4xx}/u-boot.lds | 78 +++++++--- include/configs/PLU405.h | 18 ++- include/configs/katmai.h | 9 +- include/configs/sc3.h | 5 - include/configs/yucca.h | 8 + mkconfig | 9 ++ 119 files changed, 386 insertions(+), 10514 deletions(-) delete mode 100644 board/amcc/acadia/u-boot.lds delete mode 100644 board/amcc/bamboo/u-boot.lds delete mode 100644 board/amcc/bubinga/u-boot.lds delete mode 100644 board/amcc/canyonlands/u-boot.lds delete mode 100644 board/amcc/ebony/u-boot.lds create mode 100644 board/amcc/katmai/chip_config.c delete mode 100644 board/amcc/katmai/cmd_katmai.c delete mode 100644 board/amcc/katmai/u-boot.lds delete mode 100644 board/amcc/kilauea/u-boot.lds delete mode 100644 board/amcc/luan/u-boot.lds delete mode 100644 board/amcc/makalu/u-boot.lds delete mode 100644 board/amcc/ocotea/u-boot.lds delete mode 100644 board/amcc/redwood/u-boot.lds delete mode 100644 board/amcc/sequoia/u-boot.lds delete mode 100644 board/amcc/taihu/u-boot.lds delete mode 100644 board/amcc/taishan/u-boot.lds delete mode 100644 board/amcc/walnut/u-boot.lds delete mode 100644 board/amcc/yosemite/u-boot.lds delete mode 100644 board/amcc/yucca/u-boot.lds delete mode 100644 board/cray/L1/u-boot.lds delete mode 100644 board/csb272/u-boot.lds delete mode 100644 board/csb472/u-boot.lds delete mode 100644 board/dave/PPChameleonEVB/u-boot.lds delete mode 100644 board/eric/u-boot.lds delete mode 100644 board/esd/adciop/u-boot.lds delete mode 100644 board/esd/apc405/u-boot.lds delete mode 100644 board/esd/ar405/u-boot.lds delete mode 100644 board/esd/ash405/u-boot.lds delete mode 100644 board/esd/canbt/u-boot.lds delete mode 100644 board/esd/cms700/u-boot.lds delete mode 100644 board/esd/cpci2dp/u-boot.lds delete mode 100644 board/esd/cpci405/u-boot.lds delete mode 100644 board/esd/cpciiser4/u-boot.lds delete mode 100644 board/esd/dp405/u-boot.lds delete mode 100644 board/esd/du405/u-boot.lds delete mode 100644 board/esd/du440/u-boot.lds delete mode 100644 board/esd/hh405/u-boot.lds delete mode 100644 board/esd/hub405/u-boot.lds delete mode 100644 board/esd/ocrtc/u-boot.lds delete mode 100644 board/esd/pci405/u-boot.lds delete mode 100644 board/esd/plu405/u-boot.lds delete mode 100644 board/esd/pmc405/u-boot.lds delete mode 100644 board/esd/pmc405de/u-boot.lds delete mode 100644 board/esd/pmc440/u-boot.lds delete mode 100644 board/esd/voh405/u-boot.lds delete mode 100644 board/esd/vom405/u-boot.lds delete mode 100644 board/esd/wuh405/u-boot.lds delete mode 100644 board/exbitgen/u-boot.lds delete mode 100644 board/g2000/u-boot.lds delete mode 100644 board/gdsys/dlvision/u-boot.lds delete mode 100644 board/gdsys/gdppc440etx/u-boot.lds delete mode 100644 board/gdsys/intip/u-boot.lds delete mode 100644 board/gdsys/neo/u-boot.lds delete mode 100644 board/jse/u-boot.lds delete mode 100644 board/korat/u-boot.lds delete mode 100644 board/lwmon5/u-boot.lds delete mode 100644 board/mpl/mip405/u-boot.lds delete mode 100644 board/mpl/pip405/u-boot.lds delete mode 100644 board/netstal/hcu4/u-boot.lds delete mode 100644 board/netstal/hcu5/u-boot.lds delete mode 100644 board/netstal/mcu25/u-boot.lds delete mode 100644 board/prodrive/alpr/u-boot.lds delete mode 100644 board/prodrive/p3p440/u-boot.lds delete mode 100644 board/quad100hd/u-boot.lds delete mode 100644 board/sandburst/karef/u-boot.lds delete mode 100644 board/sandburst/metrobox/u-boot.lds delete mode 100644 board/sbc405/u-boot.lds delete mode 100644 board/w7o/u-boot.lds delete mode 100644 board/xes/xpedite1000/u-boot.lds delete mode 100644 board/zeus/u-boot.lds rename {board/pcs440ep => cpu/ppc4xx}/u-boot.lds (71%)

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[U-Boot] redundant code in common/cmd_i2c.
by PratapChandu 13 Nov '09

13 Nov '09

The following code fragment in the file common/cmd_i2c.c seems to be redundant. Is not good to delete ? Line 330 - 336 is like below #if 0 for (timeout = 0; timeout < 10; timeout++) { udelay(2000); if (i2c_probe(chip) == 0) break; } #endif Regards Pratap Chandu Indian Institute of Tecnology , Roorkee

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[U-Boot] Invitation to connect on LinkedIn
by praveen garaga 13 Nov '09

13 Nov '09

LinkedIn ------------ I'd like to add you to my professional network on LinkedIn. - praveen Confirm that you know praveen garaga https://www.linkedin.com/e/isd/859852854/kHjqICy1/ Every day, millions of professionals like praveen garaga use LinkedIn to connect with colleagues, find experts, and explore opportunities. ------ (c) 2009, LinkedIn Corporation

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Re: [U-Boot] [PATCH] S3C6400/SMDK6400: fix stack_setup in start.S
by "Seunghyeon Rhee (이승현)" 13 Nov '09

13 Nov '09

Dear Minkyu Kang, 2009/11/2 Minkyu Kang <promsoft(a)gmail.com>: > Dear Seunghyeon Rhee > > 2009/10/31 "Seunghyeon Rhee (이승현)" <seunghyeon(a)lpmtec.com>: >> stack_setup is modified to initialize the stack on the correct address in >> DRAM accroding to the typical memory configuration described in >> README and the related CONFIG_* macro definitions. This makes macro >> CONFIG_MEMORY_UPPER_CODE no longer necessry. This was introduced >> and used only by this board for some unclear reason. The definition of >> this macro is removed because it's not referenced elsewhere. >> >> Signed-off-by: Seunghyeon Rhee <seunghyeon(a)lpmtec.com> >> --- >> cpu/arm1176/start.S | 7 +------ >> include/configs/smdk6400.h | 2 -- >> 2 files changed, 1 insertions(+), 8 deletions(-) >> >> diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S >> index cb891df..1ecb3b9 100644 >> --- a/cpu/arm1176/start.S >> +++ b/cpu/arm1176/start.S >> @@ -241,16 +241,11 @@ mmu_enable: >> skip_hw_init: >> /* Set up the stack */ >> stack_setup: >> -#ifdef CONFIG_MEMORY_UPPER_CODE >> - ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc) >> -#else >> - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ >> + ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */ > > this change is unnecessary, TEXT_BASE and CONFIG_SYS_UBOOT_BASE must be same. That's true for the body of U-Boot but not for SPL, where TEXT_BASE is defined to be '0'. Please refer to board/samsung/smdk6400/config.mk. On the other hand, CONFIG_SYS_UBOOT_BASE is always dependent on DRAM's base. In SPL, the base of the code should be '0' (the steppingstone memory) and then the stack is located below '0' - not a valid area. If SPL itself requires no stack, it should be no problem. But start.S calls nand_boot function right after the stack is badly set up in the air. My test results are like the following: with CONFIG_MEMORY_UPPER_CODE defined : OK with CONFIG_MEMORY_UPPER_CODE undefined : - SPL bypassed (U-Boot downloaded to DRAM directly by USB monitor program) : OK - through SPL : Not OK (seems to fail for SPL downloading the code to DRAM) I think CONFIG_MEMORY_UPPER_CODE was tested for the case it's defined but not enough for the case it's not defined. Would you check it again? > btw, is there need CONFIG_SYS_UBOOT_BASE define? > If you are not sure, why did you use CONFIG_SYS_UBOOT_BASE for the case CONFIG_MEMORY_UPPER_CODE is defined while you use TEXT_BASE otherwise? I think the unnecessary macro definition here is not CONFIG_..._BASE but CONFIG_..._CODE. TEXT_BASE and CONFIG_..._BASE have their own meanings and so both are necessary. Best regards, Seunghyeon >> sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc >> area */ >> sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* >> bdinfo */ >> sub sp, r0, #12 /* leave 3 words for abort-stack */ >> >> -#endif >> - >> clear_bss: >> ldr r0, _bss_start /* find start of bss segment */ >> ldr r1, _bss_end /* stop here */ >> diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h >> index f6e1221..f644cd2 100644 >> --- a/include/configs/smdk6400.h >> +++ b/include/configs/smdk6400.h >> @@ -49,8 +49,6 @@ >> #define CONFIG_ENABLE_MMU >> #endif >> >> -#define CONFIG_MEMORY_UPPER_CODE >> - >> #define CONFIG_SETUP_MEMORY_TAGS >> #define CONFIG_CMDLINE_TAG >> #define CONFIG_INITRD_TAG >> -- >> 1.6.2.5 >> >> >> -- >> Seunghyeon Rhee, Ph.D. / Director >> LPM Technology Inc. >> T +82-70-8255-6007 F +82-2-6442-6462 >> M +82-10-2790-0657 >> _______________________________________________ >> U-Boot mailing list >> U-Boot(a)lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot >> > > Thanks for patch :) > Minkyu Kang > -- > from. prom. > www.promsoft.net > _______________________________________________ > U-Boot mailing list > U-Boot(a)lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > -- Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657

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