November 2009 - U-Boot

[U-Boot] [RFC] env: Group environment variables
by John Schmoller 17 Nov '09

17 Nov '09

This patch groups environment variables using a non-invasive protocol. Grouping is achieved by setting a "grouping" variable to a string of variables, and setting the master grouping variable, "env_groups" to the list of these grouping variables. For instance, setenv net ipaddr netmask gatewayip serverip setenv boot bootcmd bootdelay bootargs setenv env_groups net boot would print 4 variables grouped under net, 3 variables grouped under boot, and the rest of the variables grouped under "other". If env_groups is not defined, print behaves normally. Signed-off-by: John Schmoller <jschmoller(a)xes-inc.com> --- I'm interesetd in seeing peoples opinions of this implementation of grouping environment variables. My major concerns about this implementation are 1) Using parse_line() requires placing several potentially large char array (CONFIG_SYS_CBSIZE in size) on the stack. Parse_line() does seem to be the right tool for the job, though. 2) Trying to figure out which enviroment variables have already been printed in groups is less than elegant. Currently, it's a brute-force approach of looking through every entry until a variable is found in a group or not. Suggestions for cleaner algorithms here would be appreciated. Implementation notes: If env_groups is defined, none of the grouping variables will be printed. This seemed to clutter up the printenv output. Grouping environment variables will almost certainly lead to a reqirement for bumping up CONFIG_SYS_MAXARGS. Example output: => printenv === pci variables === pci1inboundmembus=0x00000000 pci1inboundmemphys=0x00000000 pci1inboundmemsize=0x08000000 pci1outboundmembus=0x80000000 pci1outboundmemphys=0x80000000 pci1outboundmemsize=0x40000000 pci1outboundiobus=0x00000000 pci1outboundiophys=0xe8000000 pci1outboundiosize=0x00800000 pci2outboundmembus=0xc0000000 pci2outboundmemphys=0xc0000000 pci2outboundmemsize=0x10000000 === boot variables === bootcmd_flash1=run set_bootargs; bootm 0xfef00000 - 0xfff00000 bootcmd_flash2=run set_bootargs; bootm 0xf6f00000 - 0xf7f00000 bootcmd=tftp 10000000 home/jschmoller/vxWorks.st;bootvx bootdelay=3 bootfile=/home/shared/pxe/pxelinux.0 bootcmd_net=run set_bootargs; $download_cmd $osaddr $osfile; if test $? -eq 0; then if test -n $fdtaddr; then $download_cmd $fdtaddr $fdtfile; if test $? -eq 0; then bootm $osaddr - $fdtaddr; else; echo FDT DOWNLOAD FAILED; fi; else; bootm $osaddr; fi; else; echo OS DOWNLOAD FAILED; fi; === prog variables === prog_uboot1=$download_cmd $loadaddr $ubootfile; if test $? -eq 0; then protect off 0xfff80000 +80000; erase 0xfff80000 +80000; cp.w $loadaddr 0xfff80000 40000; protect on 0xfff80000 +80000; cmp.b $loadaddr 0xfff80000 80000; if test $? -ne 0; then echo PROGRAM FAILED; else; echo PROGRAM SUCCEEDED; fi; else; echo DOWNLOAD FAILED; fi; prog_uboot2=$download_cmd $loadaddr $ubootfile; if test $? -eq 0; then protect off 0xf7f80000 +80000; erase 0xf7f80000 +80000; cp.w $loadaddr 0xf7f80000 40000; protect on 0xf7f80000 +80000; cmp.b $loadaddr 0xf7f80000 80000; if test $? -ne 0; then echo PROGRAM FAILED; else; echo PROGRAM SUCCEEDED; fi; else; echo DOWNLOAD FAILED; fi; ubootfile=home/jschmoller/u-boot.bin prog_os1=$download_cmd $osaddr $osfile; if test $? -eq 0; then erase 0xfef00000 +$filesize; cp.b $osaddr 0xfef00000 $filesize; cmp.b $osaddr 0xfef00000 $filesize; if test $? -ne 0; then echo OS PROGRAM FAILED; else; echo OS PROGRAM SUCCEEDED; fi; else; echo OS DOWNLOAD FAILED; fi; prog_os2=$download_cmd $osaddr $osfile; if test $? -eq 0; then erase 0xf6f00000 +$filesize; cp.b $osaddr 0xf6f00000 $filesize; cmp.b $osaddr 0xf6f00000 $filesize; if test $? -ne 0; then echo OS PROGRAM FAILED; else; echo OS PROGRAM SUCCEEDED; fi; else; echo OS DOWNLOAD FAILED; fi; osfile=/home/user/board.uImage osaddr=0x1000000 prog_fdt1=$download_cmd $fdtaddr $fdtfile; if test $? -eq 0; then erase 0xfff00000 +$filesize;cp.b $fdtaddr 0xfff00000 $filesize; cmp.b $fdtaddr 0xfff00000 $filesize; if test $? -ne 0; then echo FDT PROGRAM FAILED; else; echo FDT PROGRAM SUCCEEDED; fi; else; echo FDT DOWNLOAD FAILED; fi; prog_fdt2=$download_cmd $fdtaddr $fdtfile; if test $? -eq 0; then erase 0xf7f00000 +$filesize;cp.b $fdtaddr 0xf7f00000 $filesize; cmp.b $fdtaddr 0xf7f00000 $filesize; if test $? -ne 0; then echo FDT PROGRAM FAILED; else; echo FDT PROGRAM SUCCEEDED; fi; else; echo FDT DOWNLOAD FAILED; fi; fdtfile=/home/user/board.dtb fdtaddr=c00000 === net variables === ## Error: "ipaddr" not defined netmask=255.255.0.0 serverip=10.52.0.33 gatewayip=10.52.0.1 ethaddr=00:17:3c:00:5f:30 ethact=eTSEC1 === board variables === serial#=02091009 board_cfg=90030065B-1 board_rev=SB === junk variables === ## Error: group "junk" not defined === other variables === baudrate=115200 loads_echo=1 preboot= autoload=yes download_cmd=tftp console_args=console=ttyS0,115200 root_args=root=/dev/nfs rw misc_args=ip=on set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args} loadaddr=0x1000000 pci2outboundiobus=0x00000000 pci2outboundiophys=0xe8800000 pci2outboundiosize=0x00800000 eth1addr=00:17:3c:00:5f:31 dnsip=10.52.0.1 skip_nand_bbt=yes pcidelay=1000 loadaddr=100000 bootargs=motetsec(0,0)host:/home/mstarzewski/xes8572-vxWorks.st h=10.52.0.33 e=10.52.143.154:ffff0000 u=drives pw=drives f=0x0 filesize=869D2 fileaddr=10000000 stdin=serial stdout=serial stderr=serial Environment size: 4148/32764 bytes => common/cmd_nvedit.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 110 insertions(+), 10 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index eb89e9e..6420e17 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -71,6 +71,54 @@ SPI_FLASH|MG_DISK|NVRAM|NOWHERE} #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) +enum { + PRINTENV_STATE_MATCHED = 0, + PRINTENV_STATE_ALL, + PRINTENV_STATE_SEARCH, + PRINTENV_STATE_GROUP +}; + +static int env_in_group(char *env) +{ + char *s; + char group_buf[CONFIG_SYS_CBSIZE]; + char *group_argv[CONFIG_SYS_MAXARGS + 1]; + int group_argc; + char env_buf[CONFIG_SYS_CBSIZE]; + char *env_argv[CONFIG_SYS_MAXARGS + 1]; + int env_argc; + int i, j; + + if (strcmp("env_groups", env) == 0) + return 1; + + if ((s = getenv("env_groups")) == NULL) + return 0; + + strcpy(group_buf, s); + group_argc = parse_line(group_buf, group_argv); + + /* Spin through all group variables specified in "env_groups" */ + for (i = 0; i < group_argc; i++) { + if ((s = getenv(group_argv[i])) == NULL) + continue; + + if (strcmp(group_argv[i], env) == 0) + return 1; + + strcpy(env_buf, s); + env_argc = parse_line(env_buf, env_argv); + + /* Spin through all vars contained in each group variable */ + for (j = 0; j < env_argc; j++) { + if (strcmp(env_argv[j], env) == 0) + return 1; + } + } + + return 0; +} + /************************************************************************ ************************************************************************/ @@ -101,30 +149,48 @@ int get_env_id (void) * state 0: finish printing this string and return (matched!) * state 1: no matching to be done; print everything * state 2: continue searching for matched name + * state 3: print all only if not found in a group */ static int printenv(char *name, int state) { - int i, j; - char c, buf[17]; + int i, j, prev_state, size; + char c, buf[17], *str, *addr; i = 0; buf[16] = '\0'; + prev_state = state; while (state && env_get_char(i) != '\0') { - if (state == 2 && envmatch((uchar *)name, i) >= 0) - state = 0; + if (state == PRINTENV_STATE_SEARCH && + envmatch((uchar *)name, i) >= 0) + state = PRINTENV_STATE_MATCHED; + + if (prev_state == PRINTENV_STATE_GROUP) { + addr = (char *)env_get_addr(i); + size = strchr(addr, '=') - addr; + str = malloc((size + 1) * sizeof(char)); + strncpy(str, addr, size); + str[size] = '\0'; + + if (env_in_group(str)) + state = PRINTENV_STATE_SEARCH; + else + state = PRINTENV_STATE_ALL; + + free(str); + } j = 0; do { buf[j++] = c = env_get_char(i++); if (j == sizeof(buf) - 1) { - if (state <= 1) + if (state != PRINTENV_STATE_SEARCH) puts(buf); j = 0; } } while (c != '\0'); - if (state <= 1) { + if (state != PRINTENV_STATE_SEARCH) { if (j) puts(buf); putc('\n'); @@ -134,7 +200,7 @@ static int printenv(char *name, int state) return -1; } - if (state == 0) + if (state == PRINTENV_STATE_MATCHED) i = 0; return i; } @@ -143,10 +209,44 @@ int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i; int rcode = 0; + char *s; + char group_buf[CONFIG_SYS_CBSIZE]; + char *group_argv[CONFIG_SYS_MAXARGS + 1]; + int group_argc; + char env_buf[CONFIG_SYS_CBSIZE]; + char *env_argv[CONFIG_SYS_MAXARGS + 1]; + int env_argc; if (argc == 1) { - /* print all env vars */ - rcode = printenv(NULL, 1); + if ((s = getenv("env_groups")) == NULL) { + /* print all env vars */ + rcode = printenv(NULL, PRINTENV_STATE_ALL); + } else { + /* print all env vars, but group them */ + strcpy(group_buf, s); + group_argc = parse_line(group_buf, group_argv); + + /* Cycle through all the groups in env_groups */ + for (i = 0; i < group_argc; i++) { + printf("=== %s variables ===\n", group_argv[i]); + if ((s = getenv(group_argv[i])) == NULL) { + printf("## Error: group \"%s", + group_argv[i]); + printf("\" not defined\n\n"); + continue; + } + + /* Recursively call printenv for each group */ + sprintf(env_buf, "printenv %s", s); + env_argc = parse_line(env_buf, env_argv); + do_printenv(cmdtp, flag, env_argc, env_argv); + putc('\n'); + } + + puts("=== other variables ===\n"); + rcode = printenv(NULL, PRINTENV_STATE_GROUP); + } + if (rcode < 0) return 1; printf("\nEnvironment size: %d/%ld bytes\n", @@ -157,7 +257,7 @@ int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* print selected env vars */ for (i = 1; i < argc; ++i) { char *name = argv[i]; - if (printenv(name, 2)) { + if (printenv(name, PRINTENV_STATE_SEARCH)) { printf("## Error: \"%s\" not defined\n", name); ++rcode; } -- 1.6.0.4

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[U-Boot] [PATCH 3/4] ARM Add New Board GEC2410
by Hui.Tang 17 Nov '09

17 Nov '09

S3C2410 NAND flash add missing function. checkpatch.pl result is as following total: 0 errors, 0 warnings, 57 lines checked 0003-S3C2410-NAND-flash-add-missing-function.patch has no obvious style problems and is ready for submission. ========================================================= Signed-off-by: Hui.Tang <zetalabs(a)gmail.com> --- drivers/mtd/nand/s3c2410_nand.c | 31 +++++++++++++++++++++++++++---- 1 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index f2f3e72..815c78e 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -36,6 +36,21 @@ #define S3C2410_ADDR_NALE 4 #define S3C2410_ADDR_NCLE 8 +#ifdef CONFIG_NAND_SPL + +/* in the early stage of NAND flash booting, printf() is not available */ +#define printf(fmt, args...) + +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = readb(this->IO_ADDR_R); +} +#endif + static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; @@ -83,9 +98,10 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - ecc_code[0] = NFECC0; - ecc_code[1] = NFECC1; - ecc_code[2] = NFECC2; + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + ecc_code[0] = readb(&nand->NFECC); + ecc_code[1] = readb(&nand->NFECC + 1); + ecc_code[2] = readb(&nand->NFECC + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); @@ -130,8 +146,13 @@ int board_nand_init(struct nand_chip *nand) /* initialize nand_chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->select_chip = NULL; + /* read_buf and write_buf are default */ /* read_byte and write_byte are default */ +#ifdef CONFIG_NAND_SPL + nand->read_buf = nand_read_buf; +#endif /* hwcontrol always must be implemented */ nand->cmd_ctrl = s3c2410_hwcontrol; @@ -142,7 +163,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.hwctl = s3c2410_nand_enable_hwecc; nand->ecc.calculate = s3c2410_nand_calculate_ecc; nand->ecc.correct = s3c2410_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW3_512; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; #else nand->ecc.mode = NAND_ECC_SOFT; #endif -- 1.6.0.4

2 1

[U-Boot] [PATCH 2/4] ARM Add New Board GEC2410
by Hui.Tang 17 Nov '09

17 Nov '09

Add ARM920T NAND flash booting. checkpatch.pl shows that all things are fine. total: 0 errors, 0 warnings, 70 lines checked 0002-ARM920T-NAND-flash-booting.patch has no obvious style problems and is ready for submission. ========================================================= Signed-off-by: Hui.Tang <zetalabs(a)gmail.com> --- cpu/arm920t/start.S | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 114427a..9b08e3c 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -38,6 +38,7 @@ .globl _start _start: b start_code +#ifndef CONFIG_NAND_SPL ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -53,7 +54,13 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#else + . = _start + 64 +#endif +.global _end_vect +_end_vect: .balignl 16,0xdeadbeef @@ -197,7 +204,11 @@ copy_loop: /* Set up the stack */ stack_setup: +#ifndef CONFIG_NAND_SPL ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ +#else + ldr r0, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE) +#endif sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ @@ -215,9 +226,14 @@ clbss_l:str r2, [r0] /* clear loop... */ cmp r0, r1 ble clbss_l +#ifndef CONFIG_NAND_SPL ldr pc, _start_armboot _start_armboot: .word start_armboot +#else + b nand_boot +/* .word nand_boot */ +#endif /* @@ -234,6 +250,7 @@ _start_armboot: .word start_armboot #ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: +#ifndef CONFIG_NAND_SPL /* * flush v4 I/D caches */ @@ -250,6 +267,7 @@ cpu_init_crit: orr r0, r0, #0x00000002 @ set bit 2 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 +#endif /* CONFIG_NAND_SPL */ /* * before relocating, we have to setup RAM timing @@ -264,6 +282,7 @@ cpu_init_crit: mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#ifndef CONFIG_NAND_SPL /* ************************************************************************* * @@ -434,3 +453,4 @@ fiq: bl do_fiq #endif +#endif /* CONFIG_NAND_SPL */ -- 1.6.0.4

2 1

[U-Boot] [PATCH] TI: DaVinci: Updating EMAC driver for DM365 and DM646x
by s-paulraj＠ti.com 16 Nov '09

16 Nov '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> The EMAC IP on DM365 and DM646x is slightly different from that on DM644x. This patch updates the DaVinci EMAC driver so that EMAC becomes operational on DM365 in U-Boot. A flag 'CONFIG_DAVINCI_EMAC_VERSION2' is used in the driver. This flag will need to be defined in the DM365 config file. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- The same modifications work on DM646x in a slightly older version of U-Boot. So when enabled this should work on the DM6467 EVM as well. This has at this point of time not been tested on the DM6467 in the latest version of U-Boot. drivers/net/davinci_emac.c | 79 ++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 77 insertions(+), 2 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index fa8cee4..1df98e9 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -107,6 +107,33 @@ static void davinci_eth_mdio_enable(void) while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} } +/* Read a PHY register via MDIO inteface */ +static int mdio_read(int phy_addr, int reg_num) +{ + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1F) << 21) | + ((phy_addr & 0x1F) << 16); + + /* Wait for command to complete */ + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO); + + return adap_mdio->USERACCESS0 & 0xFFFF; +} + +/* Write to a PHY register via MDIO inteface */ +void mdio_write(int phy_addr, int reg_num, unsigned int data) +{ + /* Wait for User access register to be ready */ + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO); + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1F) << 21) | + ((phy_addr & 0x1F) << 16) | + (data & 0xFFFF); +} + /* * Tries to find an active connected PHY. Returns 1 if address if found. * If no active PHY (or more than one PHY) found returns 0. @@ -248,6 +275,31 @@ static int davinci_mii_phy_write(char *devname, unsigned char addr, unsigned cha #endif +static void emac_gigabit_enable(void) +{ + int temp; + + temp = mdio_read(EMAC_MDIO_PHY_NUM, 0); + + if (temp & (1 << 6)) { + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC and PHY + */ + adap_emac->MACCONTROL |= EMAC_MACCONTROL_GIGFORCE | + EMAC_MACCONTROL_GIGABIT_ENABLE; + + /* + * The SYS_CLK which feeds the SOC for giga-bit operation + * does not seem to be enabled after reset as expected. + * Force enabling SYS_CLK by writing to the PHY + */ + temp = mdio_read(EMAC_MDIO_PHY_NUM, 22); + temp |= (1 << 4); + mdio_write(EMAC_MDIO_PHY_NUM, 22, temp); + } +} + /* Eth device open */ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) @@ -261,10 +313,15 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) /* Reset EMAC module and disable interrupts in wrapper */ adap_emac->SOFTRESET = 1; while (adap_emac->SOFTRESET != 0) {;} +#if defined(CONFIG_DAVINCI_EMAC_VERSION2) + adap_ewrap->SOFTRST = 1; + while (adap_ewrap->SOFTRST != 0); +#else adap_ewrap->EWCTL = 0; for (cnt = 0; cnt < 5; cnt++) { clkdiv = adap_ewrap->EWCTL; } +#endif rx_desc = emac_rx_desc; @@ -282,6 +339,10 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) adap_emac->MACADDRLO = (davinci_eth_mac_addr[5] << 8) | (davinci_eth_mac_addr[4]); +#if defined(CONFIG_DAVINCI_EMAC_VERSION2) + /* Set the Match and Valid Bits */ + adap_emac->MACADDRLO |= (1 << 19) | (1 << 20); +#endif adap_emac->MACHASH1 = 0; adap_emac->MACHASH2 = 0; @@ -347,8 +408,15 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); +#if defined(CONFIG_DAVINCI_EMAC_VERSION2) + /* We need to wait for MDIO to start */ + udelay(1000); +#endif + if (!phy.get_link_speed(active_phy_addr)) return(0); + else + emac_gigabit_enable(); /* Start receive process */ adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; @@ -411,7 +479,11 @@ static void davinci_eth_close(struct eth_device *dev) /* Reset EMAC module and disable interrupts in wrapper */ adap_emac->SOFTRESET = 1; +#if defined(CONFIG_DAVINCI_EMAC_VERSION2) + adap_ewrap->SOFTRST = 1; +#else adap_ewrap->EWCTL = 0; +#endif debug_emac("- emac_close\n"); } @@ -433,7 +505,8 @@ static int davinci_eth_send_packet (struct eth_device *dev, if (!phy.get_link_speed (active_phy_addr)) { printf ("WARN: emac_send_packet: No link\n"); return (ret_status); - } + } else + emac_gigabit_enable(); /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { @@ -456,7 +529,9 @@ static int davinci_eth_send_packet (struct eth_device *dev, if (!phy.get_link_speed (active_phy_addr)) { davinci_eth_ch_teardown (EMAC_CH_TX); return (ret_status); - } + } else + emac_gigabit_enable(); + if (adap_emac->TXINTSTATRAW & 0x01) { ret_status = length; break; -- 1.6.0.4

3 2

[U-Boot] Notification Winning
by Promotion 16 Nov '09

16 Nov '09

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1 0

[U-Boot] [PATCH] Kirkwood: Makefile cleanup- fixed ordering (cosmetic change)
by Prafulla Wadaskar 16 Nov '09

16 Nov '09

As per coding guidlines, it is good to maintain proper ordering in the makefiles. This was missed during initial coding, corrected here. This was discovered during orion5x code review Thanks to Albert Aribaud for this. Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- cpu/arm926ejs/kirkwood/Makefile | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/arm926ejs/kirkwood/Makefile b/cpu/arm926ejs/kirkwood/Makefile index d73e210..fc2cc03 100644 --- a/cpu/arm926ejs/kirkwood/Makefile +++ b/cpu/arm926ejs/kirkwood/Makefile @@ -26,8 +26,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS-y = dram.o -COBJS-y += cpu.o +COBJS-y = cpu.o +COBJS-y += dram.o COBJS-y += mpp.o COBJS-y += timer.o -- 1.5.3.3

1 0

[U-Boot] [PATCH v3] DA8xx: Add MUSB host support
by Ajay Kumar Gupta 16 Nov '09

16 Nov '09

Tested USB host functionality on DA830 EVM. Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> Signed-off-by: Swaminathan S <swami.iyer(a)ti.com> --- Patch has updated licensing header.Other patch in series has no update so not reposting them untill I get any rework comment. drivers/usb/musb/Makefile | 1 + drivers/usb/musb/da8xx.c | 143 +++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/musb/da8xx.h | 84 ++++++++++++++++++++++++++ include/usb.h | 3 +- 4 files changed, 230 insertions(+), 1 deletions(-) create mode 100644 drivers/usb/musb/da8xx.c create mode 100644 drivers/usb/musb/da8xx.h diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile index 09e0a5f..eb4d8fd 100644 --- a/drivers/usb/musb/Makefile +++ b/drivers/usb/musb/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libusb_musb.a COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o COBJS-$(CONFIG_USB_DAVINCI) += davinci.o +COBJS-$(CONFIG_USB_DA8XX) += da8xx.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c new file mode 100644 index 0000000..3e4694f --- /dev/null +++ b/drivers/usb/musb/da8xx.c @@ -0,0 +1,143 @@ +/* + * da8xx.c - TI's DA8xx platform specific usb wrapper functions. + * + * Author: Ajay Kumar Gupta <ajay.gupta(a)ti.com> + * + * Based on drivers/usb/musb/davinci.c + * + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio_defs.h> + +#include "da8xx.h" + +/* MUSB platform configuration */ +struct musb_config musb_cfg = { + (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE, + DA8XX_USB_OTG_TIMEOUT, + 0 +}; + +/* + * This function enables VBUS by driving the GPIO Bank4 Pin 15 high. + */ +static void enable_vbus(void) +{ + u32 value; + + /* configure GPIO bank4 pin 15 in output direction */ + value = readl(&davinci_gpio_bank45->dir); + writel((value & (~DA8XX_USB_VBUS_GPIO)), &davinci_gpio_bank45->dir); + + /* set GPIO bank4 pin 15 high to drive VBUS */ + value = readl(&davinci_gpio_bank45->set_data); + writel((value | DA8XX_USB_VBUS_GPIO), &davinci_gpio_bank45->set_data); +} + +/* + * Enable the usb0 phy. This initialization procedure is explained in + * the DA8xx USB user guide document. + */ +static u8 phy_on(void) +{ + u32 timeout; + u32 cfgchip2; + + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + + cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | + CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ); + cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | + CFGCHIP2_REFFREQ_24MHZ; + + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); + + /* wait until the usb phy pll locks */ + timeout = musb_cfg.timeout; + while (timeout--) + if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) + return 1; + + /* USB phy was not turned on */ + return 0; +} + +/* + * Disable the usb phy + */ +static void phy_off(void) +{ + u32 cfgchip2; + + /* + * Power down the on-chip PHY. + */ + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + cfgchip2 &= ~CFGCHIP2_PHY_PLLON; + cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN; + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); +} + +/* + * This function performs DA8xx platform specific initialization for usb0. + */ +int musb_platform_init(void) +{ + u32 revision; + + /* enable psc for usb2.0 */ + lpsc_on(33); + + /* enable usb vbus */ + enable_vbus(); + + /* reset the controller */ + writel(0x1, (DA8XX_USB_OTG_BASE + DA8XX_USB_CTRL_REG)); + udelay(5000); + + /* start the on-chip usb phy and its pll */ + if (phy_on() == 0) + return -1; + + /* Returns zero if e.g. not clocked */ + revision = readl(DA8XX_USB_OTG_BASE + DA8XX_USB_VERSION_REG); + if (revision == 0) + return -1; + + /* Disable all interrupts */ + writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | + DA8XX_USB_RXINT_MASK), + (DA8XX_USB_OTG_BASE + DA8XX_USB_INT_MASK_SET_REG)); + return 0; +} + +/* + * This function performs DA8xx platform specific deinitialization for usb0. + */ +void musb_platform_deinit(void) +{ + /* Turn of the phy */ + phy_off(); + + /* flush any interrupts */ + writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | + DA8XX_USB_RXINT_MASK), + (DA8XX_USB_OTG_BASE + DA8XX_USB_INT_MASK_CLR_REG)); + writel(0, (DA8XX_USB_OTG_BASE + DA8XX_USB_EOI_REG)); +} diff --git a/drivers/usb/musb/da8xx.h b/drivers/usb/musb/da8xx.h new file mode 100644 index 0000000..c3e9c77 --- /dev/null +++ b/drivers/usb/musb/da8xx.h @@ -0,0 +1,84 @@ +/* + * da8xx.h -- TI's DA8xx platform specific usb wrapper definitions. + * + * Author: Ajay Kumar Gupta <ajay.gupta(a)ti.com> + * + * Based on drivers/usb/musb/davinci.h + * + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __DA8XX_MUSB_H__ +#define __DA8XX_MUSB_H__ + +#include "musb_core.h" + +/* extern functions */ +extern void lpsc_on(unsigned int id); + +/* Base address of da8xx usb0 wrapper */ +#define DA8XX_USB_OTG_BASE 0x01E00000 + +/* Base address of da8xx musb core */ +#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400) + +/* Timeout for DA8xx usb module */ +#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF + +/* For now include usb OTG module registers here */ +#define DA8XX_USB_VERSION_REG 0x00 +#define DA8XX_USB_CTRL_REG 0x04 +#define DA8XX_USB_INT_MASK_SET_REG 0x30 +#define DA8XX_USB_INT_MASK_CLR_REG 0x34 +#define DA8XX_USB_EOI_REG 0x3c + +#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ +#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ +#define DA8XX_USB_TXINT_SHIFT 0 +#define DA8XX_USB_RXINT_SHIFT 8 + +#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ +#define DA8XX_USB_TXINT_MASK \ + (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT) +#define DA8XX_USB_RXINT_MASK \ + (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) + +/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ +#define CFGCHIP2_PHYCLKGD (1 << 17) +#define CFGCHIP2_VBUSSENSE (1 << 16) +#define CFGCHIP2_RESET (1 << 15) +#define CFGCHIP2_OTGMODE (3 << 13) +#define CFGCHIP2_NO_OVERRIDE (0 << 13) +#define CFGCHIP2_FORCE_HOST (1 << 13) +#define CFGCHIP2_FORCE_DEVICE (2 << 13) +#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) +#define CFGCHIP2_USB1PHYCLKMUX (1 << 12) +#define CFGCHIP2_USB2PHYCLKMUX (1 << 11) +#define CFGCHIP2_PHYPWRDN (1 << 10) +#define CFGCHIP2_OTGPWRDN (1 << 9) +#define CFGCHIP2_DATPOL (1 << 8) +#define CFGCHIP2_USB1SUSPENDM (1 << 7) +#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ +#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ +#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ +#define CFGCHIP2_REFFREQ (0xf << 0) +#define CFGCHIP2_REFFREQ_12MHZ (1 << 0) +#define CFGCHIP2_REFFREQ_24MHZ (2 << 0) +#define CFGCHIP2_REFFREQ_48MHZ (3 << 0) + +#define DA8XX_USB_VBUS_GPIO (1 << 15) +#endif /* __DA8XX_MUSB_H__ */ + diff --git a/include/usb.h b/include/usb.h index 7c47098..7c56ace 100644 --- a/include/usb.h +++ b/include/usb.h @@ -183,7 +183,8 @@ struct usb_device { #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ - defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) + defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \ + defined(CONFIG_USB_DA8XX) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); -- 1.6.2.4

4 6

[U-Boot] [PATCHi v5] OMAP3: add CM-T35 board
by Mike Rapoport 16 Nov '09

16 Nov '09

CM-T35 is a system-on-module board from CompuLab, Ltd. The CM-T35 datasheet can be found at http://www.compulab.co.il/t35/html/t35-cm-datasheet.htm Signed-off-by: Mike Rapoport <mike(a)compulab.co.il> -- v2 changes: - rename board config file from omap3_cm-t35.h to cm-t35.h - remove SZ_xx references - add MAKEALL/MAINTEINERS entries v3 changes: - fix whitespace and indentation - remove eth_init from board_eth_init - add CM-T35 entry to doc/README.omap3 - fixed board name in MAINTAINERS v4 changes: - rebased agains u-boot-ti/next branch v5 changes: - rename board files to cm_t35 - add explicit setup of GPMC with SMNAND configuration - reorginize Ethernet initialization so that I2C related code will depend on I2C initialization --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 2 + board/cm_t35/Makefile | 47 +++++++ board/cm_t35/cm_t35.c | 216 +++++++++++++++++++++++++++++++++ board/cm_t35/cm_t35.h | 173 ++++++++++++++++++++++++++ board/cm_t35/config.mk | 30 +++++ doc/README.omap3 | 16 ++- include/configs/cm_t35.h | 299 ++++++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 786 insertions(+), 2 deletions(-) create mode 100644 board/cm_t35/Makefile create mode 100644 board/cm_t35/cm_t35.c create mode 100644 board/cm_t35/cm_t35.h create mode 100644 board/cm_t35/config.mk create mode 100644 include/configs/cm_t35.h diff --git a/MAINTAINERS b/MAINTAINERS index d70a9d2..94e45f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -677,6 +677,10 @@ Stelian Pop <stelian.pop(a)leadtechdesign.com> at91sam9263ek ARM926EJS (AT91SAM9263 SoC) at91sam9rlek ARM926EJS (AT91SAM9RL SoC) +Mike Rapoport <mike(a)compulab.co.il> + + cm_t35 ARM CORTEX-A8 (OMAP3xx SoC) + Tom Rix <Tom.Rix(a)windriver.com> omap3_zoom2 ARM CORTEX-A8 (OMAP3xx SoC) diff --git a/MAKEALL b/MAKEALL index d63c5c2..e131c62 100755 --- a/MAKEALL +++ b/MAKEALL @@ -612,6 +612,7 @@ LIST_ARM11=" \ ## ARM Cortex-A8 Systems ######################################################################### LIST_ARM_CORTEX_A8=" \ + cm_t35 \ devkit8000 \ omap3_beagle \ omap3_overo \ diff --git a/Makefile b/Makefile index bcb3fe9..9d6150a 100644 --- a/Makefile +++ b/Makefile @@ -3143,6 +3143,8 @@ SMN42_config : unconfig ######################################################################### ## ARM CORTEX Systems ######################################################################### +cm_t35_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 cm_t35 NULL omap3 devkit8000_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3 diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile new file mode 100644 index 0000000..320a817 --- /dev/null +++ b/board/cm_t35/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := cm_t35.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c new file mode 100644 index 0000000..0ba23cc --- /dev/null +++ b/board/cm_t35/cm_t35.c @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2009 + * CompuLab, Ltd. <www.compulab.co.il> + * + * Authors : + * Igor Vaisbein <igor(a)compulab.co.il> + * Mike Rapoport <mike(a)compulab.co.il> + * + * Derived from omap3evm and Beagle Board by + * Manikandan Pillai <mani.pillai(a)ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <net.h> +#include <i2c.h> +#include <twl4030.h> + +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> + +#include "cm_t35.h" + +static u32 gpmc_net_config[GPMC_MAX_REG] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, + 0 +}; + +static u32 gpmc_nand_config[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, + 0, +}; + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], + CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); + + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_CM_T35; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + */ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_CM_T35(); +} + +/* + * Routine: setup_net_chip_gmpc + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip_gmpc(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], + CM_T35_SMC911X_BASE, GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], + SB_T35_SMC911X_BASE, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); +} + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C +/* + * Routine: reset_net_chip + * Description: reset the Ethernet controller via TPS65930 GPIO + */ +static void reset_net_chip(void) +{ + /* Set GPIO1 of TPS65930 as output */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, + TWL4030_BASEADD_GPIO+0x03); + /* Send a pulse on the GPIO pin */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, + TWL4030_BASEADD_GPIO+0x0C); + udelay(1); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, + TWL4030_BASEADD_GPIO+0x09); + udelay(1); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, + TWL4030_BASEADD_GPIO+0x0C); +} +#else +static inline void reset_net_chip(void) {} +#endif + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int handle_mac_address(void) +{ + unsigned char enetaddr[6]; + int rc; + + memset(enetaddr, 0, 6); + rc = eth_getenv_enetaddr("ethaddr", enetaddr); + if (rc) + return 0; + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + rc = i2c_read(0x50, 0, 1, enetaddr, 6); + if (rc) + return rc; +#endif + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + + +/* + * Routine: board_eth_init + * Description: initialize module and base-board Ethernet chips + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0, rc1 = 0; + +#ifdef CONFIG_SMC911X + setup_net_chip_gmpc(); + reset_net_chip(); + + rc1 = handle_mac_address(); + if (rc1) + printf("CM-T35: No MAC address found\n"); + + rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE); + if (rc1 > 0) + rc++; + + rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); + if (rc1 > 0) + rc++; +#endif + + return rc; +} diff --git a/board/cm_t35/cm_t35.h b/board/cm_t35/cm_t35.h new file mode 100644 index 0000000..188ba42 --- /dev/null +++ b/board/cm_t35/cm_t35.h @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2009 CompuLab, Ltd + * Authors: + * Igor Vaisbein <igor(a)compulab.co.il> + * Mike Rapoport <mike(a)compulab.co.il> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CM_T35_H_ +#define _CM_T35_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "CM-T35 board", + "NAND", +}; + +/* static void setup_net_chip(void); */ + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_CM_T35() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + /* SB-T35 Ethernet */\ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\ + /* CM-T35 Ethernet */\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)) /*GPIO_59*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*WAIT0*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*CLKOUT1*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*green LED*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\ + +#endif diff --git a/board/cm_t35/config.mk b/board/cm_t35/config.mk new file mode 100644 index 0000000..a90c86a --- /dev/null +++ b/board/cm_t35/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2009 +# CompuLab, Ltd., <www.compulab.co.il> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/doc/README.omap3 b/doc/README.omap3 index 6227151..1c1c16f 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -21,6 +21,8 @@ Currently the following boards are supported: * TI/Logic PD Zoom 2 [7] +* CompuLab Ltd. CM-T35 [8] + Toolchain ========= @@ -61,6 +63,11 @@ make make omap3_zoom2_config make +* CM-T35: + +make cm_t35_config +make + Custom commands =============== @@ -119,7 +126,7 @@ To read a bit : Acknowledgements ================ -OMAP3 U-Boot is based on U-Boot tar ball [8] for BeagleBoard and EVM done by +OMAP3 U-Boot is based on U-Boot tar ball [9] for BeagleBoard and EVM done by several TI employees. Links @@ -153,6 +160,11 @@ http://www.logicpd.com/products/devkit/ti/zoom_mobile_development_kit [7] TI/Logic PD Zoom 2 http://www.logicpd.com/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Bri… -[8] TI OMAP3 U-Boot: + +[8] CompuLab Ltd. CM-T35: + +http://www.compulab.co.il/t35/html/t35-cm-datasheet.htm + +[9] TI OMAP3 U-Boot: http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h new file mode 100644 index 0000000..9c170ae --- /dev/null +++ b/include/configs/cm_t35.h @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2009 CompuLab, Ltd. + * + * Authors : + * Igor Vaisbein <igor(a)compulab.co.il> + * Mike Rapoport <mike(a)compulab.co.il> + * + * Derived from omap3evm and Beagle Board by + * Manikandan Pillai <mani.pillai(a)ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * Configuration settings for the CompuLab CM-T35 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_CM_T35 1 /* working with CM_T35 */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +/* DDR type - Micron */ +#define CONFIG_OMAP3_MICRON_DDR 1 + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* Size of malloc() pool */ +#define CONFIG_ENV_SIZE (128 << 10) /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ +/* NS16550 Configuration */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* serial console configuration */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_YAFFS2 /* YAFFS2 Support */ +#define CONFIG_CMD_UBI /* UBI Support */ +#define CONFIG_CMD_MTDPARTS + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* TWL4030 */ +#define CONFIG_TWL4030_POWER 1 + +/* Board NAND Info. */ +#define CONFIG_NAND_OMAP_GPMC 1 +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#define OMAP34XX_GPMC_NAND_SMNAND 1 + +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +/* JFFS2 */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* ubi/ubifs related definitions */ +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS + +/* Environment information */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTFILE uImage + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "baudrate=115200\0"\ + "console=ttyS2,115200n8\0" \ + "autoload=no\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "onenand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader)," \ + "1920k(u-boot)," \ + "256k(env)," \ + "4m(kernel)," \ + "-(fs)," + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "CM-T35 # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x08000000) + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */ +#endif + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may not be populated on CM-T35 */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/* PISMO support */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_IS_IN_NAND 1 + +/* environment */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr + +#ifndef __ASSEMBLY__ +extern struct gpmc *gpmc_cfg; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +/* SMSC9220 Ethernet */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CM_T35_SMC911X_BASE 0x2C000000 +#define SB_T35_SMC911X_BASE (CM_T35_SMC911X_BASE + (16 << 20)) +#endif /* (CONFIG_CMD_NET) */ + +#define CONFIG_OMAP3_GPIO_6 1 + +#endif /* __CONFIG_H */ -- 1.6.4.4

1 0

[U-Boot] [PATCH ARM v2] Clean-up of s3c24x0 header files
by kevin.morfitt＠fearnside-systems.co.uk 16 Nov '09

16 Nov '09

Cleans up the s3c24x0 header files: s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8, S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always accessed using the IO accessor functions which cast the register address as 'volatile' anyway so it isn't required here. s3c2400.h and s3c2410.h: insert a blank line between the static inline functions Signed-off-by: Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> --- v2 changes: remove the S3C24X0_REG8, S3C24X0_REG16 and S3C24X0_REG32 register typedef's from s3c24x0.h, s3c2400.h, s3c2410.h and vcma9.h board/mpl/vcma9/vcma9.h | 14 +- include/asm-arm/arch-s3c24x0/s3c2400.h | 16 + include/asm-arm/arch-s3c24x0/s3c2410.h | 17 + include/asm-arm/arch-s3c24x0/s3c24x0.h | 904 ++++++++++++++++---------------- 4 files changed, 490 insertions(+), 461 deletions(-) diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 9f32808..2c4305c 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -118,13 +118,13 @@ static inline u32 NF_Read_ECC(void) /* VCMA9 PLD regsiters */ typedef struct { - S3C24X0_REG8 ID; - S3C24X0_REG8 NIC; - S3C24X0_REG8 CAN; - S3C24X0_REG8 MISC; - S3C24X0_REG8 GPCD; - S3C24X0_REG8 BOARD; - S3C24X0_REG8 SDRAM; + u8 ID; + u8 NIC; + u8 CAN; + u8 MISC; + u8 GPCD; + u8 BOARD; + u8 SDRAM; } /*__attribute__((__packed__))*/ VCMA9_PLD; #define VCMA9_PLD_BASE 0x2C000100 diff --git a/include/asm-arm/arch-s3c24x0/s3c2400.h b/include/asm-arm/arch-s3c24x0/s3c2400.h index 26bd4e4..2678be1 100644 --- a/include/asm-arm/arch-s3c24x0/s3c2400.h +++ b/include/asm-arm/arch-s3c24x0/s3c2400.h @@ -67,67 +67,83 @@ static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) { return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; } + static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) { return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; } + static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) { return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; } + static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) { return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; } + static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) { return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; } + static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) { return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } + static inline struct s3c24x0_uart *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) { return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); } + static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) { return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; } + static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) { return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; } + static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) { return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; } + static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) { return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; } + static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) { return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; } + static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) { return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; } + static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) { return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; } + static inline struct s3c2400_adc *s3c2400_get_base_adc(void) { return (struct s3c2400_adc *)S3C24X0_ADC_BASE; } + static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) { return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } + static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) { return (struct s3c2400_mmc *)S3C2400_MMC_BASE; diff --git a/include/asm-arm/arch-s3c24x0/s3c2410.h b/include/asm-arm/arch-s3c24x0/s3c2410.h index be2e76e..0543fe1 100644 --- a/include/asm-arm/arch-s3c24x0/s3c2410.h +++ b/include/asm-arm/arch-s3c24x0/s3c2410.h @@ -73,71 +73,88 @@ static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) { return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; } + static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) { return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; } + static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) { return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; } + static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) { return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; } + static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) { return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; } + static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) { return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } + static inline struct s3c2410_nand *s3c2410_get_base_nand(void) { return (struct s3c2410_nand *)S3C2410_NAND_BASE; } + static inline struct s3c24x0_uart *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) { return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); } + static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) { return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; } + static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) { return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; } + static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) { return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; } + static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) { return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; } + static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) { return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; } + static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) { return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; } + static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) { return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; } + static inline struct s3c2410_adc *s3c2410_get_base_adc(void) { return (struct s3c2410_adc *)S3C2410_ADC_BASE; } + static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) { return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } + static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) { return (struct s3c2410_sdi *)S3C2410_SDI_BASE; diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h index 56a551a..15f53dd 100644 --- a/include/asm-arm/arch-s3c24x0/s3c24x0.h +++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h @@ -31,84 +31,80 @@ #ifndef __S3C24X0_H__ #define __S3C24X0_H__ -typedef volatile u8 S3C24X0_REG8; -typedef volatile u16 S3C24X0_REG16; -typedef volatile u32 S3C24X0_REG32; - /* Memory controller (see manual chapter 5) */ struct s3c24x0_memctl { - S3C24X0_REG32 BWSCON; - S3C24X0_REG32 BANKCON[8]; - S3C24X0_REG32 REFRESH; - S3C24X0_REG32 BANKSIZE; - S3C24X0_REG32 MRSRB6; - S3C24X0_REG32 MRSRB7; + u32 BWSCON; + u32 BANKCON[8]; + u32 REFRESH; + u32 BANKSIZE; + u32 MRSRB6; + u32 MRSRB7; }; /* USB HOST (see manual chapter 12) */ struct s3c24x0_usb_host { - S3C24X0_REG32 HcRevision; - S3C24X0_REG32 HcControl; - S3C24X0_REG32 HcCommonStatus; - S3C24X0_REG32 HcInterruptStatus; - S3C24X0_REG32 HcInterruptEnable; - S3C24X0_REG32 HcInterruptDisable; - S3C24X0_REG32 HcHCCA; - S3C24X0_REG32 HcPeriodCuttendED; - S3C24X0_REG32 HcControlHeadED; - S3C24X0_REG32 HcControlCurrentED; - S3C24X0_REG32 HcBulkHeadED; - S3C24X0_REG32 HcBuldCurrentED; - S3C24X0_REG32 HcDoneHead; - S3C24X0_REG32 HcRmInterval; - S3C24X0_REG32 HcFmRemaining; - S3C24X0_REG32 HcFmNumber; - S3C24X0_REG32 HcPeriodicStart; - S3C24X0_REG32 HcLSThreshold; - S3C24X0_REG32 HcRhDescriptorA; - S3C24X0_REG32 HcRhDescriptorB; - S3C24X0_REG32 HcRhStatus; - S3C24X0_REG32 HcRhPortStatus1; - S3C24X0_REG32 HcRhPortStatus2; + u32 HcRevision; + u32 HcControl; + u32 HcCommonStatus; + u32 HcInterruptStatus; + u32 HcInterruptEnable; + u32 HcInterruptDisable; + u32 HcHCCA; + u32 HcPeriodCuttendED; + u32 HcControlHeadED; + u32 HcControlCurrentED; + u32 HcBulkHeadED; + u32 HcBuldCurrentED; + u32 HcDoneHead; + u32 HcRmInterval; + u32 HcFmRemaining; + u32 HcFmNumber; + u32 HcPeriodicStart; + u32 HcLSThreshold; + u32 HcRhDescriptorA; + u32 HcRhDescriptorB; + u32 HcRhStatus; + u32 HcRhPortStatus1; + u32 HcRhPortStatus2; }; /* INTERRUPT (see manual chapter 14) */ struct s3c24x0_interrupt { - S3C24X0_REG32 SRCPND; - S3C24X0_REG32 INTMOD; - S3C24X0_REG32 INTMSK; - S3C24X0_REG32 PRIORITY; - S3C24X0_REG32 INTPND; - S3C24X0_REG32 INTOFFSET; + u32 SRCPND; + u32 INTMOD; + u32 INTMSK; + u32 PRIORITY; + u32 INTPND; + u32 INTOFFSET; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 SUBSRCPND; - S3C24X0_REG32 INTSUBMSK; + u32 SUBSRCPND; + u32 INTSUBMSK; #endif }; /* DMAS (see manual chapter 8) */ struct s3c24x0_dma { - S3C24X0_REG32 DISRC; + u32 DISRC; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 DISRCC; + u32 DISRCC; #endif - S3C24X0_REG32 DIDST; + u32 DIDST; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 DIDSTC; + u32 DIDSTC; #endif - S3C24X0_REG32 DCON; - S3C24X0_REG32 DSTAT; - S3C24X0_REG32 DCSRC; - S3C24X0_REG32 DCDST; - S3C24X0_REG32 DMASKTRIG; + u32 DCON; + u32 DSTAT; + u32 DCSRC; + u32 DCDST; + u32 DMASKTRIG; #ifdef CONFIG_S3C2400 - S3C24X0_REG32 res[1]; + u32 res[1]; #endif #ifdef CONFIG_S3C2410 - S3C24X0_REG32 res[7]; + u32 res[7]; #endif }; @@ -120,201 +116,201 @@ struct s3c24x0_dmas { /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ struct s3c24x0_clock_power { - S3C24X0_REG32 LOCKTIME; - S3C24X0_REG32 MPLLCON; - S3C24X0_REG32 UPLLCON; - S3C24X0_REG32 CLKCON; - S3C24X0_REG32 CLKSLOW; - S3C24X0_REG32 CLKDIVN; + u32 LOCKTIME; + u32 MPLLCON; + u32 UPLLCON; + u32 CLKCON; + u32 CLKSLOW; + u32 CLKDIVN; }; /* LCD CONTROLLER (see manual chapter 15) */ struct s3c24x0_lcd { - S3C24X0_REG32 LCDCON1; - S3C24X0_REG32 LCDCON2; - S3C24X0_REG32 LCDCON3; - S3C24X0_REG32 LCDCON4; - S3C24X0_REG32 LCDCON5; - S3C24X0_REG32 LCDSADDR1; - S3C24X0_REG32 LCDSADDR2; - S3C24X0_REG32 LCDSADDR3; - S3C24X0_REG32 REDLUT; - S3C24X0_REG32 GREENLUT; - S3C24X0_REG32 BLUELUT; - S3C24X0_REG32 res[8]; - S3C24X0_REG32 DITHMODE; - S3C24X0_REG32 TPAL; + u32 LCDCON1; + u32 LCDCON2; + u32 LCDCON3; + u32 LCDCON4; + u32 LCDCON5; + u32 LCDSADDR1; + u32 LCDSADDR2; + u32 LCDSADDR3; + u32 REDLUT; + u32 GREENLUT; + u32 BLUELUT; + u32 res[8]; + u32 DITHMODE; + u32 TPAL; #ifdef CONFIG_S3C2410 - S3C24X0_REG32 LCDINTPND; - S3C24X0_REG32 LCDSRCPND; - S3C24X0_REG32 LCDINTMSK; - S3C24X0_REG32 LPCSEL; + u32 LCDINTPND; + u32 LCDSRCPND; + u32 LCDINTMSK; + u32 LPCSEL; #endif }; /* NAND FLASH (see S3C2410 manual chapter 6) */ struct s3c2410_nand { - S3C24X0_REG32 NFCONF; - S3C24X0_REG32 NFCMD; - S3C24X0_REG32 NFADDR; - S3C24X0_REG32 NFDATA; - S3C24X0_REG32 NFSTAT; - S3C24X0_REG32 NFECC; + u32 NFCONF; + u32 NFCMD; + u32 NFADDR; + u32 NFDATA; + u32 NFSTAT; + u32 NFECC; }; /* UART (see manual chapter 11) */ struct s3c24x0_uart { - S3C24X0_REG32 ULCON; - S3C24X0_REG32 UCON; - S3C24X0_REG32 UFCON; - S3C24X0_REG32 UMCON; - S3C24X0_REG32 UTRSTAT; - S3C24X0_REG32 UERSTAT; - S3C24X0_REG32 UFSTAT; - S3C24X0_REG32 UMSTAT; + u32 ULCON; + u32 UCON; + u32 UFCON; + u32 UMCON; + u32 UTRSTAT; + u32 UERSTAT; + u32 UFSTAT; + u32 UMSTAT; #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 URXH; + u8 res1[3]; + u8 UTXH; + u8 res2[3]; + u8 URXH; #else /* Little Endian */ - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 URXH; - S3C24X0_REG8 res2[3]; + u8 UTXH; + u8 res1[3]; + u8 URXH; + u8 res2[3]; #endif - S3C24X0_REG32 UBRDIV; + u32 UBRDIV; }; /* PWM TIMER (see manual chapter 10) */ struct s3c24x0_timer { - S3C24X0_REG32 TCNTB; - S3C24X0_REG32 TCMPB; - S3C24X0_REG32 TCNTO; + u32 TCNTB; + u32 TCMPB; + u32 TCNTO; }; struct s3c24x0_timers { - S3C24X0_REG32 TCFG0; - S3C24X0_REG32 TCFG1; - S3C24X0_REG32 TCON; + u32 TCFG0; + u32 TCFG1; + u32 TCON; struct s3c24x0_timer ch[4]; - S3C24X0_REG32 TCNTB4; - S3C24X0_REG32 TCNTO4; + u32 TCNTB4; + u32 TCNTO4; }; /* USB DEVICE (see manual chapter 13) */ struct s3c24x0_usb_dev_fifos { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 EP_FIFO_REG; + u8 res[3]; + u8 EP_FIFO_REG; #else /* little endian */ - S3C24X0_REG8 EP_FIFO_REG; - S3C24X0_REG8 res[3]; + u8 EP_FIFO_REG; + u8 res[3]; #endif }; struct s3c24x0_usb_dev_dmas { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 EP_DMA_TTC_H; + u8 res1[3]; + u8 EP_DMA_CON; + u8 res2[3]; + u8 EP_DMA_UNIT; + u8 res3[3]; + u8 EP_DMA_FIFO; + u8 res4[3]; + u8 EP_DMA_TTC_L; + u8 res5[3]; + u8 EP_DMA_TTC_M; + u8 res6[3]; + u8 EP_DMA_TTC_H; #else /* little endian */ - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_H; - S3C24X0_REG8 res6[3]; + u8 EP_DMA_CON; + u8 res1[3]; + u8 EP_DMA_UNIT; + u8 res2[3]; + u8 EP_DMA_FIFO; + u8 res3[3]; + u8 EP_DMA_TTC_L; + u8 res4[3]; + u8 EP_DMA_TTC_M; + u8 res5[3]; + u8 EP_DMA_TTC_H; + u8 res6[3]; #endif }; struct s3c24x0_usb_device { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res4[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res6[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; + u8 res1[3]; + u8 FUNC_ADDR_REG; + u8 res2[3]; + u8 PWR_REG; + u8 res3[3]; + u8 EP_INT_REG; + u8 res4[15]; + u8 USB_INT_REG; + u8 res5[3]; + u8 EP_INT_EN_REG; + u8 res6[15]; + u8 USB_INT_EN_REG; + u8 res7[3]; + u8 FRAME_NUM1_REG; + u8 res8[3]; + u8 FRAME_NUM2_REG; + u8 res9[3]; + u8 INDEX_REG; + u8 res10[7]; + u8 MAXP_REG; + u8 res11[3]; + u8 EP0_CSR_IN_CSR1_REG; + u8 res12[3]; + u8 IN_CSR2_REG; + u8 res13[7]; + u8 OUT_CSR1_REG; + u8 res14[3]; + u8 OUT_CSR2_REG; + u8 res15[3]; + u8 OUT_FIFO_CNT1_REG; + u8 res16[3]; + u8 OUT_FIFO_CNT2_REG; #else /* little endian */ - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res3[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res5[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res9[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; - S3C24X0_REG8 res16[3]; + u8 FUNC_ADDR_REG; + u8 res1[3]; + u8 PWR_REG; + u8 res2[3]; + u8 EP_INT_REG; + u8 res3[15]; + u8 USB_INT_REG; + u8 res4[3]; + u8 EP_INT_EN_REG; + u8 res5[15]; + u8 USB_INT_EN_REG; + u8 res6[3]; + u8 FRAME_NUM1_REG; + u8 res7[3]; + u8 FRAME_NUM2_REG; + u8 res8[3]; + u8 INDEX_REG; + u8 res9[7]; + u8 MAXP_REG; + u8 res10[7]; + u8 EP0_CSR_IN_CSR1_REG; + u8 res11[3]; + u8 IN_CSR2_REG; + u8 res12[3]; + u8 OUT_CSR1_REG; + u8 res13[7]; + u8 OUT_CSR2_REG; + u8 res14[3]; + u8 OUT_FIFO_CNT1_REG; + u8 res15[3]; + u8 OUT_FIFO_CNT2_REG; + u8 res16[3]; #endif /* __BIG_ENDIAN */ struct s3c24x0_usb_dev_fifos fifo[5]; struct s3c24x0_usb_dev_dmas dma[5]; @@ -323,45 +319,45 @@ struct s3c24x0_usb_device { /* WATCH DOG TIMER (see manual chapter 18) */ struct s3c24x0_watchdog { - S3C24X0_REG32 WTCON; - S3C24X0_REG32 WTDAT; - S3C24X0_REG32 WTCNT; + u32 WTCON; + u32 WTDAT; + u32 WTCNT; }; /* IIC (see manual chapter 20) */ struct s3c24x0_i2c { - S3C24X0_REG32 IICCON; - S3C24X0_REG32 IICSTAT; - S3C24X0_REG32 IICADD; - S3C24X0_REG32 IICDS; + u32 IICCON; + u32 IICSTAT; + u32 IICADD; + u32 IICDS; }; /* IIS (see manual chapter 21) */ struct s3c24x0_i2s { #ifdef __BIG_ENDIAN - S3C24X0_REG16 res1; - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res5; - S3C24X0_REG16 IISFIFO; + u16 res1; + u16 IISCON; + u16 res2; + u16 IISMOD; + u16 res3; + u16 IISPSR; + u16 res4; + u16 IISFCON; + u16 res5; + u16 IISFIFO; #else /* little endian */ - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res1; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFIFO; - S3C24X0_REG16 res5; + u16 IISCON; + u16 res1; + u16 IISMOD; + u16 res2; + u16 IISPSR; + u16 res3; + u16 IISFCON; + u16 res4; + u16 IISFIFO; + u16 res5; #endif }; @@ -369,87 +365,87 @@ struct s3c24x0_i2s { /* I/O PORT (see manual chapter 9) */ struct s3c24x0_gpio { #ifdef CONFIG_S3C2400 - S3C24X0_REG32 PACON; - S3C24X0_REG32 PADAT; + u32 PACON; + u32 PADAT; - S3C24X0_REG32 PBCON; - S3C24X0_REG32 PBDAT; - S3C24X0_REG32 PBUP; + u32 PBCON; + u32 PBDAT; + u32 PBUP; - S3C24X0_REG32 PCCON; - S3C24X0_REG32 PCDAT; - S3C24X0_REG32 PCUP; + u32 PCCON; + u32 PCDAT; + u32 PCUP; - S3C24X0_REG32 PDCON; - S3C24X0_REG32 PDDAT; - S3C24X0_REG32 PDUP; + u32 PDCON; + u32 PDDAT; + u32 PDUP; - S3C24X0_REG32 PECON; - S3C24X0_REG32 PEDAT; - S3C24X0_REG32 PEUP; + u32 PECON; + u32 PEDAT; + u32 PEUP; - S3C24X0_REG32 PFCON; - S3C24X0_REG32 PFDAT; - S3C24X0_REG32 PFUP; + u32 PFCON; + u32 PFDAT; + u32 PFUP; - S3C24X0_REG32 PGCON; - S3C24X0_REG32 PGDAT; - S3C24X0_REG32 PGUP; + u32 PGCON; + u32 PGDAT; + u32 PGUP; - S3C24X0_REG32 OPENCR; + u32 OPENCR; - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 EXTINT; + u32 MISCCR; + u32 EXTINT; #endif #ifdef CONFIG_S3C2410 - S3C24X0_REG32 GPACON; - S3C24X0_REG32 GPADAT; - S3C24X0_REG32 res1[2]; - S3C24X0_REG32 GPBCON; - S3C24X0_REG32 GPBDAT; - S3C24X0_REG32 GPBUP; - S3C24X0_REG32 res2; - S3C24X0_REG32 GPCCON; - S3C24X0_REG32 GPCDAT; - S3C24X0_REG32 GPCUP; - S3C24X0_REG32 res3; - S3C24X0_REG32 GPDCON; - S3C24X0_REG32 GPDDAT; - S3C24X0_REG32 GPDUP; - S3C24X0_REG32 res4; - S3C24X0_REG32 GPECON; - S3C24X0_REG32 GPEDAT; - S3C24X0_REG32 GPEUP; - S3C24X0_REG32 res5; - S3C24X0_REG32 GPFCON; - S3C24X0_REG32 GPFDAT; - S3C24X0_REG32 GPFUP; - S3C24X0_REG32 res6; - S3C24X0_REG32 GPGCON; - S3C24X0_REG32 GPGDAT; - S3C24X0_REG32 GPGUP; - S3C24X0_REG32 res7; - S3C24X0_REG32 GPHCON; - S3C24X0_REG32 GPHDAT; - S3C24X0_REG32 GPHUP; - S3C24X0_REG32 res8; - - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 DCLKCON; - S3C24X0_REG32 EXTINT0; - S3C24X0_REG32 EXTINT1; - S3C24X0_REG32 EXTINT2; - S3C24X0_REG32 EINTFLT0; - S3C24X0_REG32 EINTFLT1; - S3C24X0_REG32 EINTFLT2; - S3C24X0_REG32 EINTFLT3; - S3C24X0_REG32 EINTMASK; - S3C24X0_REG32 EINTPEND; - S3C24X0_REG32 GSTATUS0; - S3C24X0_REG32 GSTATUS1; - S3C24X0_REG32 GSTATUS2; - S3C24X0_REG32 GSTATUS3; - S3C24X0_REG32 GSTATUS4; + u32 GPACON; + u32 GPADAT; + u32 res1[2]; + u32 GPBCON; + u32 GPBDAT; + u32 GPBUP; + u32 res2; + u32 GPCCON; + u32 GPCDAT; + u32 GPCUP; + u32 res3; + u32 GPDCON; + u32 GPDDAT; + u32 GPDUP; + u32 res4; + u32 GPECON; + u32 GPEDAT; + u32 GPEUP; + u32 res5; + u32 GPFCON; + u32 GPFDAT; + u32 GPFUP; + u32 res6; + u32 GPGCON; + u32 GPGDAT; + u32 GPGUP; + u32 res7; + u32 GPHCON; + u32 GPHDAT; + u32 GPHUP; + u32 res8; + + u32 MISCCR; + u32 DCLKCON; + u32 EXTINT0; + u32 EXTINT1; + u32 EXTINT2; + u32 EINTFLT0; + u32 EINTFLT1; + u32 EINTFLT2; + u32 EINTFLT3; + u32 EINTMASK; + u32 EINTPEND; + u32 GSTATUS0; + u32 GSTATUS1; + u32 GSTATUS2; + u32 GSTATUS3; + u32 GSTATUS4; #endif }; @@ -457,112 +453,112 @@ struct s3c24x0_gpio { /* RTC (see manual chapter 17) */ struct s3c24x0_rtc { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[67]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res3[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res17[3]; - S3C24X0_REG8 BCDYEAR; + u8 res1[67]; + u8 RTCCON; + u8 res2[3]; + u8 TICNT; + u8 res3[11]; + u8 RTCALM; + u8 res4[3]; + u8 ALMSEC; + u8 res5[3]; + u8 ALMMIN; + u8 res6[3]; + u8 ALMHOUR; + u8 res7[3]; + u8 ALMDATE; + u8 res8[3]; + u8 ALMMON; + u8 res9[3]; + u8 ALMYEAR; + u8 res10[3]; + u8 RTCRST; + u8 res11[3]; + u8 BCDSEC; + u8 res12[3]; + u8 BCDMIN; + u8 res13[3]; + u8 BCDHOUR; + u8 res14[3]; + u8 BCDDATE; + u8 res15[3]; + u8 BCDDAY; + u8 res16[3]; + u8 BCDMON; + u8 res17[3]; + u8 BCDYEAR; #else /* little endian */ - S3C24X0_REG8 res0[64]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res2[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDYEAR; - S3C24X0_REG8 res17[3]; + u8 res0[64]; + u8 RTCCON; + u8 res1[3]; + u8 TICNT; + u8 res2[11]; + u8 RTCALM; + u8 res3[3]; + u8 ALMSEC; + u8 res4[3]; + u8 ALMMIN; + u8 res5[3]; + u8 ALMHOUR; + u8 res6[3]; + u8 ALMDATE; + u8 res7[3]; + u8 ALMMON; + u8 res8[3]; + u8 ALMYEAR; + u8 res9[3]; + u8 RTCRST; + u8 res10[3]; + u8 BCDSEC; + u8 res11[3]; + u8 BCDMIN; + u8 res12[3]; + u8 BCDHOUR; + u8 res13[3]; + u8 BCDDATE; + u8 res14[3]; + u8 BCDDAY; + u8 res15[3]; + u8 BCDMON; + u8 res16[3]; + u8 BCDYEAR; + u8 res17[3]; #endif }; /* ADC (see manual chapter 16) */ struct s3c2400_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCDAT; + u32 ADCCON; + u32 ADCDAT; }; /* ADC (see manual chapter 16) */ struct s3c2410_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCTSC; - S3C24X0_REG32 ADCDLY; - S3C24X0_REG32 ADCDAT0; - S3C24X0_REG32 ADCDAT1; + u32 ADCCON; + u32 ADCTSC; + u32 ADCDLY; + u32 ADCDAT0; + u32 ADCDAT1; }; /* SPI (see manual chapter 22) */ struct s3c24x0_spi_channel { - S3C24X0_REG8 SPCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 SPSTA; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 SPPIN; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 SPPRE; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 SPTDAT; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 SPRDAT; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 res7[16]; + u8 SPCON; + u8 res1[3]; + u8 SPSTA; + u8 res2[3]; + u8 SPPIN; + u8 res3[3]; + u8 SPPRE; + u8 res4[3]; + u8 SPTDAT; + u8 res5[3]; + u8 SPRDAT; + u8 res6[3]; + u8 res7[16]; }; struct s3c24x0_spi { @@ -573,84 +569,84 @@ struct s3c24x0_spi { /* MMC INTERFACE (see S3C2400 manual chapter 19) */ struct s3c2400_mmc { #ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG16 res5; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 MMPRE; - S3C24X0_REG16 res7; - S3C24X0_REG16 MMLEN; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 MMCR7; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 res10; - S3C24X0_REG16 MMCR16; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 MMDAT; + u8 res1[3]; + u8 MMCON; + u8 res2[3]; + u8 MMCRR; + u8 res3[3]; + u8 MMFCON; + u8 res4[3]; + u8 MMSTA; + u16 res5; + u16 MMFSTA; + u8 res6[3]; + u8 MMPRE; + u16 res7; + u16 MMLEN; + u8 res8[3]; + u8 MMCR7; + u32 MMRSP[4]; + u8 res9[3]; + u8 MMCMD0; + u32 MMCMD1; + u16 res10; + u16 MMCR16; + u8 res11[3]; + u8 MMDAT; #else - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG8 res4[3]; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG16 res5; - S3C24X0_REG8 MMPRE; - S3C24X0_REG8 res6[3]; - S3C24X0_REG16 MMLEN; - S3C24X0_REG16 res7; - S3C24X0_REG8 MMCR7; - S3C24X0_REG8 res8[3]; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG8 res9[3]; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 MMCR16; - S3C24X0_REG16 res10; - S3C24X0_REG8 MMDAT; - S3C24X0_REG8 res11[3]; + u8 MMCON; + u8 res1[3]; + u8 MMCRR; + u8 res2[3]; + u8 MMFCON; + u8 res3[3]; + u8 MMSTA; + u8 res4[3]; + u16 MMFSTA; + u16 res5; + u8 MMPRE; + u8 res6[3]; + u16 MMLEN; + u16 res7; + u8 MMCR7; + u8 res8[3]; + u32 MMRSP[4]; + u8 MMCMD0; + u8 res9[3]; + u32 MMCMD1; + u16 MMCR16; + u16 res10; + u8 MMDAT; + u8 res11[3]; #endif }; /* SD INTERFACE (see S3C2410 manual chapter 19) */ struct s3c2410_sdi { - S3C24X0_REG32 SDICON; - S3C24X0_REG32 SDIPRE; - S3C24X0_REG32 SDICARG; - S3C24X0_REG32 SDICCON; - S3C24X0_REG32 SDICSTA; - S3C24X0_REG32 SDIRSP0; - S3C24X0_REG32 SDIRSP1; - S3C24X0_REG32 SDIRSP2; - S3C24X0_REG32 SDIRSP3; - S3C24X0_REG32 SDIDTIMER; - S3C24X0_REG32 SDIBSIZE; - S3C24X0_REG32 SDIDCON; - S3C24X0_REG32 SDIDCNT; - S3C24X0_REG32 SDIDSTA; - S3C24X0_REG32 SDIFSTA; + u32 SDICON; + u32 SDIPRE; + u32 SDICARG; + u32 SDICCON; + u32 SDICSTA; + u32 SDIRSP0; + u32 SDIRSP1; + u32 SDIRSP2; + u32 SDIRSP3; + u32 SDIDTIMER; + u32 SDIBSIZE; + u32 SDIDCON; + u32 SDIDCNT; + u32 SDIDSTA; + u32 SDIFSTA; #ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 SDIDAT; + u8 res[3]; + u8 SDIDAT; #else - S3C24X0_REG8 SDIDAT; - S3C24X0_REG8 res[3]; + u8 SDIDAT; + u8 res[3]; #endif - S3C24X0_REG32 SDIIMSK; + u32 SDIIMSK; }; #endif /*__S3C24X0_H__*/ -- 1.6.0.6

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[U-Boot] [STATUS] Release date slippage
by Wolfgang Denk 15 Nov '09

15 Nov '09

Hello everybody, I'm afraid we will have to shift the release of v2009.11 by about two weeks. I'm currently targeting a release date of December 02, 2009. Due to personal reasons I didn;t find much time lately to apply the patches / bug fixes that should go into the upcopming release, and to push out the next release candidate to aollow for broader testing. I'm sorry for that. I hope I will be able to catch up in the next few days. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Remember that Beethoven wrote his first symphony in C ...

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