November 2009 - U-Boot

[U-Boot] [PATCH] S3C6400/SMDK6400: fix stack_setup in start.S
by "Seunghyeon Rhee (이승현)" 02 Nov '09

02 Nov '09

stack_setup is modified to initialize the stack on the correct address in DRAM accroding to the typical memory configuration described in README and the related CONFIG_* macro definitions. This makes macro CONFIG_MEMORY_UPPER_CODE no longer necessry. This was introduced and used only by this board for some unclear reason. The definition of this macro is removed because it's not referenced elsewhere. Signed-off-by: Seunghyeon Rhee <seunghyeon(a)lpmtec.com> --- cpu/arm1176/start.S | 7 +------ include/configs/smdk6400.h | 2 -- 2 files changed, 1 insertions(+), 8 deletions(-) diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index cb891df..1ecb3b9 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -241,16 +241,11 @@ mmu_enable: skip_hw_init: /* Set up the stack */ stack_setup: -#ifdef CONFIG_MEMORY_UPPER_CODE - ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc) -#else - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ sub sp, r0, #12 /* leave 3 words for abort-stack */ -#endif - clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index f6e1221..f644cd2 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -49,8 +49,6 @@ #define CONFIG_ENABLE_MMU #endif -#define CONFIG_MEMORY_UPPER_CODE - #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -- 1.6.2.5 -- Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657

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Re: [U-Boot] [PATCH] sheevaplug: correct SDRAM address control register value
by Tom 02 Nov '09

02 Nov '09

Prafulla Wadaskar wrote: > Hi Tom > > Please pull > > The following changes since commit 21e0b054c4285f7a497ac4510acf0ae90a28eae0: > Tom Rix (1): > ARM Update mach-types.h > > are available in the git repository at: > > u-boot-marvell.git on next branch ..BRANCH.NOT.VERIFIED.. > > Mark Asselstine (1): > sheevaplug: correct SDRAM address control register > > board/Marvell/sheevaplug/kwbimage.cfg | 10 +++++----- > 1 files changed, 5 insertions(+), 5 deletions(- > > Regards.. > Prafulla . . > I have pushed this to arm/next. Thanks. Tom

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[U-Boot] [PATCH-ARM 3/3] Add Support for the SBC2440-II Board
by kevin.morfitt＠fearnside-systems.co.uk 02 Nov '09

02 Nov '09

This patch adds support for the Embest SBC2440-II Board. Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/embest/sbc2440ii/Makefile | 55 +++++++ board/embest/sbc2440ii/config.mk | 25 +++ board/embest/sbc2440ii/lowlevel_init.S | 219 +++++++++++++++++++++++++++ board/embest/sbc2440ii/sbc2440ii.c | 122 +++++++++++++++ cpu/arm920t/s3c24x0/timer.c | 1 + include/configs/sbc2440ii.h | 254 ++++++++++++++++++++++++++++++++ 9 files changed, 684 insertions(+), 0 deletions(-) create mode 100644 board/embest/sbc2440ii/Makefile create mode 100644 board/embest/sbc2440ii/config.mk create mode 100644 board/embest/sbc2440ii/lowlevel_init.S create mode 100644 board/embest/sbc2440ii/sbc2440ii.c create mode 100644 include/configs/sbc2440ii.h diff --git a/MAINTAINERS b/MAINTAINERS index d70a9d2..65f8dfe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -638,6 +638,10 @@ Nishanth Menon <nm(a)ti.com> omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC) omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC) +Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> + + sbc2440ii ARM920T + David Müller <d.mueller(a)elsoft.ch> smdk2410 ARM920T diff --git a/MAKEALL b/MAKEALL index 5492d8f..c84b23e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -552,6 +552,7 @@ LIST_ARM9=" \ openrd_base \ rd6281a \ sbc2410x \ + sbc2440ii \ scb9328 \ sheevaplug \ smdk2400 \ diff --git a/Makefile b/Makefile index b91b1c0..a6619e5 100644 --- a/Makefile +++ b/Makefile @@ -3020,6 +3020,9 @@ rd6281a_config: unconfig sbc2410x_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 +sbc2440ii_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t sbc2440ii embest s3c24x0 + scb9328_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx diff --git a/board/embest/sbc2440ii/Makefile b/board/embest/sbc2440ii/Makefile new file mode 100644 index 0000000..26237a2 --- /dev/null +++ b/board/embest/sbc2440ii/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by: +# (C) Copyright 2009 +# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sbc2440ii.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/embest/sbc2440ii/config.mk b/board/embest/sbc2440ii/config.mk new file mode 100644 index 0000000..def11d8 --- /dev/null +++ b/board/embest/sbc2440ii/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# +# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by: +# (C) Copyright 2009 +# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + +# +# SBC2440-II has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3800'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# +# we load ourself to 33F8'0000 +# +# download area is 3000'0000 + +TEXT_BASE = 0x33F80000 diff --git a/board/embest/sbc2440ii/lowlevel_init.S b/board/embest/sbc2440ii/lowlevel_init.S new file mode 100644 index 0000000..95f49f8 --- /dev/null +++ b/board/embest/sbc2440ii/lowlevel_init.S @@ -0,0 +1,219 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +/* + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar(a)sec.samsung.com> + */ + +#define BWSCON 0x48000000 + +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1 << 2) +#define UBLB (0x1 << 3) + +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) +#define BWSCON_VAL ((B1_BWSCON << 4) + (B2_BWSCON << 8) + \ + (B3_BWSCON << 12) + (B4_BWSCON << 16) + \ + (B5_BWSCON << 20) + (B6_BWSCON << 24) + \ + (B7_BWSCON << 28)) + +#define B0_TACS 0x0 +#define B0_TCOS 0x0 +#define B0_TACC 0x7 +#define B0_TCOH 0x0 +#define B0_TAH 0x0 +#define B0_TACP 0x0 +#define B0_PMC 0x0 +#define BANKCON0_VAL ((B0_TACS << 13) + (B0_TCOS << 11) + (B0_TACC << 8) + \ + (B0_TCOH << 6) + (B0_TAH << 4) + (B0_TACP << 2) + \ + B0_PMC) + +#define B1_TACS 0x0 +#define B1_TCOS 0x0 +#define B1_TACC 0x7 +#define B1_TCOH 0x0 +#define B1_TAH 0x0 +#define B1_TACP 0x0 +#define B1_PMC 0x0 +#define BANKCON1_VAL ((B1_TACS << 13) + (B1_TCOS << 11) + (B1_TACC << 8) + \ + (B1_TCOH << 6) + (B1_TAH << 4) + (B1_TACP << 2) + \ + B1_PMC) + +#define B2_TACS 0x0 +#define B2_TCOS 0x0 +#define B2_TACC 0x7 +#define B2_TCOH 0x0 +#define B2_TAH 0x0 +#define B2_TACP 0x0 +#define B2_PMC 0x0 +#define BANKCON2_VAL ((B2_TACS << 13) + (B2_TCOS << 11) + (B2_TACC << 8) + \ + (B2_TCOH << 6) + (B2_TAH << 4) + (B2_TACP << 2) + \ + B2_PMC) + +#define B3_TACS 0x0 /* 0clk */ +#define B3_TCOS 0x3 /* 4clk */ +#define B3_TACC 0x7 /* 14clk */ +#define B3_TCOH 0x1 /* 1clk */ +#define B3_TAH 0x3 /* 4clk */ +#define B3_TACP 0x3 /* 6clk */ +#define B3_PMC 0x0 /* 16data */ +#define BANKCON3_VAL ((B3_TACS << 13) + (B3_TCOS << 11) + (B3_TACC << 8) + \ + (B3_TCOH << 6) + (B3_TAH << 4) + (B3_TACP << 2) + \ + B3_PMC) + +#define B4_TACS 0x0 +#define B4_TCOS 0x0 +#define B4_TACC 0x7 +#define B4_TCOH 0x0 +#define B4_TAH 0x0 +#define B4_TACP 0x0 +#define B4_PMC 0x0 +#define BANKCON4_VAL ((B4_TACS << 13) + (B4_TCOS << 11) + (B4_TACC << 8) + \ + (B4_TCOH << 6) + (B4_TAH << 4) + (B4_TACP << 2) + \ + B4_PMC) + +#define B5_TACS 0x0 +#define B5_TCOS 0x0 +#define B5_TACC 0x7 +#define B5_TCOH 0x0 +#define B5_TAH 0x0 +#define B5_TACP 0x0 +#define B5_PMC 0x0 +#define BANKCON5_VAL ((B5_TACS << 13) + (B5_TCOS << 11) + (B5_TACC << 8) + \ + (B5_TCOH << 6) + (B5_TAH << 4) + (B5_TACP << 2) + \ + B5_PMC) + +#define B6_MT 0x3 /* SDRAM */ +#define B6_TRCD 0x2 +#define B6_SCAN 0x1 /* 9bit */ +#define BANKCON6_VAL ((B6_MT << 15) + (B6_TRCD << 2) + B6_SCAN) + +#define B7_MT 0x3 /* SDRAM */ +#define B7_TRCD 0x2 /* 4clk */ +#define B7_SCAN 0x1 /* 9bit */ +#define BANKCON7_VAL ((B7_MT << 15) + (B7_TRCD << 2) + B7_SCAN) + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define TRP 0x0 /* 2clk */ +#define TRC 0x3 /* 7clk */ +#define TCHR 0x2 /* 3clk */ +#define REFCNT 1259 +#define REFRESH_VAL ((REFEN << 23) + (TREFMD << 22) + (TRP << 20) + \ + (TRC << 18) + (TCHR << 16) + REFCNT) + +/* BANKSIZE parameter */ +#define BURST_EN 1 /* Enable burst mode */ +#define SCKE_EN 1 /* Enable SDRAM power-down mode */ +#define SCLK_EN 1 /* SCLK is active only during the access */ +#define BK67MAP 2 /* 128M/128M */ +#define BANKSIZE_VAL ((BURST_EN << 7) + (SCKE_EN << 5) + \ + (SCLK_EN << 4) + BK67MAP) + +/* MRSRB6 parameter */ +#define WBL6 0 /* Burst */ +#define TM6 0 /* Modem register set */ +#define CL6 3 /* Latency is 3 clocks */ +#define BT6 0 /* Sequential */ +#define BL6 0 +#define MRSRB6_VAL ((WBL6 << 9) + (TM6 << 7) + (CL6 << 4) + \ + (BT6 << 3) + BL6) + +/* MRSRB7 parameter */ +#define WBL7 0 /* Burst */ +#define TM7 0 /* Modem register set */ +#define CL7 3 /* Latency is 3 clocks */ +#define BT7 0 /* Sequential */ +#define BL7 0 +#define MRSRB7_VAL ((WBL7 << 9) + (TM7 << 7) + (CL7 << 4) + \ + (BT7 << 3) + BL7) + +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word BWSCON_VAL + .word BANKCON0_VAL + .word BANKCON1_VAL + .word BANKCON2_VAL + .word BANKCON3_VAL + .word BANKCON4_VAL + .word BANKCON5_VAL + .word BANKCON6_VAL + .word BANKCON7_VAL + .word REFRESH_VAL + .word BANKSIZE_VAL + .word MRSRB6_VAL + .word MRSRB7_VAL diff --git a/board/embest/sbc2440ii/sbc2440ii.c b/board/embest/sbc2440ii/sbc2440ii.c new file mode 100644 index 0000000..7c793e9 --- /dev/null +++ b/board/embest/sbc2440ii/sbc2440ii.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <s3c2440.h> +#include <asm/io.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +static inline void pll_settle_delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" "bne 1b" : + "=r" (loops) : "0"(loops)); +} + +int board_init(void) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + writel(0xFFFFFFFF, &clk_power->LOCKTIME); + + /* configure UPLL */ + writel((CONFIG_SYS_U_MDIV << 12) + (CONFIG_SYS_U_PDIV << 4) + + CONFIG_SYS_U_SDIV, &clk_power->UPLLCON); + + /* some delay between UPLL and MPLL */ + pll_settle_delay(8000); + + /* configure MPLL */ + writel((CONFIG_SYS_M_MDIV << 12) + (CONFIG_SYS_M_PDIV << 4) + + CONFIG_SYS_M_SDIV, &clk_power->MPLLCON); + + /* configure the GPIO */ + writel(CONFIG_SYS_GPACON, &gpio->GPACON); + writel(CONFIG_SYS_GPBCON, &gpio->GPBCON); + writel(CONFIG_SYS_GPBUP, &gpio->GPBUP); + writel(CONFIG_SYS_GPBDAT, &gpio->GPBDAT); + writel(CONFIG_SYS_GPCCON, &gpio->GPCCON); + writel(CONFIG_SYS_GPCUP, &gpio->GPCUP); + writel(CONFIG_SYS_GPDCON, &gpio->GPDCON); + writel(CONFIG_SYS_GPDUP, &gpio->GPDUP); + writel(CONFIG_SYS_GPECON, &gpio->GPECON); + writel(CONFIG_SYS_GPEUP, &gpio->GPEUP); + writel(CONFIG_SYS_GPFCON, &gpio->GPFCON); + writel(CONFIG_SYS_GPFUP, &gpio->GPFUP); + writel(CONFIG_SYS_GPGCON, &gpio->GPGCON); + writel(CONFIG_SYS_GPGUP, &gpio->GPGUP); + writel(CONFIG_SYS_GPHCON, &gpio->GPHCON); + writel(CONFIG_SYS_GPHUP, &gpio->GPHUP); + writel(CONFIG_SYS_GPJCON, &gpio->GPJCON); + writel(CONFIG_SYS_GPJUP, &gpio->GPJUP); + writel(CONFIG_SYS_EXTINT0, &gpio->EXTINT0); + writel(CONFIG_SYS_EXTINT1, &gpio->EXTINT1); + writel(CONFIG_SYS_EXTINT2, &gpio->EXTINT2); + writel(CONFIG_SYS_EINTMASK, &gpio->EINTMASK); + + /* arch number of SBC2440-II Board */ + gd->bd->bi_arch_number = MACH_TYPE_SBC2440II; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_CS8900 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); +#endif + return rc; +} +#endif diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 2ee1518..bbe4c07 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -180,6 +180,7 @@ ulong get_tbclk(void) #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ + defined(CONFIG_SBC2440II) || \ defined(CONFIG_SMDK2410) || \ defined(CONFIG_VCMA9) tbclk = CONFIG_SYS_HZ; diff --git a/include/configs/sbc2440ii.h b/include/configs/sbc2440ii.h new file mode 100644 index 0000000..7ac36cf --- /dev/null +++ b/include/configs/sbc2440ii.h @@ -0,0 +1,254 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * Gary Jennejohn <gj(a)denx.de> + * David Mueller <d.mueller(a)elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * Configuation settings for the friendly-arm SBC-2410X board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_IDENT_STRING " for Embest SBC2440-II" + +/* If we are developing, we might want to start armboot from ram + so we MUST NOT initialize critical regs like mem-timing ... */ +#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */ + +/* High Level Configuration Options (easy to change) */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24X0 type of SoC */ +#define CONFIG_S3C2440 1 /* specifically, a SAMSUNG S3C2440 SoC*/ +#define CONFIG_SBC2440II 1 /* on an Embest SBC-2440-II Board */ +#define CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT + +/* input clock of PLL - the SBC2440-II has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +/* The PLL values for MPLL = 400MHz, UPLL = 48MHz + The clock frequency ratios are set to 1:4:8 ie: + PCLK = 50MHz + HCLK = 100MHz + FCLK = 400MHz + */ +/* The MPLL values. */ +#define CONFIG_SYS_M_MDIV 0x5C +#define CONFIG_SYS_M_PDIV 1 +#define CONFIG_SYS_M_SDIV 1 + +/* The UPLL values. */ +#define CONFIG_SYS_U_MDIV 0x38 +#define CONFIG_SYS_U_PDIV 2 +#define CONFIG_SYS_U_SDIV 2 + +/* We don't need the MMU or interrupts. */ +#undef USE_920T_MMU +#undef CONFIG_USE_IRQ + +/* The GPIO configuration */ +#define CONFIG_SYS_GPACON 0x007FFFFF +#define CONFIG_SYS_GPBCON 0x00055555 +#define CONFIG_SYS_GPBUP 0x000007FF +#define CONFIG_SYS_GPBDAT 0x000001C0 /* Switch on LED1. */ +#define CONFIG_SYS_GPCCON 0xAAAAAAAA +#define CONFIG_SYS_GPCUP 0x0000FFFF +#define CONFIG_SYS_GPDCON 0xAAAAAAAA +#define CONFIG_SYS_GPDUP 0x0000FFFF +#define CONFIG_SYS_GPECON 0xAAAAA800 +#define CONFIG_SYS_GPEUP 0x00001FFF +#define CONFIG_SYS_GPFCON 0x000055AA +#define CONFIG_SYS_GPFUP 0x000000FF +#define CONFIG_SYS_GPGCON 0xFD95FFBA +#define CONFIG_SYS_GPGUP 0x0000FFFF +#define CONFIG_SYS_GPHCON 0x0002FAAA +#define CONFIG_SYS_GPHUP 0x000007FF +#define CONFIG_SYS_GPJCON 0x02FAAAAA +#define CONFIG_SYS_GPJUP 0x00001FFF +#define CONFIG_SYS_EXTINT0 0x22222222 +#define CONFIG_SYS_EXTINT1 0x22222222 +#define CONFIG_SYS_EXTINT2 0x22222222 +#define CONFIG_SYS_EINTMASK 0x00FFFFF0 + +/* + * Hardware drivers + */ +#define CONFIG_CS8900 1 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x19000300 +#define CONFIG_CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* Serial console configuration */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2440-II */ +#define CONFIG_BAUDRATE 115200 +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* RTC */ +#define CONFIG_RTC_S3C24X0 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration. */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_JFFS2_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=sbc2440-II-nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=sbc2440-II-nand:2m(kernel),62m(rootfs)" +#define CONFIG_EXTRA_ENV_SETTINGS "autostart=yes" +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS \ +"noinitrd root=/dev/mtdblock1 rootfstype=jffs2 init=/linuxrc console=ttySAC0" +#define CONFIG_LOADADDR 30008000 +#define CONFIG_BOOTCOMMAND "nboot 30008000 0 0" + +/* kgdb settings */ +#if defined(CONFIG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 115200 + #define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "[ SBC2440-II ]# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MEMTEST_START 0x30000000 +#define CONFIG_SYS_MEMTEST_END 0x33F00000 +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_HZ 1000 + +/* Stack sizes */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ + #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ + #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* FLASH and environment and organization */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x00200000 /* 2MB */ +#define CONFIG_SYS_MAX_FLASH_SECT (35) +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +/* FLASH driver setup */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) + +/* NAND flash settings */ +#if defined(CONFIG_CMD_NAND) + #define CONFIG_NAND_S3C2410 + #define CONFIG_SYS_NAND_BASE 0x4e00000c + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define SECTORSIZE 512 + #define CONFIG_S3C2410_NAND_HWECC + #define CONFIG_SYS_NAND_LARGEPAGE + #define CONFIG_SYS_NAND_TACLS 0 + #define CONFIG_SYS_NAND_TWRPH0 3 + #define CONFIG_SYS_NAND_TWRPH1 1 +#endif + +/* Kernel boot argument config. */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +/* USB settings */ +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x49000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sbc2440-II" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +/*----------------------------------------------------------------------- + * Enable network + */ +#define CONFIG_NET_MULTI + +/* Other settings. */ +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_CMDLINE_EDITING + #undef CONFIG_AUTO_COMPLETE +#else + #define CONFIG_AUTO_COMPLETE +#endif + +#endif /* __CONFIG_H */ -- 1.6.0.6

2 1

[U-Boot] [PATCH] ARM: fix build error with gcc-4.4.2 about inline function declared weak
by walsimou＠walsimou.com 01 Nov '09

01 Nov '09

From: Abdoulaye Walsimou Gaye <walsimou(a)walsimou.com> This patch fix build error with gcc-4.4.2 about inline function declared weak, see below: board.c:96: error: inline function 'coloured_LED_init' cannot be declared weak board.c:98: error: inline function 'red_LED_on' cannot be declared weak board.c:100: error: inline function 'red_LED_off' cannot be declared weak board.c:102: error: inline function 'green_LED_on' cannot be declared weak board.c:104: error: inline function 'green_LED_off' cannot be declared weak board.c:106: error: inline function 'yellow_LED_on' cannot be declared weak board.c:108: error: inline function 'yellow_LED_off' cannot be declared weak board.c:110: error: inline function 'blue_LED_on' cannot be declared weak board.c:112: error: inline function 'blue_LED_off' cannot be declared weak make[1]: *** [board.o] Error 1 Signed-off-by: Abdoulaye Walsimou Gaye <walsimou(a)walsimou.com> --- lib_arm/board.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/lib_arm/board.c b/lib_arm/board.c index 5e3d7f6..886c74c 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -93,23 +93,23 @@ extern void rtl8019_get_enetaddr (uchar * addr); * May be supplied by boards if desired */ void inline __coloured_LED_init (void) {} -void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init"))); +void coloured_LED_init(void)__attribute__((weak, alias("__coloured_LED_init"))); void inline __red_LED_on (void) {} -void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on"))); +void red_LED_on(void) __attribute__((weak, alias("__red_LED_on"))); void inline __red_LED_off(void) {} -void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); +void red_LED_off(void)__attribute__((weak, alias("__red_LED_off"))); void inline __green_LED_on(void) {} -void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); +void green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); void inline __green_LED_off(void) {} -void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off"))); +void green_LED_off(void)__attribute__((weak, alias("__green_LED_off"))); void inline __yellow_LED_on(void) {} -void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on"))); +void yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on"))); void inline __yellow_LED_off(void) {} -void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))); +void yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))); void inline __blue_LED_on(void) {} -void inline blue_LED_on(void)__attribute__((weak, alias("__blue_LED_on"))); +void blue_LED_on(void)__attribute__((weak, alias("__blue_LED_on"))); void inline __blue_LED_off(void) {} -void inline blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off"))); +void blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off"))); /************************************************************************ * Init Utilities * -- 1.6.0.4

4 4

[U-Boot] [PATCH-ARM 2/3] Add sc32440 support to the s3c2410 nand driver
by kevin.morfitt＠fearnside-systems.co.uk 01 Nov '09

01 Nov '09

This patch adds support for the s3c2440 cpu to the nand driver. It does this by replacing the existing driver with that from linux 2.6.31.5, modified to make it work in the u-boot mtd nand architecture. Note that the linux s3c2410 nand driver supports s3c2410 and s3c2440, though I haven't been able to test this on an s3c2410 board, only an s3c2440 board. Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> drivers/mtd/nand/s3c2410_nand.c | 134 +++++++++++++++++++++------------------ 1 files changed, 73 insertions(+), 61 deletions(-) diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index 87d0bf6..b8ea581 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -2,6 +2,10 @@ * (C) Copyright 2006 OpenMoko, Inc. * Author: Harald Welte <laforge(a)openmoko.org> * + * Modified to add S3C2440 support by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -21,48 +25,53 @@ #include <common.h> #include <nand.h> +#include <linux/mtd/nand_ecc.h> #include <s3c24x0_cpu.h> #include <asm/io.h> -#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) +#if defined(CONFIG_S3C2410_NAND_HWECC) && defined(CONFIG_SYS_NAND_LARGEPAGE) +/* new oob placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob = { + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {8, 8} } +}; +#endif -#define S3C2410_ADDR_NALE 4 -#define S3C2410_ADDR_NCLE 8 +static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + unsigned long reg = readl(&nand->S3C24X0_NAND_CTRL_REG); + + if (chip == -1) { + debugX(1, "Negating nFCE\n"); + reg |= S3C24X0_NAND_nFCE_BIT; + } else { + debugX(1, "Asserting nFCE\n"); + reg &= ~S3C24X0_NAND_nFCE_BIT; + } + writel(reg, &nand->S3C24X0_NAND_CTRL_REG); +} static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *chip = mtd->priv; struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong)nand; - - if (!(ctrl & NAND_CLE)) - IO_ADDR_W |= S3C2410_ADDR_NCLE; - if (!(ctrl & NAND_ALE)) - IO_ADDR_W |= S3C2410_ADDR_NALE; - - chip->IO_ADDR_W = (void *)IO_ADDR_W; + if (cmd == NAND_CMD_NONE) + return; - if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); - else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); + if (ctrl & NAND_CLE) { + debugX(1, "NFCMD = 0x%08X\n", cmd); + writel(cmd, &nand->NFCMD); } - if (cmd != NAND_CMD_NONE) - writeb(cmd, chip->IO_ADDR_W); + if (ctrl & NAND_ALE) { + debugX(1, "NFADDR = 0x%08X\n", cmd); + writel(cmd, &nand->NFADDR); + } } static int s3c2410_dev_ready(struct mtd_info *mtd) @@ -76,39 +85,32 @@ static int s3c2410_dev_ready(struct mtd_info *mtd) void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); + unsigned long reg = readl(&nand->S3C24X0_NAND_CTRL_REG); + debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); + reg |= S3C24X0_NAND_INITECC_BIT; + writel(reg, &nand->S3C24X0_NAND_CTRL_REG); } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - ecc_code[0] = NFECC0; - ecc_code[1] = NFECC1; - ecc_code[2] = NFECC2; + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + unsigned long ecc = readl(&nand->S3C24X0_NAND_ECC_REG); + + ecc_code[0] = ecc; + ecc_code[1] = ecc >> 8; + ecc_code[2] = ecc >> 16; debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", - mtd , ecc_code[0], ecc_code[1], ecc_code[2]); + mtd, ecc_code[0], ecc_code[1], ecc_code[2]); return 0; } - -static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - if (read_ecc[0] == calc_ecc[0] && - read_ecc[1] == calc_ecc[1] && - read_ecc[2] == calc_ecc[2]) - return 0; - - printf("s3c2410_nand_correct_data: not implemented\n"); - return -1; -} #endif int board_nand_init(struct nand_chip *nand) { - u_int32_t cfg; - u_int8_t tacls, twrph0, twrph1; + unsigned long reg; struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); struct s3c2410_nand *nand_reg = s3c2410_get_base_nand(); @@ -117,15 +119,12 @@ int board_nand_init(struct nand_chip *nand) writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); /* initialize hardware */ - twrph0 = 3; - twrph1 = 0; - tacls = 0; - - cfg = S3C2410_NFCONF_EN; - cfg |= S3C2410_NFCONF_TACLS(tacls - 1); - cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); - cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->NFCONF); + reg = S3C24X0_NAND_TACLS_BITS(CONFIG_SYS_NAND_TACLS); + reg |= S3C24X0_NAND_TWRPH0_BITS(CONFIG_SYS_NAND_TWRPH0); + reg |= S3C24X0_NAND_TWRPH1_BITS(CONFIG_SYS_NAND_TWRPH1); + writel(reg, &nand_reg->S3C24X0_NAND_TIMING_REG); + reg = S3C24X0_NAND_EN_BIT | S3C24X0_NAND_nFCE_BIT; + writel(reg, &nand_reg->S3C24X0_NAND_CTRL_REG); /* initialize nand_chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; @@ -133,16 +132,29 @@ int board_nand_init(struct nand_chip *nand) /* read_buf and write_buf are default */ /* read_byte and write_byte are default */ + nand->select_chip = s3c2410_nand_select_chip; + nand->chip_delay = 50; + /* hwcontrol always must be implemented */ nand->cmd_ctrl = s3c2410_hwcontrol; - nand->dev_ready = s3c2410_dev_ready; #ifdef CONFIG_S3C2410_NAND_HWECC - nand->ecc.hwctl = s3c2410_nand_enable_hwecc; - nand->ecc.calculate = s3c2410_nand_calculate_ecc; - nand->ecc.correct = s3c2410_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW3_512; + nand->ecc.correct = nand_correct_data; + nand->ecc.hwctl = s3c2410_nand_enable_hwecc; + nand->ecc.calculate = s3c2410_nand_calculate_ecc; + nand->ecc.mode = NAND_ECC_HW; + /* change the behaviour depending on whether we are using + * the large or small page nand device */ +#ifdef CONFIG_SYS_NAND_LARGEPAGE + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.layout = &nand_hw_eccoob; +#else + nand->ecc.size = 256; + nand->ecc.bytes = 3; +#endif + debugX(2, "ecc: size: %d bytes: %d\n", nand->ecc.size, nand->ecc.bytes); #else nand->ecc.mode = NAND_ECC_SOFT; #endif -- 1.6.0.6

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[U-Boot] Can't see NFS packages with wireshark
by Michael Schmid 01 Nov '09

01 Nov '09

Hi! I have: Board: Artila M501 board with AT91RM9200 U-Boot: 1.1.2 Kernel: 2.6.14-M5 (I know that U-Boot and Kernel are quite old, but I think for my learning purposes it is OK... Will try to update later.) My problem: I'm trying to run root-fs over nfs... I know that my nfs-server is OK, because I can mount from another linux-pc. But I'm not able to mount nfs from my target-system. And I can't see any package from my target on wireshark which is running on the nfs-server -> So it seems that my target doesn't send any packet to the server or it get lost on my net.... Can you see any problem with my configuration? See configuration and bootlog below: Configuration: *************************** baudrate=115200 ethaddr=00:13:48:00:77:b5 rootpath=/opt/arm lel=1 initrd=0x20800000,8192000 ramdisk_size=15360 root=/dev/ram0 rw loader=tftp 21000000 m501_64M.alf mtdparts=phys_mapped_flash:128k(loader)ro,128k(reserved)ro,1408k(linux)ro,2560(ramdisk)ro,-(userdisk) filesize=3A3 netmask=255.255.255.0 kernel=tftp 21000000 M501K;erase 10040000 1019ffff;cp.b 21000000 10040000 $(filesize) skernel=loadb 21000000;erase 10040000 1019ffff;cp.b 21000000 10040000 $(filesize) ramdisk=tftp 21000000 M501R;erase 101a0000 1041ffff;cp.b 21000000 101a0000 $(filesize) sramdisk=loadb 21000000;erase 101a0000 1041ffff;cp.b 21000000 101a0000 $(filesize) ipaddr=192.168.2.196 bootdelay=1 bargs=setenv bootargs mem=64M console=$(console),115200 initrd=0x20800000,8192000 ramdisk_size=15360 root=/dev/ram0 rw mtdparts=phys_mapped_flash:128k(loader)ro,128k(env)ro,1408k(linux)ro,2560k(ramdisk)ro,-(userdisk) serverip=192.168.2.40 gateway=192.168.2.1 console=ttyS0 bootargs=mem=64M root=/dev/nfs rw nfsroot=192.168.2.40:/opt/arm ip=192.168.2.196:192.168.2.40:192.168.2.1:255.255.255.0:kleiner_michi::off console=ttyS0,115200 bootcmd=bootm 10040000 stdin=serial stdout=serial stderr=serial *************************** log: *************************** Starting M501............. Starting kernel ... Uncompressing Linux............................................................................................... done, booting the kernel. Linux version 2.6.14-M5 (Alan@ace-yang) (gcc version 3.3.2) #837 Tue Aug 14 14:14:03 CST 2007 CPU: ARM920Tid(wb) [41129200] revision 0 (ARMv4T) Machine: Artila M501 SOM Memory policy: ECC disabled, Data cache writeback Clocks: CPU 179 MHz, master 59 MHz, main 18.432 MHz CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets CPU0: D cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets Built 1 zonelists Kernel command line: mem=64M root=/dev/nfs rw nfsroot=192.168.2.40:/opt/arm ip=192.168.2.196:192.168.2.40:192.168.2.1:255.255.255.0:kleiner_michi::off console=ttyS0,115200 AT91: 128 gpio irqs in 4 banks PID hash table entries: 512 (order: 9, 8192 bytes) Console: colour dummy device 80x30 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 64MB = 64MB total Memory: 61824KB available (2389K code, 523K data, 104K init) Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok NET: Registered protocol family 16 SCSI subsystem initialized usbcore: registered new driver usbfs usbcore: registered new driver hub NetWinder Floating Point Emulator V0.97 (extended precision) JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc. Initializing Cryptographic API Matrix500 RTC driver. Matrix500 GPIO Driver Loaded. AT91 SPI driver loaded AT91 Watchdog Timer enabled (5 seconds) ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL ttyS1 at MMIO 0xfefc0000 (irq = 6) is a AT91_SERIAL ttyS2 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL ttyS3 at MMIO 0xfefc8000 (irq = 8) is a AT91_SERIAL ttyS4 at MMIO 0xfefcc000 (irq = 9) is a AT91_SERIAL io scheduler noop registered io scheduler anticipatory registered RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize PPP generic driver version 2.4.2 PPP BSD Compression module registered NET: Registered protocol family 24 eth0: Link now 100-FullDuplex eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:13:48:00:77:b5) eth0: Davicom 9161AE PHY (Copper) physmap flash device: 1000000 at 10000000 phys_mapped_flash: Found 1 x16 devices at 0x0 in 16-bit bank Intel/Sharp Extended Query Table at 0x010A Using buffer write method cfi_cmdset_0001: Erase suspend on write enabled RedBoot partition parsing not available block2mtd: version $Revision: 1.28 $ at91rm9200-ohci at91rm9200-ohci: AT91RM9200 OHCI at91rm9200-ohci at91rm9200-ohci: new USB bus registered, assigned bus number 1 at91rm9200-ohci at91rm9200-ohci: irq 23, io mem 0x00300000 usb usb1: Product: AT91RM9200 OHCI usb usb1: Manufacturer: Linux 2.6.14-M5 ohci_hcd usb usb1: SerialNumber: at91rm9200 hub 1-0:1.0: USB hub found hub 1-0:1.0: 2 ports detected usbcore: registered new driver cdc_acm drivers/usb/class/cdc-acm.c: v0.23:USB Abstract Control Model driver for USB modems and ISDN adapters usbcore: registered new driver usblp drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver Initializing USB Mass Storage driver... usbcore: registered new driver usb-storage USB Mass Storage support registered. rtusb init ====> usbcore: registered new driver rt73 usbcore: registered new driver usbserial drivers/usb/serial/usb-serial.c: USB Serial support registered for Generic usbcore: registered new driver usbserial_generic drivers/usb/serial/usb-serial.c: USB Serial Driver core v2.0 drivers/usb/serial/usb-serial.c: USB Serial support registered for FTDI USB Serial Device usbcore: registered new driver ftdi_sio drivers/usb/serial/ftdi_sio.c: v1.4.3:USB FTDI Serial Converters Driver drivers/usb/serial/usb-serial.c: USB Serial support registered for PL-2303 usbcore: registered new driver pl2303 drivers/usb/serial/pl2303.c: Prolific PL2303 USB to serial adaptor driver v0.12 mice: PS/2 mouse device common for all mice i2c /dev entries driver Found AT91 i2c RTC found. AT91RM9200 MCI initialized NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 2, 16384 bytes) TCP bind hash table entries: 4096 (order: 2, 16384 bytes) TCP: Hash tables configured (established 4096 bind 4096) TCP reno registered ip_conntrack version 2.3 (512 buckets, 4096 max) - 240 bytes per conntrack ctnetlink v0.90: registering with nfnetlink. ip_tables: (C) 2000-2002 Netfilter core team ipt_recent v0.3.1: Stephen Frost <sfrost(a)snowman.net>. http://snowman.net/projects/ipt_recent/ arp_tables: (C) 2002 David S. Miller TCP bic registered Netfilter messages via NETLINK v0.30. NET: Registered protocol family 1 NET: Registered protocol family 17 eth0: Link now 100-FullDuplex IP-Config: Complete: device=eth0, addr=192.168.2.196, mask=255.255.255.0, gw=192.168.2.1, host=kleiner_michi, domain=, nis-domain=(none), bootserver=192.168.2.40, rootserver=192.168.2.40, rootpath= VFS: Cannot open root device "nfs" or unknown-block(0,255) Please append a correct "root=" boot option Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,255) *************************** Regards! Michael

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[U-Boot] Enabling 2 FCC ports using CONFIG_NET_MULTI
by Gurumurthy Gowdar 01 Nov '09

01 Nov '09

hi , Manually i am setting the MAC address using setenv ethaddr MAC Address for each FCC. i am using FCC1 & FCC2. i want one FCC port to be active at a time. PowerPC is MPC8280 Regards, Gurumurthy

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[U-Boot] Pull request: u-boot-sh
by Nobuhiro Iwamatsu 01 Nov '09

01 Nov '09

Dear Wolfgang, Could you pull from the master branch at git://git.denx.de/u-boot-sh.git ? Best regards, Nobuhiro The following changes since commit f2b4bc04d6aed6be712d236dab48ac4c4da22cbf: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash are available in the git repository at: git://git.denx.de/u-boot-sh.git master Nobuhiro Iwamatsu (3): sh: Remove malloc_bin_reloc from lib_sh, lib_nios2 and lib_nios. sh: Move some defs to convince 'pcrel too far' sh: Update lowlevel_init.S of espt-giga board/espt/lowlevel_init.S | 10 +--- board/renesas/sh7785lcr/lowlevel_init.S | 107 +++++++++++++++---------------- lib_nios/board.c | 2 - lib_nios2/board.c | 2 - lib_sh/board.c | 2 - 5 files changed, 54 insertions(+), 69 deletions(-)

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[U-Boot] SMDK2410 board
by David Kaplan 01 Nov '09

01 Nov '09

I'm trying to get u-boot running on a smdk2410-based board. I'm using openocd and jtag and am trying to load u-boot into ram as follows: load_image u-boot.bin 0x33f80000 Which *seems* to work: 103668 bytes written at address 0x33f80000 downloaded 103668 byte in 0.500045s I then try to run it by using resume 0x33f80000 but it doesn't seem that u-boot is executing. What am I doing wrong?

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