October 2009 - U-Boot

[U-Boot] [PATCH 5/6] ppc4xx: Add common ppc4xx linker script
by Stefan Roese 27 Oct '09

27 Oct '09

This linker script can be used by all PPC4xx platforms. It works for PPC405 and PPC440 platforms. Boards which need a board specific linker script can override this default linker script in board/*/config.mk. Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/config.mk | 3 + cpu/ppc4xx/u-boot.lds | 169 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 172 insertions(+), 0 deletions(-) create mode 100644 cpu/ppc4xx/u-boot.lds diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index 00ad39b..979004b 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -32,3 +32,6 @@ PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 else PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 endif + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/cpu/ppc4xx/u-boot.lds diff --git a/cpu/ppc4xx/u-boot.lds b/cpu/ppc4xx/u-boot.lds new file mode 100644 index 0000000..2b47934 --- /dev/null +++ b/cpu/ppc4xx/u-boot.lds @@ -0,0 +1,169 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "config.h" /* CONFIG_BOARDDIR */ + +#ifndef RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + +#ifdef CONFIG_440 + .bootpg RESET_VECTOR_ADDRESS - 0xffc : + { + cpu/ppc4xx/start.o (.bootpg) + + /* + * PPC440 board need a board specific object with the + * TLB definitions. This needs to get included right after + * start.o, since the first shadow TLB only covers 4k + * of address space. + */ + CONFIG_BOARDDIR/init.o (.bootpg) + } :text = 0xffff +#endif + + .resetvec RESET_VECTOR_ADDRESS : + { + *(.resetvec) + } :text = 0xffff + + . = RESET_VECTOR_ADDRESS + 0x4; + + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. Note that + * this is a temporary fix. Code to dynamically the fixup the bss + * location will be added in the future. When the bss relocation + * fixup code is present this workaround should be removed. + */ +#if (RESET_VECTOR_ADDRESS == 0xfffffffc) + . |= 0x10; +#endif + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} -- 1.6.5.1

1 0

[U-Boot] [PATCH 4/6] ppc4xx: Add custom linker script to board/*/config.mk
by Stefan Roese 27 Oct '09

27 Oct '09

These boards have special linker scripts right now. We can't use the common 4xx linker script here. So overrride the linker script (LDSCRIPT) in board/*/config.mk and choose the board specific version. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amirix/ap1000/config.mk | 3 +++ board/esd/dasa_sim/config.mk | 3 +++ board/ml2/config.mk | 3 +++ board/xilinx/ml300/config.mk | 3 +++ 4 files changed, 12 insertions(+), 0 deletions(-) diff --git a/board/amirix/ap1000/config.mk b/board/amirix/ap1000/config.mk index c09783a..09c6efa 100644 --- a/board/amirix/ap1000/config.mk +++ b/board/amirix/ap1000/config.mk @@ -25,3 +25,6 @@ # like it's not in RAM. This is a bit of voodoo to allow it to be # run from RAM instead of Flash. TEXT_BASE = 0x08000000 + +# Use board specific linker script +LDSCRIPT := $(SRCTREE)/board/amirix/ap1000/u-boot.lds diff --git a/board/esd/dasa_sim/config.mk b/board/esd/dasa_sim/config.mk index ae855dc..4fe3774 100644 --- a/board/esd/dasa_sim/config.mk +++ b/board/esd/dasa_sim/config.mk @@ -21,3 +21,6 @@ # MA 02111-1307 USA # TEXT_BASE = 0xFFFC0000 + +# Use board specific linker script +LDSCRIPT := $(SRCTREE)/board/esd/dasa_sim/u-boot.lds diff --git a/board/ml2/config.mk b/board/ml2/config.mk index 41118d5..5e0bdae 100644 --- a/board/ml2/config.mk +++ b/board/ml2/config.mk @@ -27,3 +27,6 @@ #TEXT_BASE = 0xFFFE0000 TEXT_BASE = 0x18000000 + +# Use board specific linker script +LDSCRIPT := $(SRCTREE)/board/ml2/u-boot.lds diff --git a/board/xilinx/ml300/config.mk b/board/xilinx/ml300/config.mk index 57ddb2f..208a25b 100644 --- a/board/xilinx/ml300/config.mk +++ b/board/xilinx/ml300/config.mk @@ -27,3 +27,6 @@ #TEXT_BASE = 0xFFFE0000 TEXT_BASE = 0x04000000 + +# Use board specific linker script +LDSCRIPT := $(SRCTREE)/board/xilinx/ml300/u-boot.lds -- 1.6.5.1

1 0

[U-Boot] [PATCH 3/6] ppc4xx: Fix problems in some ppc4xx board Makefiles
by Stefan Roese 27 Oct '09

27 Oct '09

Some 4xx Makefiles didn't add $(SOBJ) to their board library. This was no till now problem, since those boards included this object (init.o most of the time) directly from their linker scripts. This patch clean this up, so that all objects are now collected in the board library. This is in preparation for the upcoming PPC4xx linker script consolidation. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/eric/Makefile | 2 +- board/jse/Makefile | 2 +- board/ml2/Makefile | 2 +- board/mpl/mip405/Makefile | 2 +- board/mpl/pip405/Makefile | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/eric/Makefile b/board/eric/Makefile index 81a4552..c2a6872 100644 --- a/board/eric/Makefile +++ b/board/eric/Makefile @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/jse/Makefile b/board/jse/Makefile index 6be03ac..fc71601 100644 --- a/board/jse/Makefile +++ b/board/jse/Makefile @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/ml2/Makefile b/board/ml2/Makefile index 2a93666..59644db 100644 --- a/board/ml2/Makefile +++ b/board/ml2/Makefile @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 53bf846..18a8d86 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -38,7 +38,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 590c7da..774b59f 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -41,7 +41,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) -- 1.6.5.1

1 0

[U-Boot] esdmode for DDR2
by Werner Nedel 27 Oct '09

27 Oct '09

Hi, I was looking the ctrl_regs.c file at the last release of u-boot, specifically at sdram_mode register, and checking at AN3369.pdf I think that Rtt bit position might be wrong. At the code, the bit shifting is 5, but shouldn't be 6? I think that it overwrites AL register. Thanks in advance, Werner Nedel.

2 6

[U-Boot] [PATCH 0/7] Some patches for MPC8569E-MDS
by Anton Vorontsov 27 Oct '09

27 Oct '09

Hello Kumar, Just resending rebased MPC8569E-MDS patches with your comments addressed, plus there some fixes in eSDHC patch for pilot boards (BCSR registers changed). Thanks, -- Anton Vorontsov email: cbouatmailru(a)gmail.com irc://irc.freenode.net/bd2

3 16

[U-Boot] [PATCH] fsl_pci: Fix compiler warning
by Peter Tyser 27 Oct '09

27 Oct '09

Get rid of: fsl_pci_init.c: In function 'fsl_pci_init_port': fsl_pci_init.c:424: warning: initialization discards qualifiers from pointer target type Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- This fixes the compiler warning in the just-applied "ppc/85xx/pci: fsl_pci_init: pcie agent mode support" drivers/pci/fsl_pci_init.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 289878a..259f879 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -421,7 +421,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, pci = (ccsr_fsl_pci_t *) pci_info->regs; if (pcie_ep) { - pit_t *pi = &pci->pit[2]; + volatile pit_t *pi = &pci->pit[2]; pci_setup_indirect(hose, (u32) &pci->cfg_addr, (u32) &pci->cfg_data); -- 1.6.2.1

2 1

[U-Boot] [PATCH 1/2 v3] 85xx: MP Boot Page Translation update
by Peter Tyser 27 Oct '09

27 Oct '09

This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- Hi Kumar, Hopefully this isn't too invasive... I tried to address your previous v2 comments of: - Its possible that the location in memory is not mapped in the TLBs. We typically max out @ 2G of DDR mapped (via the TLBs). So what happens if we have 3G of DDR? - We expect the the address that the spin table is at to be marked cache-inhibited. Changes since v1: - Use clrbits_be32() instead of in/out_be32() - Boot page translation is only disabled when CONFIG_MPC8xxx_DISABLT_BPTR is defined. - Instead of zeroing out BPTR when disabling translation, this patch only disables translation, but maintins the translation address. This should make it easier to properly re-enable translation if need be. Changes since v2: - Use CONFIG_BPTR_VIRT_ADDR to determine virtual address of secondary cores' boot page - Split get_spin_addr() into get_[phys|virt]_addr() cpu/mpc85xx/fdt.c | 2 +- cpu/mpc85xx/mp.c | 70 ++++++++++++++++++++++++++++++---------------- cpu/mpc85xx/mp.h | 3 +- cpu/mpc85xx/release.S | 34 +++++++++++++++++++--- include/asm-ppc/config.h | 10 ++++++ 5 files changed, 88 insertions(+), 31 deletions(-) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index efb6518..de2dcac 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -43,7 +43,7 @@ extern void ft_fixup_num_cores(void *blob); void ft_fixup_cpu(void *blob, u64 memory_limit) { int off; - ulong spin_tbl_addr = get_spin_addr(); + ulong spin_tbl_addr = get_spin_phys_addr(); u32 bootpg = determine_mp_bootpg(); u32 id = get_my_id(); diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index b5c6020..00b6450 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -52,10 +52,10 @@ int cpu_status(int nr) u32 *table, id = get_my_id(); if (nr == id) { - table = (u32 *)get_spin_addr(); + table = (u32 *)get_spin_virt_addr(); printf("table base @ 0x%p\n", table); } else { - table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; printf("Running on cpu %d\n", id); printf("\n"); printf("table @ 0x%p\n", table); @@ -77,7 +77,7 @@ static u8 boot_entry_map[4] = { int cpu_release(int nr, int argc, char *argv[]) { - u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; u64 boot_addr; if (nr == get_my_id()) { @@ -124,23 +124,29 @@ u32 determine_mp_bootpg(void) return (gd->ram_size - 4096); } -ulong get_spin_addr(void) +ulong get_spin_phys_addr(void) { extern ulong __secondary_start_page; extern ulong __spin_table; - ulong addr = - (ulong)&__spin_table - (ulong)&__secondary_start_page; - addr += 0xfffff000; + return (determine_mp_bootpg() + + (ulong)&__spin_table - (ulong)&__secondary_start_page); +} + +ulong get_spin_virt_addr(void) +{ + extern ulong __secondary_start_page; + extern ulong __spin_table; - return addr; + return (CONFIG_BPTR_VIRT_ADDR + + (ulong)&__spin_table - (ulong)&__secondary_start_page); } #ifdef CONFIG_FSL_CORENET static void plat_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; - u32 *table = (u32 *)get_spin_addr(); + u32 *table = (u32 *)get_spin_virt_addr(); volatile ccsr_gur_t *gur; volatile ccsr_local_t *ccm; volatile ccsr_rcpm_t *rcpm; @@ -194,12 +200,23 @@ static void plat_mp_up(unsigned long bootpg) mtspr(SPRN_TBWU, 0); mtspr(SPRN_TBWL, 0); out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); + +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR + /* + * Disabling Boot Page Translation allows the memory region 0xfffff000 + * to 0xffffffff to be used normally. Leaving Boot Page Translation + * enabled remaps 0xfffff000 to SDRAM which makes that memory region + * unusable for normal operation but it does allow OSes to easily + * reset a processor core to put it back into U-Boot's spinloop. + */ + clrbits_be32(&ecm->bptr, 0x80000000); +#endif } #else static void plat_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; - u32 *table = (u32 *)get_spin_addr(); + u32 *table = (u32 *)get_spin_virt_addr(); volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -256,6 +273,17 @@ static void plat_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); + +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR + /* + * Disabling Boot Page Translation allows the memory region 0xfffff000 + * to 0xffffffff to be used normally. Leaving Boot Page Translation + * enabled remaps 0xfffff000 to SDRAM which makes that memory region + * unusable for normal operation but it does allow OSes to easily + * reset a processor core to put it back into U-Boot's spinloop. + */ + clrbits_be32(&ecm->bptr, 0x80000000); +#endif } #endif @@ -269,33 +297,27 @@ void cpu_mp_lmb_reserve(struct lmb *lmb) void setup_mp(void) { extern ulong __secondary_start_page; + extern ulong __bootpg_addr; ulong fixup = (ulong)&__secondary_start_page; u32 bootpg = determine_mp_bootpg(); + /* Store the bootpg's SDRAM address for use by secondary CPU cores */ + __bootpg_addr = bootpg; + /* look for the tlb covering the reset page, there better be one */ - int i = find_tlb_idx((void *)0xfffff000, 1); + int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); /* we found a match */ if (i != -1) { /* map reset page to bootpg so we can copy code there */ disable_tlb(i); - set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ - 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ - - memcpy((void *)0xfffff000, (void *)fixup, 4096); - flush_cache(0xfffff000, 4096); - - disable_tlb(i); - - /* setup reset page back to 1:1, we'll use HW boot translation - * to map this where we want - */ - set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */ + set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ + memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); + plat_mp_up(bootpg); } else { puts("WARNING: No reset page TLB. " diff --git a/cpu/mpc85xx/mp.h b/cpu/mpc85xx/mp.h index 2c2929e..3422cc1 100644 --- a/cpu/mpc85xx/mp.h +++ b/cpu/mpc85xx/mp.h @@ -3,7 +3,8 @@ #include <asm/mp.h> -ulong get_spin_addr(void); +ulong get_spin_phys_addr(void); +ulong get_spin_virt_addr(void); u32 get_my_id(void); #define BOOT_ENTRY_ADDR_UPPER 0 diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index ecbd0d5..a1ae78a 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -138,23 +138,38 @@ __secondary_start_page: stw r3,ENTRY_R6_UPPER(r10) stw r3,ENTRY_R6_LOWER(r10) + /* load r13 with the address of the 'bootpg' in SDRAM */ + lis r13,toreset(__bootpg_addr)@h + ori r13,r13,toreset(__bootpg_addr)@l + lwz r13,0(r13) + /* setup mapping for AS = 1, and jump there */ lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h mtspr SPRN_MAS0,r11 lis r11,(MAS1_VALID|MAS1_IPROT)@h ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr SPRN_MAS1,r11 - lis r11,(0xfffff000|MAS2_I)@h - ori r11,r11,(0xfffff000|MAS2_I)@l + oris r11,r13,(MAS2_I)@h + ori r11,r13,(MAS2_I)@l mtspr SPRN_MAS2,r11 - lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h - ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l + oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h + ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l mtspr SPRN_MAS3,r11 tlbwe bl 1f 1: mflr r11 - addi r11,r11,28 + /* + * OR in 0xfff to create a mask of the bootpg SDRAM address. We use + * this mask to fixup the cpu spin table and the address that we want + * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the + * bootpg is at 0x7ffff000 in SDRAM. + */ + ori r13,r13,0xfff + and r11, r11, r13 + and r10, r10, r13 + + addi r11,r11,(2f-1b) mfmsr r13 ori r12,r13,MSR_IS|MSR_DS@l @@ -227,6 +242,15 @@ __secondary_start_page: mtspr SPRN_SRR1,r13 rfi + /* + * Allocate some space for the SDRAM address of the bootpg. + * This variable has to be in the boot page so that it can + * be accessed by secondary cores when they come out of reset. + */ + .globl __bootpg_addr +__bootpg_addr: + .long 0 + .align L1_CACHE_SHIFT .globl __spin_table __spin_table: diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index eba7901..af0853b 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -47,6 +47,16 @@ #define CONFIG_MAX_CPUS 1 #endif +/* + * Provide a default boot page translation virtual address that lines up with + * Freescale's default e500 reset page. + */ +#if (defined(CONFIG_E500) && defined(CONFIG_MP)) +#ifndef CONFIG_BPTR_VIRT_ADDR +#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 +#endif +#endif + /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS -- 1.6.2.1

2 3

[U-Boot] [PATCH]85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate
by Poonam Aggrwal 27 Oct '09

27 Oct '09

Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/p1_p2_rdb/ddr.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 08d3aaa..658347b 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -86,8 +86,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00440862 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00040852 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 -- 1.5.6.5

2 1

[U-Boot] [PATCH]85xx/p1_p2rdb: Bug Fix: Crash while configuring 32 bit DDR i/f for P1020RDB.
by Poonam Aggrwal 27 Oct '09

27 Oct '09

The data being modified was in NOR flash which caused the crash. file->board/freescale/p1_p2_rdb/ddr.c function->fixed_sdram() Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/p1_p2_rdb/ddr.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 90d86ec..a30b695 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -211,7 +211,7 @@ phys_size_t fixed_sdram (void) { sys_info_t sysinfo; char buf[32]; - fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL; + fsl_ddr_cfg_regs_t ddr_cfg_regs; size_t ddr_size; struct cpu_type *cpu; @@ -220,13 +220,13 @@ phys_size_t fixed_sdram (void) strmhz(buf, sysinfo.freqDDRBus)); if(sysinfo.freqDDRBus <= DATARATE_400MHZ) - ddr_cfg_regs = &ddr_cfg_regs_400; + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs)); else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) - ddr_cfg_regs = &ddr_cfg_regs_533; + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs)); else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) - ddr_cfg_regs = &ddr_cfg_regs_667; + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs)); else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) - ddr_cfg_regs = &ddr_cfg_regs_800; + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); else panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, sysinfo.freqDDRBus)); @@ -235,14 +235,14 @@ phys_size_t fixed_sdram (void) /* P1020 and it's derivatives support max 32bit DDR width */ if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { - ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE; - ddr_cfg_regs->cs[0].bnds = 0x0000001F; + ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; + ddr_cfg_regs.cs[0].bnds = 0x0000001F; ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } else ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); return ddr_size; } -- 1.5.6.5

2 1

[U-Boot] u-boot beagleboard Rev C. usb support.
by john hagen 27 Oct '09

27 Oct '09

Hello, I'm trying to determine my chances at getting my beagleboard (Rev C) to boot from the usb OTG port using a usb pen drive. I see in the latest tree that the beagle board configuration does not have USB related (STORAGE, EHCI) things enabled. Has anyone attempted this? Thanks JH

1 0