October 2009 - U-Boot

[U-Boot] Please pull u-boot-cfi-flash/master
by Stefan Roese 28 Oct '09

28 Oct '09

Hi Wolfgang, please pull this update. Thanks. The following changes since commit 4946775c6db52dba28f72ba3525764b54f1d4593: Wolfgang Denk (1): Coding Style cleanup; update CHANGELOG, prepare -rc1 are available in the git repository at: git://www.denx.de/git/u-boot-cfi-flash.git master Stefan Roese (1): cfi: Add weak default function for flash_cmd_reset() drivers/mtd/cfi_flash.c | 151 ++++++--------------------------------------- include/mtd/cfi_flash.h | 157 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+), 133 deletions(-) create mode 100644 include/mtd/cfi_flash.h

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[U-Boot] Pull request: u-boot-sparc
by Daniel Hellstrom 28 Oct '09

28 Oct '09

Dear Wolfgang, Please pull from the master branch at git://www.denx.de/git/u-boot-sparc.git Thanks, Daniel The following changes since commit f3ee25859e3920ee7c7cc519a3e6f60d70d7a53f: Matthias Fuchs (1): License cleanup: Fix license header for some esd display configurations are available in the git repository at: git://www.denx.de/git/u-boot-sparc.git testing Sergey Mironov (1): Fix bug in jumptable call stubs for SPARC. examples/standalone/stubs.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)

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Re: [U-Boot] medical profession listings
by Carlo Thomas 28 Oct '09

28 Oct '09

Beat the Recession - get more new clients now. Medical Community Contact Lists that will generate results: Doctors, Dentists, Chiropractors, Hospitals etc.. Drop me a line here for more info & samples: Vince(a)listexperts.us send an email to exit(a)listexperts.us to be taken off future mailing.

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[U-Boot] [PATCH] AT91RM9200: real pointer variable for PORT A to D configuration
by Jens Scharsig 28 Oct '09

28 Oct '09

adds real pointer variable for use with use I/O accessors * defines for PORT A to D configuration registers * defines for SMC configuration registers Signed-off-by: Jens Scharsig <esw(a)bus-elektronik.de> --- diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 00bae1c..1b4667e 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -251,6 +251,15 @@ typedef struct _AT91S_SMC2 AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ } AT91S_SMC2, *AT91PS_SMC2; +#define AT91C_SMC_CSR0 ((AT91_REG *) 0xFFFFFF70) +#define AT91C_SMC_CSR1 ((AT91_REG *) 0xFFFFFF74) +#define AT91C_SMC_CSR2 ((AT91_REG *) 0xFFFFFF78) +#define AT91C_SMC_CSR3 ((AT91_REG *) 0xFFFFFF7C) +#define AT91C_SMC_CSR4 ((AT91_REG *) 0xFFFFFF80) +#define AT91C_SMC_CSR5 ((AT91_REG *) 0xFFFFFF84) +#define AT91C_SMC_CSR6 ((AT91_REG *) 0xFFFFFF88) +#define AT91C_SMC_CSR7 ((AT91_REG *) 0xFFFFFF8C) + /* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ #define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ @@ -586,6 +595,7 @@ typedef struct _AT91S_PDC #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ + #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ @@ -615,7 +625,96 @@ typedef struct _AT91S_PDC #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ + +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) +#define AT91C_PIOB_PUDR ((AT91_REG *) 0xFFFFF660) +#define AT91C_PIOB_PUER ((AT91_REG *) 0xFFFFF664) +#define AT91C_PIOB_PUSR ((AT91_REG *) 0xFFFFF668) +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) + +#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) +#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) +#define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) +#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) +#define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) +#define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) +#define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) +#define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) +#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) +#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) +#define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) +#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) +#define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) +#define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) +#define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) +#define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) +#define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) +#define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) +#define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) +#define AT91C_PIOC_PUDR ((AT91_REG *) 0xFFFFF860) +#define AT91C_PIOC_PUER ((AT91_REG *) 0xFFFFF864) +#define AT91C_PIOC_PUSR ((AT91_REG *) 0xFFFFF868) +#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) +#define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) +#define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) +#define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) +#define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) +#define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) + +#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) +#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) +#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) +#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) +#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) +#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) +#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) +#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) +#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) +#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) +#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) +#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) +#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) +#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) +#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) +#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) +#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) +#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) +#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) +#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) +#define AT91C_PIOD_PUDR ((AT91_REG *) 0xFFFFFA60) +#define AT91C_PIOD_PUER ((AT91_REG *) 0xFFFFFA64) +#define AT91C_PIOD_PUSR ((AT91_REG *) 0xFFFFFA68) +#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) +#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) +#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) +#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) +#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) +#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ #define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ @@ -638,6 +737,7 @@ typedef struct _AT91S_PDC #define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ #define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ #define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ +#define AT91C_ID_PIOD ((unsigned int) 5) /* PIO port D BGA only */ #define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ #define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ #define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ @@ -730,17 +830,39 @@ typedef struct _AT91S_PDC #define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ #define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ +#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) +#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) +#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) +#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) +#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) +#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) +#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) +#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) +#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) +#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) +#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) +#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) +#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) +#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) +#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) +#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) +#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) +#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) +#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) +#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) +#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) +#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) +#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) +#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) +#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) +#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) +#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) +#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) #define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ -#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ -#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ -#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */ #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ @@ -774,12 +896,6 @@ typedef struct _AT91S_PDC #define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ -#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ -#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ #else /* flash */

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[U-Boot] [PATCH] galaxy5200: Add default environment variables
by Eric Millbrandt 28 Oct '09

28 Oct '09

Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use reset to retry. Define default bootcommand and bootargs for production. Signed-off-by: Eric Millbrandt <emillbrandt(a)dekaresearch.com> --- include/configs/galaxy5200.h | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 931acfb..4be28b2 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -88,15 +88,21 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ /* even with bootdelay=0 */ -#undef CONFIG_BOOTARGS +#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */ +#define CONFIG_RESET_TO_RETRY #define CONFIG_PREBOOT "echo;" \ "echo Welcome to U-Boot;"\ "echo" +#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \ + "bootm ff040000 ff900000 fffc0000" +#define CONFIG_BOOTARGS "console=ttyPSC0,115200" +#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0" + /* * IPB Bus clocking configuration. */ -- 1.6.3.1

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[U-Boot] u-boot.bin
by David Kaplan 28 Oct '09

28 Oct '09

What sort of generated file size should i expect for the u-boot.bin file? I know it's impossible for anyone to tell me exactly, but in what region of sizes are we talking?

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[U-Boot] [PATCH] MCF532x: make icache_enable use CONFIG_SYS_SDRAM_SIZE
by Wolfgang Wegner 28 Oct '09

28 Oct '09

in cpu/mcf532x/start.S, the function icache_enable enables the cache for a fixed 32MB region starting at the SDRAM start address; this patch changes the function to cover the region defined by CONFIG_SYS_SDRAM_SIZE Signed-off-by: Wolfgang Wegner <w.wegner(a)astro-kom.de> --- cpu/mcf532x/start.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index a46c47a..ff13a9f 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -280,7 +280,7 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 + move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0 movec %d0, %ACR0 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ -- 1.5.6.5

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[U-Boot] [PATCH] 85xx: Add support for e500mc cache stashing
by Kumar Gala 28 Oct '09

28 Oct '09

The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/cpu_init.c | 5 +++++ cpu/mpc85xx/fdt.c | 18 ++++++++++++++++++ cpu/mpc85xx/release.S | 13 +++++++++++++ cpu/mpc85xx/start.S | 8 +++++++- 4 files changed, 43 insertions(+), 1 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0041a60..16ce82c 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -357,6 +357,11 @@ int cpu_init_r(void) while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + mtspr(SPRN_L2CSR1, (32 + 1)); +#endif + /* enable the cache */ mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index de2dcac..5f9aeb1 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -197,6 +197,15 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } +#ifdef CONFIG_SYS_CACHE_STASHING + { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + if (reg) + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg * 2) + 32 + 1); + } +#endif + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); fdt_setprop_cell(blob, l2_off, "cache-size", size); @@ -252,6 +261,15 @@ static inline void ft_fixup_cache(void *blob) fdt_setprop_cell(blob, off, "d-cache-size", dsize); fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); +#ifdef CONFIG_SYS_CACHE_STASHING + { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + if (reg) + fdt_setprop_cell(blob, off, "cache-stash-id", + (*reg * 2) + 32 + 0); + } +#endif + /* i-side config */ isize = (l1cfg1 & 0x7ff) * 1024; inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index a1ae78a..58c2bb9 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -99,6 +99,13 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8 +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync @@ -110,6 +117,12 @@ __secondary_start_page: andis. r1,r3,L2CSR0_L2FI@h bne 1b +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + addi r3,r8,1 + mtspr SPRN_L2CSR1,r3 +#endif + lis r3,CONFIG_SYS_INIT_L2CSR0@h ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 6a86528..7e60e67 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -102,6 +102,12 @@ _start_e500: * */ +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + li r2,(32 + 0) + mtspr L1CSR2,r2 +#endif + lis r2,L1CSR0_CPE@H /* enable parity */ ori r2,r2,L1CSR0_DCE mtspr L1CSR0,r2 /* enable L1 Dcache */ -- 1.6.0.6

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[U-Boot] [PATCH] ppc/p4080: Added p4080 SERDES registers & USB offset
by Kumar Gala 28 Oct '09

28 Oct '09

Added immap definition for SERDES registers on p4080, the USB offset (since it was missing) and a GPL header. Signed-off-by: Li Yang <leoli(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/asm-ppc/immap_85xx.h | 83 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 83 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 4194295..0ce93e3 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -6,6 +6,23 @@ * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao(a)motorola.com) * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __IMMAP_85xx__ @@ -1847,17 +1864,81 @@ typedef struct ccsr_gur { } ccsr_gur_t; #endif +typedef struct serdes_corenet { + struct { + u32 rstctl; /* Reset Control Register */ +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 + u32 pllcr0; /* PLL Control Register 0 */ + u32 pllcr1; /* PLL Control Register 1 */ + u32 res[5]; + } bank[3]; + u32 res1[12]; + u32 srdstcalcr; /* TX Calibration Control */ + u32 res2[3]; + u32 srdsrcalcr; /* RX Calibration Control */ + u32 res3[3]; + u32 srdsgr0; /* General Register 0 */ + u32 res4[11]; + u32 srdspccr0; /* Protocol Converter Config 0 */ + u32 srdspccr1; /* Protocol Converter Config 1 */ + u32 srdspccr2; /* Protocol Converter Config 2 */ + u32 res5[197]; + struct { + u32 gcr0; /* General Control Register 0 */ +#define SRDS_GCR0_1STLANE 0x00010000 + u32 gcr1; /* General Control Register 1 */ +#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 +#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 +#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 +#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 +#define SRDS_GCR1_OPAD_CTL 0x04000000 + u32 res1[4]; + u32 tecr0; /* TX Equalization Control Reg 0 */ +#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 +#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 + u32 res3; + u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ + u32 res4[7]; + } lane[24]; + u32 res6[384]; +} serdes_corenet_t; + +enum { + FSL_SRDS_B1_LANE_A = 0, + FSL_SRDS_B1_LANE_B = 1, + FSL_SRDS_B1_LANE_C = 2, + FSL_SRDS_B1_LANE_D = 3, + FSL_SRDS_B1_LANE_E = 4, + FSL_SRDS_B1_LANE_F = 5, + FSL_SRDS_B1_LANE_G = 6, + FSL_SRDS_B1_LANE_H = 7, + FSL_SRDS_B1_LANE_I = 8, + FSL_SRDS_B1_LANE_J = 9, + FSL_SRDS_B2_LANE_A = 16, + FSL_SRDS_B2_LANE_B = 17, + FSL_SRDS_B2_LANE_C = 18, + FSL_SRDS_B2_LANE_D = 19, + FSL_SRDS_B3_LANE_A = 20, + FSL_SRDS_B3_LANE_B = 21, + FSL_SRDS_B3_LANE_C = 22, + FSL_SRDS_B3_LANE_D = 23, +}; + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #else @@ -1929,6 +2010,8 @@ typedef struct ccsr_gur { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) -- 1.6.0.6

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[U-Boot] NAND and new board
by David Kaplan 28 Oct '09

28 Oct '09

I'm trying to add config for a new board (custom board with s3c2410). I am confused about how to define NAND mem. The chip in question is a Samsung K9F5608U0D (32M NAND). I have noticed various nand.c files in board/*. Are any of those good enough for me (and I can add to my board) or do I need to build my own? If I need to do it myself, would anyone be able to provide a few pointers?

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