August 2008 - U-Boot

[U-Boot] [PATCH] Add command to enable/disable interrupts
by Kumar Gala 12 Aug '08

12 Aug '08

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- This is part of my bootm work, but clearly the patch is standalone. - k common/Makefile | 1 + common/cmd_irq.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 0 deletions(-) create mode 100644 common/cmd_irq.c diff --git a/common/Makefile b/common/Makefile index 4287108..ca838ff 100644 --- a/common/Makefile +++ b/common/Makefile @@ -69,6 +69,7 @@ endif COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o +COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o COBJS-y += cmd_load.o diff --git a/common/cmd_irq.c b/common/cmd_irq.c new file mode 100644 index 0000000..04914c6 --- /dev/null +++ b/common/cmd_irq.c @@ -0,0 +1,50 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <command.h> + +int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + if (argc != 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* on */ + if (strncmp(argv[1], "on", 2) == 0) { + enable_interrupts(); + } else { + disable_interrupts(); + } + + return 0; +} + +U_BOOT_CMD( + interrupts, 5, 0, do_interrupts, + "interrupts - enable or disable interrupts\n", + "[on, off]\n" + " - enable or disable interrupts\n" +); -- 1.5.5.1

1 0

[U-Boot] [PATCH] Change CFG_ENV_SIZE to CFG_ENV_SECT_SIZE for SPI sector erase
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> The CFG_ENV_SIZE is not suitable used for SPI flash erase sector size. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- common/env_sf.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/env_sf.c b/common/env_sf.c index d641a9a..0a0626e 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -69,7 +69,7 @@ int saveenv(void) } puts("Erasing SPI flash..."); - if (spi_flash_erase(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE)) + if (spi_flash_erase(env_flash, CFG_ENV_OFFSET, CFG_ENV_SECT_SIZE)) return 1; puts("Writing to SPI flash..."); -- 1.5.6.4

3 2

[U-Boot] AT91 Pull Request
by Jean-Christophe PLAGNIOL-VILLARD 12 Aug '08

12 Aug '08

Hi Wolfgang please pull The following changes since commit cd82919e6c8a73b363a26f34b734923844e52d1c: Wolfgang Denk (1): Coding style cleanup, update CHANGELOG, prepare release are available in the git repository at: git://git.denx.de/u-boot-at91.git master Jean-Christophe PLAGNIOL-VILLARD (1): at91: move arch-at91sam9 to arch-at91 Makefile | 10 +++++----- cpu/arm926ejs/{at91sam9 => at91}/Makefile | 0 cpu/arm926ejs/{at91sam9 => at91}/config.mk | 2 +- cpu/arm926ejs/{at91sam9 => at91}/ether.c | 0 cpu/arm926ejs/{at91sam9 => at91}/lowlevel_init.S | 0 cpu/arm926ejs/{at91sam9 => at91}/spi.c | 0 cpu/arm926ejs/{at91sam9 => at91}/timer.c | 0 cpu/arm926ejs/{at91sam9 => at91}/u-boot.lds | 0 cpu/arm926ejs/{at91sam9 => at91}/usb.c | 0 .../{arch-at91sam9 => arch-at91}/at91_pio.h | 0 .../{arch-at91sam9 => arch-at91}/at91_pit.h | 0 .../{arch-at91sam9 => arch-at91}/at91_pmc.h | 0 .../{arch-at91sam9 => arch-at91}/at91_rstc.h | 0 .../{arch-at91sam9 => arch-at91}/at91_spi.h | 0 .../{arch-at91sam9 => arch-at91}/at91cap9.h | 0 .../{arch-at91sam9 => arch-at91}/at91cap9_matrix.h | 0 .../{arch-at91sam9 => arch-at91}/at91sam9260.h | 0 .../at91sam9260_matrix.h | 0 .../{arch-at91sam9 => arch-at91}/at91sam9261.h | 0 .../at91sam9261_matrix.h | 0 .../{arch-at91sam9 => arch-at91}/at91sam9263.h | 0 .../at91sam9263_matrix.h | 0 .../{arch-at91sam9 => arch-at91}/at91sam9_smc.h | 0 .../{arch-at91sam9 => arch-at91}/at91sam9rl.h | 0 .../at91sam9rl_matrix.h | 0 include/asm-arm/{arch-at91sam9 => arch-at91}/clk.h | 0 .../asm-arm/{arch-at91sam9 => arch-at91}/gpio.h | 0 .../{arch-at91sam9 => arch-at91}/hardware.h | 0 include/asm-arm/{arch-at91sam9 => arch-at91}/io.h | 0 .../{arch-at91sam9 => arch-at91}/memory-map.h | 0 30 files changed, 6 insertions(+), 6 deletions(-) rename cpu/arm926ejs/{at91sam9 => at91}/Makefile (100%) rename cpu/arm926ejs/{at91sam9 => at91}/config.mk (62%) rename cpu/arm926ejs/{at91sam9 => at91}/ether.c (100%) rename cpu/arm926ejs/{at91sam9 => at91}/lowlevel_init.S (100%) rename cpu/arm926ejs/{at91sam9 => at91}/spi.c (100%) rename cpu/arm926ejs/{at91sam9 => at91}/timer.c (100%) rename cpu/arm926ejs/{at91sam9 => at91}/u-boot.lds (100%) rename cpu/arm926ejs/{at91sam9 => at91}/usb.c (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91_pio.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91_pit.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91_pmc.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91_rstc.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91_spi.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91cap9.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91cap9_matrix.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9260.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9260_matrix.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9261.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9261_matrix.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9263.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9263_matrix.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9_smc.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9rl.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/at91sam9rl_matrix.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/clk.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/gpio.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/hardware.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/io.h (100%) rename include/asm-arm/{arch-at91sam9 => arch-at91}/memory-map.h (100%) Best Regards, J.

2 1

[U-Boot] [PATCH 01/14] Add proper SPD definitions for DDR1/2/3
by Kumar Gala 12 Aug '08

12 Aug '08

From: James Yang <James.Yang(a)freescale.com> Also added a few helper functions for DDR1 & DDR2 to print SPD info and verify the checksum. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- common/Makefile | 1 + common/ddr_spd.c | 498 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/ddr_spd.h | 249 ++++++++++++++++++++++++++ 3 files changed, 748 insertions(+), 0 deletions(-) create mode 100644 common/ddr_spd.c create mode 100644 include/ddr_spd.h diff --git a/common/Makefile b/common/Makefile index 4287108..3ea4abf 100644 --- a/common/Makefile +++ b/common/Makefile @@ -144,6 +144,7 @@ COBJS-y += cmd_mac.o COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o COBJS-$(CONFIG_MP) += cmd_mp.o COBJS-$(CONFIG_CMD_SF) += cmd_sf.o +COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o COBJS := $(COBJS-y) SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/common/ddr_spd.c b/common/ddr_spd.c new file mode 100644 index 0000000..e4be34f --- /dev/null +++ b/common/ddr_spd.c @@ -0,0 +1,498 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <ddr_spd.h> + +void +ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", + 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", + 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", + 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", + 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", + 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", + 5, spd->nrows, + " spd->nrows * 5 # of DIMM Banks *"); + printf("%-3d : %02x %s\n", + 6, spd->dataw_lsb, + " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); + printf("%-3d : %02x %s\n", + 7, spd->dataw_msb, + " spd->dataw_msb, * 7 Data Width msb of this assembly *"); + printf("%-3d : %02x %s\n", + 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", + 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", + 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", + 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", + 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", + 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", + 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", + 15, spd->min_delay, + " spd->min_delay, * 15 Back to Back Random Access *"); + printf("%-3d : %02x %s\n", + 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", + 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", + 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", + 19, spd->cs_lat, + " spd->cs_lat, * 19 Chip Select Latency *"); + printf("%-3d : %02x %s\n", + 20, spd->write_lat, + " spd->write_lat, * 20 Write Latency/Recovery *"); + printf("%-3d : %02x %s\n", + 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", + 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", + 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", + 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", + 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", + 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", + 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", + 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", + 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", + 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", + 31, spd->bank_dens, + " spd->bank_dens, * 31 Density of each bank on module *"); + printf("%-3d : %02x %s\n", + 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", + 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", + 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", + 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", + 36, spd->res_36_40[0], + " spd->res_36_40[0], * 36 Reserved / tWR *"); + printf("%-3d : %02x %s\n", + 37, spd->res_36_40[1], + " spd->res_36_40[1], * 37 Reserved / tWTR *"); + printf("%-3d : %02x %s\n", + 38, spd->res_36_40[2], + " spd->res_36_40[2], * 38 Reserved / tRTP *"); + printf("%-3d : %02x %s\n", + 39, spd->res_36_40[3], + " spd->res_36_40[3], * 39 Reserved / mem_probe *"); + printf("%-3d : %02x %s\n", + 40, spd->res_36_40[4], + " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); + printf("%-3d : %02x %s\n", + 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", + 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", + 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", + 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", + 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", + 46, spd->res_46, + " spd->res_46, * 46 Reserved/ PLL Relock time *"); + printf("%-3d : %02x %s\n", + 47, spd->dimm_height, + " spd->dimm_height * 47 SDRAM DIMM Height *"); + + printf("%-3d-%3d: ", 48, 61); + for (i = 0; i < 14; i++) { + printf("%02x", spd->res_48_61[i]); + } + printf(" * 48-61 IDD in SPD and Reserved space *\n"); + + printf("%-3d : %02x %s\n", + 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", + 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) { + printf("%02x", spd->mid[i]); + } + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + printf("%-3d : %02x %s\n", + 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + for (i = 0; i < 18; i++) { + printf("%c", spd->mpart[i]); + } + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", + 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", + 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) { + printf("%02x", spd->sernum[i]); + } + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + for (i = 0; i < 27; i++) { + printf("%02x", spd->mspec[i]); + } + + printf("* 99 Manufacturer Specific Data *\n"); +} + +void +ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", + 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", + 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", + 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", + 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", + 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", + 5, spd->mod_ranks, + " spd->mod_ranks * 5 # of Module Rows on this assembly *"); + printf("%-3d : %02x %s\n", + 6, spd->dataw, + " spd->dataw, * 6 Data Width of this assembly *"); + printf("%-3d : %02x %s\n", + 7, spd->res_7, + " spd->res_7, * 7 Reserved *"); + printf("%-3d : %02x %s\n", + 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", + 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", + 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", + 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", + 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", + 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", + 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", + 15, spd->res_15, + " spd->res_15, * 15 Reserved *"); + printf("%-3d : %02x %s\n", + 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", + 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", + 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", + 19, spd->mech_char, + " spd->mech_char, * 19 Mechanical Characteristics *"); + printf("%-3d : %02x %s\n", + 20, spd->dimm_type, + " spd->dimm_type, * 20 DIMM type *"); + printf("%-3d : %02x %s\n", + 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", + 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", + 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", + 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", + 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", + 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", + 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", + 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", + 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", + 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", + 31, spd->rank_dens, + " spd->rank_dens, * 31 Density of each rank on module *"); + printf("%-3d : %02x %s\n", + 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", + 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", + 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", + 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", + 36, spd->twr, + " spd->twr, * 36 Write Recovery time tWR *"); + printf("%-3d : %02x %s\n", + 37, spd->twtr, + " spd->twtr, * 37 Int write to read delay tWTR *"); + printf("%-3d : %02x %s\n", + 38, spd->trtp, + " spd->trtp, * 38 Int read to precharge delay tRTP *"); + printf("%-3d : %02x %s\n", + 39, spd->mem_probe, + " spd->mem_probe, * 39 Mem analysis probe characteristics *"); + printf("%-3d : %02x %s\n", + 40, spd->trctrfc_ext, + " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); + printf("%-3d : %02x %s\n", + 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", + 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", + 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", + 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", + 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", + 46, spd->pll_relock, + " spd->pll_relock, * 46 PLL Relock time *"); + printf("%-3d : %02x %s\n", + 47, spd->Tcasemax, + " spd->Tcasemax, * 47 Tcasemax *"); + printf("%-3d : %02x %s\n", + 48, spd->psiTAdram, + " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) *"); + printf("%-3d : %02x %s\n", + 49, spd->dt0_mode, + " spd->dt0_mode, * 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) *)"); + printf("%-3d : %02x %s\n", + 50, spd->dt2n_dt2q, + " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) *"); + printf("%-3d : %02x %s\n", + 51, spd->dt2p, + " spd->dt2p, * 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down (DT2P) *"); + printf("%-3d : %02x %s\n", + 52, spd->dt3n, + " spd->dt3n, * 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) *"); + printf("%-3d : %02x %s\n", + 53, spd->dt3pfast, + " spd->dt3pfast, * 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3Pfast) *"); + printf("%-3d : %02x %s\n", + 54, spd->dt3pslow, + " spd->dt3pslow, * 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3Pslow) *"); + printf("%-3d : %02x %s\n", + 55, spd->dt4r_dt4r4w, + " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) *"); + printf("%-3d : %02x %s\n", + 56, spd->dt5b, + " spd->dt5b, * 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) *"); + printf("%-3d : %02x %s\n", + 57, spd->dt7, + " spd->dt7, * 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) *"); + printf("%-3d : %02x %s\n", + 58, spd->psiTApll, + " spd->psiTApll, * 58 Thermal Resistance of PLL Package form Top (Case) to Ambient (Psi T-A PLL) *"); + printf("%-3d : %02x %s\n", + 59, spd->psiTAreg, + " spd->psiTAreg, * 59 Thermal Reisitance of Register Package from Top (Case) to Ambient (Psi T-A Register) *"); + printf("%-3d : %02x %s\n", + 60, spd->dtpllactive, + " spd->dtpllactive, * 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) *"); + printf("%-3d : %02x %s\n", + 61, spd->dtregact, + " spd->dtregact, * 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) *"); + printf("%-3d : %02x %s\n", + 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", + 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) { + printf("%02x", spd->mid[i]); + } + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + printf("%-3d : %02x %s\n", + 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + for (i = 0; i < 18; i++) { + printf("%c", spd->mpart[i]); + } + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", + 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", + 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) { + printf("%02x", spd->sernum[i]); + } + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + for (i = 0; i < 27; i++) { + printf("%02x", spd->mspec[i]); + } + + printf("* 99 Manufacturer Specific Data *\n"); +} + +/* used for ddr1 and ddr2 spd */ +static int +spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) +{ + unsigned int cksum = 0; + unsigned int i; + + /* + * Check SPD revision supported + * Rev 1.2 or less supported by this code + */ + if (spd_rev > 0x12) { + printf("SPD revision %02X not supported by this code\n", + spd_rev); + return 1; + } + + /* + * Calculate checksum + */ + for (i = 0; i < 63; i++) { + cksum += *buf++; + } + cksum &= 0xFF; + + if (cksum != spd_cksum) { + printf("SPD checksum unexpected. " + "Checksum in SPD = %02X, computed SPD = %02X\n", + spd_cksum, cksum); + return 1; + } + + return 0; +} + +unsigned int +ddr1_spd_check(const ddr1_spd_eeprom_t *spd) +{ + const u8 *p = (const u8 *)spd; + + return spd_check(p, spd->spd_rev, spd->cksum); +} + +unsigned int +ddr2_spd_check(const ddr2_spd_eeprom_t *spd) +{ + const u8 *p = (const u8 *)spd; + + return spd_check(p, spd->spd_rev, spd->cksum); +} diff --git a/include/ddr_spd.h b/include/ddr_spd.h new file mode 100644 index 0000000..1a1c99b --- /dev/null +++ b/include/ddr_spd.h @@ -0,0 +1,249 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef _DDR_SPD_H_ +#define _DDR_SPD_H_ + +/* + * Format from "JEDEC Standard No. 21-C, + * Appendix D: Rev 1.0: SPD's for DDR SDRAM + */ +typedef struct ddr1_spd_eeprom_s { + unsigned char info_size; /* 0 # bytes written into serial memory */ + unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Fundamental memory type */ + unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ + unsigned char nrows; /* 5 Number of DIMM Banks */ + unsigned char dataw_lsb; /* 6 Data Width of this assembly */ + unsigned char dataw_msb; /* 7 ... Data Width continuation */ + unsigned char voltage; /* 8 Voltage intf std of this assembly */ + unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */ + unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X (tAC) */ + unsigned char config; /* 11 DIMM Configuration type */ + unsigned char refresh; /* 12 Refresh Rate/Type */ + unsigned char primw; /* 13 Primary SDRAM Width */ + unsigned char ecw; /* 14 Error Checking SDRAM width */ + unsigned char min_delay; /* 15 for Back to Back Random Address */ + unsigned char burstl; /* 16 Burst Lengths Supported */ + unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ + unsigned char cas_lat; /* 18 CAS# Latencies Supported */ + unsigned char cs_lat; /* 19 CS# Latency */ + unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ + unsigned char mod_attr; /* 21 SDRAM Module Attributes */ + unsigned char dev_attr; /* 22 SDRAM Device Attributes */ + unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-0.5 */ + unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-0.5 (tAC) */ + unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-1 */ + unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-1 (tAC) */ + unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ + unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ + unsigned char bank_dens; /* 31 Density of each bank on module */ + unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clock */ + unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clock */ + unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ + unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ + unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ + unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ + unsigned char trfc; /* 42 Min Auto to Active period tRFC */ + unsigned char tckmax; /* 43 Max device cycle time tCKmax */ + unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ + unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ + unsigned char res_46; /* 46 Reserved */ + unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ + unsigned char res_48_61[14]; /* 48-61 Reserved */ + unsigned char spd_rev; /* 62 SPD Data Revision Code */ + unsigned char cksum; /* 63 Checksum for bytes 0-62 */ + unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ + unsigned char mloc; /* 72 Manufacturing Location */ + unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ + unsigned char rev[2]; /* 91 Revision Code */ + unsigned char mdate[2]; /* 93 Manufacturing Date */ + unsigned char sernum[4]; /* 95 Assembly Serial Number */ + unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ + +} ddr1_spd_eeprom_t; + +/* + * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", + * SPD Revision 1.2 + */ +typedef struct ddr2_spd_eeprom_s { + unsigned char info_size; /* 0 # bytes written into serial memory */ + unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Fundamental memory type */ + unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ + unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ + unsigned char dataw; /* 6 Module Data Width */ + unsigned char res_7; /* 7 Reserved */ + unsigned char voltage; /* 8 Voltage intf std of this assembly */ + unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */ + unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X (tAC) */ + unsigned char config; /* 11 DIMM Configuration type */ + unsigned char refresh; /* 12 Refresh Rate/Type */ + unsigned char primw; /* 13 Primary SDRAM Width */ + unsigned char ecw; /* 14 Error Checking SDRAM width */ + unsigned char res_15; /* 15 Reserved */ + unsigned char burstl; /* 16 Burst Lengths Supported */ + unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ + unsigned char cas_lat; /* 18 CAS# Latencies Supported */ + unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ + unsigned char dimm_type; /* 20 DIMM type information */ + unsigned char mod_attr; /* 21 SDRAM Module Attributes */ + unsigned char dev_attr; /* 22 SDRAM Device Attributes */ + unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */ + unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 (tAC) */ + unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */ + unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 (tAC) */ + unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ + unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ + unsigned char rank_dens; /* 31 Density of each rank on module */ + unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clock (tIS) */ + unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clock (tIH) */ + unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe (tDS) */ + unsigned char data_hold; /* 35 Data Input Hold Time After Strobe (tDH) */ + unsigned char twr; /* 36 Write Recovery time tWR */ + unsigned char twtr; /* 37 Int write to read delay tWTR */ + unsigned char trtp; /* 38 Int read to precharge delay tRTP */ + unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ + unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ + unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ + unsigned char trfc; /* 42 Min Auto to Active period tRFC */ + unsigned char tckmax; /* 43 Max device cycle time tCKmax */ + unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ + unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ + unsigned char pll_relock; /* 46 PLL Relock time */ + unsigned char Tcasemax; /* 47 Tcasemax */ + unsigned char psiTAdram; /* 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) */ + unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) */ + unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) */ + unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down (DT2P) */ + unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) */ + unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3Pfast) */ + unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3Pslow) */ + unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) */ + unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) */ + unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) */ + unsigned char psiTApll; /* 58 Thermal Resistance of PLL Package form Top (Case) to Ambient (Psi T-A PLL) */ + unsigned char psiTAreg; /* 59 Thermal Reisitance of Register Package from Top (Case) to Ambient (Psi T-A Register) */ + unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) */ + unsigned char dtregact; /* 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) */ + + unsigned char spd_rev; /* 62 SPD Data Revision Code */ + unsigned char cksum; /* 63 Checksum for bytes 0-62 */ + unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ + unsigned char mloc; /* 72 Manufacturing Location */ + unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ + unsigned char rev[2]; /* 91 Revision Code */ + unsigned char mdate[2]; /* 93 Manufacturing Date */ + unsigned char sernum[4]; /* 95 Assembly Serial Number */ + unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ + +} ddr2_spd_eeprom_t; + +typedef struct ddr3_spd_eeprom_s { + /* General Section: Bytes 0-59 */ + unsigned char info_size_crc; /* 0 # bytes written into serial memory, CRC coverage */ + unsigned char spd_rev; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Key Byte / Fundamental memory type */ + unsigned char module_type; /* 3 Key Byte / Module Type */ + unsigned char density_banks; /* 4 SDRAM Density and Banks */ + unsigned char addressing; /* 5 SDRAM Addressing */ + unsigned char res_6; /* 6 Reserved */ + unsigned char organization; /* 7 Module Organization */ + unsigned char bus_width; /* 8 Module Memory Bus Width */ + unsigned char ftb_div; /* 9 Fine Timebase (FTB) Dividend / Divisor */ + unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ + unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ + unsigned char tCK_min; /* 12 SDRAM Minimum Cycle Time (tCK_min) */ + unsigned char res_13; /* 13 Reserved */ + unsigned char caslat_lsb; /* 14 CAS Latencies Supported, Least Significant Byte */ + unsigned char caslat_msb; /* 15 CAS Latencies Supported, Most Significant Byte */ + unsigned char tAA_min; /* 16 Minimum CAS Latency Time (tAA_min) */ + unsigned char tWR_min; /* 17 Minimum WRite REcovery Time (tWR_min) */ + unsigned char tRCD_min; /* 18 Minimum RAS# to CAS# Delay Time (tRCD_min) */ + unsigned char tRRD_min; /* 19 Minimum Row Active to Row Active Delay Time (tRRD_min) */ + unsigned char tRP_min; /* 20 Minimum Row Precharge Delay Time (tRP_min) */ + unsigned char tRAS_tRC_ext; /* 21 Upper Nibbles for tRAS and tRC */ + unsigned char tRAS_min_lsb; /* 22 Minimum Active to Precharge Delay Time (tRAS_min), LSB */ + unsigned char tRC_min_lsb; /* 23 Minimum Active to Active/Refresh Delay Time (tRC_min), LSB */ + unsigned char tRFC_min_lsb; /* 24 Minimum Refresh Recovery Delay Time (tRFC_min), LSB */ + unsigned char tRFC_min_msb; /* 25 Minimum Refresh Recovery Delay Time (tRFC_min), MSB */ + unsigned char tWTR_min; /* 26 Minimum Internal Write to Read Command Delay Time (tWTR_min) */ + unsigned char tRTP_min; /* 27 Minimum Internal Read to Precharge Command Delay Time (tRTP_min) */ + unsigned char tFAW_msb; /* 28 Upper Nibble for tFAW */ + unsigned char tFAW_min; /* 29 Minimum Four Activate Window Delay Time (tFAW_min), LSB */ + unsigned char opt_features; /* 30 SDRAM Optional Features */ + unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Options */ + unsigned char res_32_59[28]; /* 32-59 Reserved, General Section */ + + /* Module-Specific Section: Bytes 60-116 */ + union { + struct { + unsigned char mod_height; /* 60 (Unbuffered) Module Nominal Height */ + unsigned char mod_thickness; /* 61 (Unbuffered) Module Maximum Thickness */ + unsigned char ref_raw_card; /* 62 (Unbuffered) Reference Raw Card Used */ + unsigned char addr_mapping; /* 63 (Unbuffered) Address Mapping from Edge Connector to DRAM */ + unsigned char res_64_116[53]; /* 64-116 (Unbuffered) Reserved */ + } unbuffered; + struct { + unsigned char mod_height; /* 60 (Registered) Module Nominal Height */ + unsigned char mod_thickness; /* 61 (Registered) Module Maximum Thickness */ + unsigned char ref_raw_card; /* 62 (Registered) Reference Raw Card Used */ + } registered; + unsigned char uc[57]; /* 60-116 Module-Specific Section */ + } mod_section; + + /* Unique Module ID: Bytes 117-125 */ + unsigned char mmid_lsb; /* 117 Module Manufacturer ID Code LSB - JEP-106 */ + unsigned char mmid_msb; /* 118 Module Manufacturer ID Code MSB - JEP-106 */ + unsigned char mloc; /* 119 Manufacturing Location */ + unsigned char mdate[2]; /* 120-121 Manufacturing Date */ + unsigned char sernum[4]; /* 122-125 Module Serial Number */ + + /* CRC: Bytes 126-127 */ + unsigned char crc[2]; /* 126-127 SPD Cyclical Redundancy Code (CRC) */ + + /* Other Manufacturer Fields and User Space: Bytes 128-255 */ + unsigned char mpart[18]; /* 128-145 Manufacturer's Module Part Number */ + unsigned char mrev[2]; /* 146-147 Module Revision Code */ + + unsigned char dmid_lsb; /* 148 DRAM Manufacturer ID Code LSB - JEP-106 */ + unsigned char dmid_msb; /* 149 DRAM Manufacturer ID Code MSB - JEP-106 */ + + unsigned char msd[26]; /* 150-175 Manufacturer's Specific Data */ + unsigned char cust[80]; /* 176-255 Open for Customer Use */ + +} ddr3_spd_eeprom_t; + +extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); +extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); +extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); +extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); + +/* + * Byte 2 Fundamental Memory Types. + */ +#define SPD_MEMTYPE_FPM (0x01) +#define SPD_MEMTYPE_EDO (0x02) +#define SPD_MEMTYPE_PIPE_NIBBLE (0x03) +#define SPD_MEMTYPE_SDRAM (0x04) +#define SPD_MEMTYPE_ROM (0x05) +#define SPD_MEMTYPE_SGRAM (0x06) +#define SPD_MEMTYPE_DDR (0x07) +#define SPD_MEMTYPE_DDR2 (0x08) +#define SPD_MEMTYPE_DDR2_FBDIMM (0x09) +#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) +#define SPD_MEMTYPE_DDR3 (0x0B) + +#endif /* _DDR_SPD_H_ */ -- 1.5.5.1

2 18

[U-Boot] [PATCH 1/3] mpc85xx: Add support for the MPC8572DS reference board
by Kumar Gala 12 Aug '08

12 Aug '08

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- MAKEALL | 1 + Makefile | 3 + board/freescale/mpc8572ds/Makefile | 54 +++ board/freescale/mpc8572ds/config.mk | 32 ++ board/freescale/mpc8572ds/ddr.c | 344 +++++++++++++++++++ board/freescale/mpc8572ds/law.c | 41 +++ board/freescale/mpc8572ds/mpc8572ds.c | 573 +++++++++++++++++++++++++++++++ board/freescale/mpc8572ds/tlb.c | 85 +++++ board/freescale/mpc8572ds/u-boot.lds | 145 ++++++++ cpu/mpc85xx/cpu.c | 2 +- cpu/mpc85xx/pci.c | 2 +- include/configs/MPC8572DS.h | 600 +++++++++++++++++++++++++++++++++ 12 files changed, 1880 insertions(+), 2 deletions(-) create mode 100644 board/freescale/mpc8572ds/Makefile create mode 100644 board/freescale/mpc8572ds/config.mk create mode 100644 board/freescale/mpc8572ds/ddr.c create mode 100644 board/freescale/mpc8572ds/law.c create mode 100644 board/freescale/mpc8572ds/mpc8572ds.c create mode 100644 board/freescale/mpc8572ds/tlb.c create mode 100644 board/freescale/mpc8572ds/u-boot.lds create mode 100644 include/configs/MPC8572DS.h diff --git a/MAKEALL b/MAKEALL index ee83cca..2112936 100755 --- a/MAKEALL +++ b/MAKEALL @@ -352,6 +352,7 @@ LIST_85xx=" \ MPC8555CDS \ MPC8560ADS \ MPC8568MDS \ + MPC8572DS \ PM854 \ PM856 \ sbc8540 \ diff --git a/Makefile b/Makefile index 138dffb..52b658a 100644 --- a/Makefile +++ b/Makefile @@ -2197,6 +2197,9 @@ MPC8555CDS_config: unconfig MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale +MPC8572DS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale + PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile new file mode 100644 index 0000000..3e82bbf --- /dev/null +++ b/board/freescale/mpc8572ds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk new file mode 100644 index 0000000..5b32186 --- /dev/null +++ b/board/freescale/mpc8572ds/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8572ds board +# +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1 diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c new file mode 100644 index 0000000..60b8454 --- /dev/null +++ b/board/freescale/mpc8572ds/ddr.c @@ -0,0 +1,344 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <../cpu/mpc8xxx/fsl_ddr_sdram.h> + +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 +#define SDRAM_TYPE_LPDDR1 6 +#define SDRAM_TYPE_DDR3 7 + + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_sdram_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_sdram_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS1; + } + if (ctrl_num == 1 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS2; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + + +void +fsl_ddr_sdram_dump_memctl_regs(unsigned int ctrl_num) +{ + unsigned int i; + volatile ccsr_ddr_t *ddr; + + if (ctrl_num == 0) + ddr = (void *)CFG_MPC85xx_DDR_ADDR; + else + ddr = (void *)CFG_MPC85xx_DDR2_ADDR; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + unsigned int bnds = 0; + unsigned int config = 0; + unsigned int config_2 = 0; + unsigned int *pbnds = NULL; + unsigned int *pconfig = NULL; + unsigned int *pconfig_2 = NULL; + + if (i == 0) { + bnds = ddr->cs0_bnds; + config = ddr->cs0_config; + config_2 = ddr->cs0_config_2; + pbnds = (unsigned int *)&ddr->cs0_bnds; + pconfig = (unsigned int *)&ddr->cs0_config; + pconfig_2= (unsigned int *)&ddr->cs0_config_2; + + } else if (i == 1) { + bnds = ddr->cs1_bnds; + config = ddr->cs1_config; + config_2 = ddr->cs1_config_2; + pbnds = (unsigned int *)&ddr->cs1_bnds; + pconfig = (unsigned int *)&ddr->cs1_config; + pconfig_2= (unsigned int *)&ddr->cs1_config_2; + + } else if (i == 2) { + bnds = ddr->cs2_bnds; + config = ddr->cs2_config; + config_2 = ddr->cs2_config_2; + pbnds = (unsigned int *)&ddr->cs2_bnds; + pconfig = (unsigned int *)&ddr->cs2_config; + pconfig_2= (unsigned int *)&ddr->cs2_config_2; + + } else if (i == 3) { + bnds = ddr->cs3_bnds; + config = ddr->cs3_config; + config_2 = ddr->cs3_config_2; + pbnds = (unsigned int *) &ddr->cs3_bnds; + pconfig = (unsigned int *) &ddr->cs3_config; + pconfig_2= (unsigned int *) &ddr->cs3_config_2; + + } else { + /* + * FIXME what happens if CONFIG_CHIP_SELECTS_PER_CTRL > 4 + */ + } + + printf("cs%u_bnds = %08X\t%p\n", i, bnds, pbnds); + printf("cs%u_config = %08X\t%p\n", i, config, pconfig); + printf("cs%u_config_2 = %08X\t%p\n", + i, config_2, pconfig_2); + } + + /* + * Due to inconsistencies between immap_85xx.h and immap_86xx.h, + * you will have to modify the structure member names by hand + * between architectures. + */ + printf("timing_cfg_3 = %08X\t%p\n", + ddr->timing_cfg_3, &ddr->timing_cfg_3); + printf("timing_cfg_0 = %08X\t%p\n", + ddr->timing_cfg_0, &ddr->timing_cfg_0); + printf("timing_cfg_1 = %08X\t%p\n", + ddr->timing_cfg_1, &ddr->timing_cfg_1); + printf("timing_cfg_2 = %08X\t%p\n", + ddr->timing_cfg_2, &ddr->timing_cfg_2); +// printf("ddr_sdram_cfg = %08X\t%p\n", +// ddr->sdram_cfg_1, &ddr->sdram_cfg_1); + printf("ddr_sdram_cfg = %08X\t%p\n", + ddr->sdram_cfg, &ddr->sdram_cfg); + printf("ddr_sdram_cfg_2 = %08X\t%p\n", + ddr->sdram_cfg_2, &ddr->sdram_cfg_2); +// printf("ddr_sdram_mode = %08X\t%p\n", +// ddr->sdram_mode_1, &ddr->sdram_mode_1); + printf("ddr_sdram_mode = %08X\t%p\n", + ddr->sdram_mode, &ddr->sdram_mode); + printf("ddr_sdram_mode_2 = %08X\t%p\n", + ddr->sdram_mode_2, &ddr->sdram_mode_2); + printf("ddr_sdram_interval = %08X\t%p\n", + ddr->sdram_interval, &ddr->sdram_interval); + printf("ddr_data_init = %08X\t%p\n", + ddr->sdram_data_init, &ddr->sdram_data_init); + printf("ddr_sdram_clk_cntl = %08X\t%p\n", + ddr->sdram_clk_cntl, &ddr->sdram_clk_cntl); + printf("ddr_init_addr = %08X\t%p\n", + ddr->init_addr, &ddr->init_addr); + printf("ddr_init_ext_addr = %08X\t%p\n", + ddr->init_ext_addr, &ddr->init_ext_addr); + + printf("timing_cfg_4 = %08X\t%p\n", + ddr->timing_cfg_4, &ddr->timing_cfg_4); + printf("timing_cfg_5 = %08X\t%p\n", + ddr->timing_cfg_5, &ddr->timing_cfg_5); + printf("ddr_zq_cntl = %08X\t%p\n", + ddr->ddr_zq_cntl, &ddr->ddr_zq_cntl); + printf("ddr_wrlvl_cntl = %08X\t%p\n", + ddr->ddr_wrlvl_cntl, &ddr->ddr_wrlvl_cntl); + printf("ddr_pd_cntl = %08X\t%p\n", + ddr->ddr_pd_cntl, &ddr->ddr_pd_cntl); + printf("ddr_sr_cntr = %08X\t%p\n", + ddr->ddr_sr_cntr, &ddr->ddr_sr_cntr); + printf("ddr_sdram_rcw_1 = %08X\t%p\n", + ddr->ddr_sdram_rcw_1, &ddr->ddr_sdram_rcw_1); + printf("ddr_sdram_rcw_2 = %08X\t%p\n", + ddr->ddr_sdram_rcw_2, &ddr->ddr_sdram_rcw_2); + + printf("debug_1 = %08X\t%p\n", + ddr->debug_1, &ddr->debug_1); +} + + +void +fsl_ddr_sdram_set_memctl_regs(const fsl_memctl_config_regs_t *regs, + unsigned int ctrl_num) +{ + unsigned int i; + volatile ccsr_ddr_t *ddr; + + switch (ctrl_num) { + case 0: + ddr = (void *)CFG_MPC85xx_DDR_ADDR; + break; + case 1: + ddr = (void *)CFG_MPC85xx_DDR2_ADDR; + break; + default: + printf("fsl_ddr_sdram_set_memctl_regs() unexpected ctrl_num = %u\n", ctrl_num); + return; + } + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + ddr->cs0_bnds = regs->cs[i].bnds; + ddr->cs0_config = regs->cs[i].config; + ddr->cs0_config_2 = regs->cs[i].config_2; + + } else if (i == 1) { + ddr->cs1_bnds = regs->cs[i].bnds; + ddr->cs1_config = regs->cs[i].config; + ddr->cs1_config_2 = regs->cs[i].config_2; + + } else if (i == 2) { + ddr->cs2_bnds = regs->cs[i].bnds; + ddr->cs2_config = regs->cs[i].config; + ddr->cs2_config_2 = regs->cs[i].config_2; + + } else if (i == 3) { + ddr->cs3_bnds = regs->cs[i].bnds; + ddr->cs3_config = regs->cs[i].config; + ddr->cs3_config_2 = regs->cs[i].config_2; + } + } + + /* + * Someone decided to use different names from the documentation... + */ + ddr->timing_cfg_3 = regs->timing_cfg_3; + ddr->timing_cfg_0 = regs->timing_cfg_0; + ddr->timing_cfg_1 = regs->timing_cfg_1; + ddr->timing_cfg_2 = regs->timing_cfg_2; + ddr->sdram_cfg_2 = regs->ddr_sdram_cfg_2; + ddr->sdram_mode = regs->ddr_sdram_mode; + ddr->sdram_mode_2 = regs->ddr_sdram_mode_2; + ddr->sdram_interval = regs->ddr_sdram_interval; + ddr->sdram_data_init = regs->ddr_data_init; + ddr->sdram_clk_cntl = regs->ddr_sdram_clk_cntl; + ddr->init_addr = regs->ddr_init_addr; + ddr->init_ext_addr = regs->ddr_init_ext_addr; + + /* + * FIXME: ECC? Need to program err_disable, err_sbe, and err_int_en + */ + + /* 8572 */ + ddr->timing_cfg_4 = regs->timing_cfg_4; + ddr->timing_cfg_5 = regs->timing_cfg_5; + ddr->ddr_zq_cntl = regs->ddr_zq_cntl; + ddr->ddr_wrlvl_cntl = regs->ddr_wrlvl_cntl; + ddr->ddr_pd_cntl = regs->ddr_pd_cntl; + ddr->ddr_sr_cntr = regs->ddr_sr_cntr; + ddr->ddr_sdram_rcw_1 = regs->ddr_sdram_rcw_1; + ddr->ddr_sdram_rcw_2 = regs->ddr_sdram_rcw_2; + + /* + * 32-bit workaround for DDR2 + * 32_BE + */ + if ((((ddr->sdram_cfg >> 24) & 0x7) == SDRAM_TYPE_DDR2) + && ddr->sdram_cfg_2 & 0x80000) { + /* + * set DEBUG_1[31] + */ + ddr->debug_1 |= 1; + } + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + ddr->sdram_cfg = regs->ddr_sdram_cfg; + + /* + * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. + */ + while (ddr->sdram_cfg_2 & 0x10) { + udelay(10000); /* throttle polling rate */ + } +} + + +unsigned int +fsl_ddr_sdram_type_function(void) +{ + return SDRAM_TYPE_DDR2; +} + + +/* + * factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * FIXME: need to figure out the function parameters necessary to compute + * FIXME: a clock adjust value + */ + +unsigned int +fsl_ddr_sdram_clk_adjust_function(void) +{ + return 7; +} + + +/* + * factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + * + * FIXME: figure out how to compute or tabulate good values for this + */ + +unsigned int +fsl_ddr_sdram_cpo_override_function(void) +{ + return 10; +} + + +/* + * factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + +unsigned int +fsl_ddr_sdram_write_data_delay_function(void) +{ + return 5; +} + + +/* + * factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + +unsigned int +fsl_ddr_sdram_half_strength_driver_enable_function(void) +{ + return 0; +} diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c new file mode 100644 index 0000000..d69b593 --- /dev/null +++ b/board/freescale/mpc8572ds/law.c @@ -0,0 +1,41 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), + SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c new file mode 100644 index 0000000..8cc3a02 --- /dev/null +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -0,0 +1,573 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include "../common/pixis.h" +#include "../cpu/mpc8xxx/fsl_ddr_sdram.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +long int fixed_sdram(void); + +int checkboard (void) +{ + printf ("Board: MPC8572DS, System ID: 0x%02x, " + "System Version: 0x%02x, FPGA Version: 0x%02x\n", + in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), + in8(PIXIS_BASE + PIXIS_PVER)); + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + +#ifdef CONFIG_SPD_EEPROM + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + puts(" DDR: "); + return dram_size; +} + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + uint d_init; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; + +#if defined (CONFIG_DDR_ECC) + ddr->err_int_en = CFG_DDR_ERR_INT_EN; + ddr->err_disable = CFG_DDR_ERR_DIS; + ddr->err_sbe = CFG_DDR_SBE; +#endif + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CFG_DDR_CONTROL; + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR - 1st controller: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n\n"); + asm("sync; isync"); + udelay(500); +#endif + + return 512 * 1024 * 1024; +} + +#endif + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +int first_free_busno=0; +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + printf (" eTSEC1 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + printf (" eTSEC2 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf (" eTSEC3 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + printf (" eTSEC4 is in sgmii mode.\n"); + + +#ifdef CONFIG_PCIE3 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie3_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 3) || + (host_agent == 5) || (host_agent == 6); + int pcie_configured = io_sel >= 1; + u32 temp32; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE3 connected to ULI as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE3_MEM_BASE, + CFG_PCIE3_MEM_PHYS, + CFG_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE3_IO_BASE, + CFG_PCIE3_IO_PHYS, + CFG_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCIE3 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + * Device 1d has the first on-board memory BAR. + */ + + pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), + PCI_BASE_ADDRESS_1, &temp32); + if (temp32 >= CFG_PCIE3_MEM_PHYS) { + debug(" uli1572 read to %x\n", temp32); + in_be32((unsigned *)temp32); + } + } else { + printf (" PCIE3: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie2_hose; + int pcie_ep = (host_agent == 2) || (host_agent == 4) || + (host_agent == 6); + int pcie_configured = io_sel & 4; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE2_MEM_BASE, + CFG_PCIE2_MEM_PHYS, + CFG_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE2_IO_BASE, + CFG_PCIE2_IO_PHYS, + CFG_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf (" PCIE2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE2: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif +#ifdef CONFIG_PCIE1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 1) || (host_agent == 4) || + (host_agent == 5); + int pcie_configured = io_sel & 6; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + hose->first_busno=first_free_busno; + + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE1: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif +} +#endif + +int last_stage_init(void) +{ + unsigned int i; + const unsigned int flashbase = CFG_FLASH_BASE; + const u8 flash_esel = 2; + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Invalidate any remaining lines of the flash from caches. */ + for (i = 0; i < 256*1024*1024; i+=32) { + asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); + asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); + } + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ + + return 0; +} + +#ifdef CONFIG_GET_CLK_FROM_ICS307 +/* decode S[0-2] to Output Divider (OD) */ +static unsigned char ics307_S_to_OD[] = { + 10, 2, 8, 4, 5, 7, 3, 6 +}; + +/* Calculate frequency being generated by ICS307-02 clock chip based upon + * the control bytes being programmed into it. */ +/* XXX: This function should probably go into a common library */ +static unsigned long +ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) +{ + const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; + unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); + unsigned long RDW = cw2 & 0x7F; + unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; + unsigned long freq; + + /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ + + /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 + * cw1: V8 V7 V6 V5 V4 V3 V2 V1 + * cw2: V0 R6 R5 R4 R3 R2 R1 R0 + * + * R6:R0 = Reference Divider Word (RDW) + * V8:V0 = VCO Divider Word (VDW) + * S2:S0 = Output Divider Select (OD) + * F1:F0 = Function of CLK2 Output + * TTL = duty cycle + * C1:C0 = internal load capacitance for cyrstal + */ + + /* Adding 1 to get a "nicely" rounded number, but this needs + * more tweaking to get a "properly" rounded number. */ + + freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); + + debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, + freq); + return freq; +} + +unsigned long get_board_sys_clk(ulong dummy) +{ + return ics307_clk_freq ( + in8(PIXIS_BASE + PIXIS_VSYSCLK0), + in8(PIXIS_BASE + PIXIS_VSYSCLK1), + in8(PIXIS_BASE + PIXIS_VSYSCLK2) + ); +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + return ics307_clk_freq ( + in8(PIXIS_BASE + PIXIS_VDDRCLK0), + in8(PIXIS_BASE + PIXIS_VDDRCLK1), + in8(PIXIS_BASE + PIXIS_VDDRCLK2) + ); +} +#else +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x07; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + + return val; +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x38; + i >>= 3; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + return val; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + ulong base, size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCIE3 + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE2 + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE1 + path = fdt_getprop(blob, node, "pci2", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c new file mode 100644 index 0000000..965356a --- /dev/null +++ b/board/freescale/mpc8572ds/tlb.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS, CFG_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x40000000, CFG_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x50000000, CFG_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8572ds/u-boot.lds b/board/freescale/mpc8572ds/u-boot.lds new file mode 100644 index 0000000..a05ece5 --- /dev/null +++ b/board/freescale/mpc8572ds/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bde8e56..5c2231d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -154,7 +154,7 @@ int checkcpu (void) #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) +#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || defined(CONFIG_MPC8572) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index a5060cd..fdc4c83 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,7 +29,7 @@ #include <asm/cpm_85xx.h> #include <pci.h> -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT) static struct pci_controller *pci_hose; diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h new file mode 100644 index 0000000..1823d77 --- /dev/null +++ b/include/configs/MPC8572DS.h @@ -0,0 +1,600 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8572ds board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8572 1 +#define CONFIG_MPC8572DS 1 +#define CONFIG_MP 1 /* support multiple processors */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ + +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +extern unsigned long get_board_ddr_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_ICS307_REFCLK_HZ 33333333 /* ICS307 clock chip ref freq */ +#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq + from ICS307 instead of switches */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x7fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + + +/* + * DDR Setup + */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#undef CONFIG_DDR_DLL + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CFG_DDR_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + + +/* + * Number of memory controllers on device + */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 + +/* + * Number of DIMM slots per memory controller + */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* + * Number of chip selects per memory controller + * + * The MPC8572 (the chip) has 4 chip selects per memory controller. + * However, the MPC8572DS (the board) has only 1 DIMM slot per memory + * controller, so therefore it only has 2 chip selects per memory + * controller that are actually connected. + */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* + * I2C addresses of SPD EEPROMs + */ +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ + + +/* + * These are used when DDR doesn't use SPD. + */ +#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ +#define CFG_DDR_CS0_BNDS 0x0000001F +#define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x3935d322 +#define CFG_DDR_TIMING_2 0x14904cc8 +#define CFG_DDR_MODE_1 0x00480432 +#define CFG_DDR_MODE_2 0x00000000 +#define CFG_DDR_INTERVAL 0x06180100 +#define CFG_DDR_DATA_INIT 0xdeadbeef +#define CFG_DDR_CLK_CTRL 0x03800000 +#define CFG_DDR_OCD_CTRL 0x00000000 +#define CFG_DDR_OCD_STATUS 0x00000000 +#define CFG_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ +#define CFG_DDR_CONTROL2 0x04400010 + +#define CFG_DDR_ERR_INT_EN 0x0000000d +#define CFG_DDR_ERR_DIS 0x00000000 +#define CFG_DDR_SBE 0x00010000 + +/* + * FIXME: Not used in fixed_sdram function + */ +#define CFG_DDR_MODE 0x00000022 +#define CFG_DDR_CS1_BNDS 0x00000000 +#define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ +#define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ +#define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ +#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CFG_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ + +#define CFG_BR0_PRELIM 0xe8001001 +#define CFG_OR0_PRELIM 0xf8000ff7 + +#define CFG_BR1_PRELIM 0xe0001001 +#define CFG_OR1_PRELIM 0xf8000ff7 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE} +#define CFG_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_AMD_CHECK_DQ7 + +#define CONFIG_LAST_STAGE_INIT /* call last_stage_init() function */ + +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ + +#define CFG_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CFG_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_PWR 0x5 /* PIXIS Power status register */ +#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VSTAT 0x11 /* VELA Status Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ +#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ +#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ +#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ +#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ +#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ +#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ +#define PIXIS_VWATCH 0x24 /* Watchdog Register */ +#define PIXIS_LED 0x25 /* LED Register */ + +/* old pixis referenced names */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0xc0 + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CFG_PCIE3_MEM_BASE 0x80000000 +#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE +#define CFG_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE3_IO_BASE 0x00000000 +#define CFG_PCIE3_IO_PHYS 0xffc00000 +#define CFG_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CFG_PCIE2_MEM_BASE 0xa0000000 +#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE +#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE2_IO_BASE 0x00000000 +#define CFG_PCIE2_IO_PHYS 0xffc10000 +#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CFG_PCIE1_MEM_BASE 0xc0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xffc20000 +#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#if defined(CONFIG_PCI) + +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CFG_PCIE1_IO_PHYS + +/* video */ +#define CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_CONSOLE_CURSOR*/ +#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#undef CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + +#ifndef CONFIG_PCI_PNP + #define PCI_ENET0_IOADDR CFG_PCIE3_IO_BASE + #define PCI_ENET0_MEMADDR CFG_PCIE3_IO_BASE + #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif /* SCSI */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#if CFG_MONITOR_BASE > 0xfff80000 +#define CFG_ENV_ADDR 0xfff80000 +#else +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) +#endif +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_NET +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_EXT2 +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:02:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD +#endif + +#define CONFIG_IPADDR 192.168.1.254 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=8572ds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=8572ds/mpc8572ds.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ -- 1.5.5.1

2 5

[U-Boot] [PATCH] Change CFG_ENV_SIZE to CFG_ENV_SECT_SIZE for SPI sector erase
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> The CFG_ENV_SIZE is not suitable used for SPI flash erase sector size if CFG_ENV_SIZE is less than CFG_ENV_SECT_SIZE. Add condition check if CFG_ENV_SIZE is larger than CFG_ENV_SECT_SIZE, calculate the right number of sectors for erasing. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- common/env_sf.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/common/env_sf.c b/common/env_sf.c index d641a9a..9077d78 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -63,13 +63,21 @@ uchar env_get_char_spec(int index) int saveenv(void) { + u32 sector = 1; + if (!env_flash) { puts("Environment SPI flash not initialized\n"); return 1; } + if (CFG_ENV_SIZE > CFG_ENV_SECT_SIZE) { + sector = CFG_ENV_SIZE / CFG_ENV_SECT_SIZE; + if (CFG_ENV_SIZE % CFG_ENV_SECT_SIZE) + sector++; + } + puts("Erasing SPI flash..."); - if (spi_flash_erase(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE)) + if (spi_flash_erase(env_flash, CFG_ENV_OFFSET, sector * CFG_ENV_SECT_SIZE)) return 1; puts("Writing to SPI flash..."); -- 1.5.6.4

1 0

[U-Boot] [Fwd: Re: mvbc_p board: build warnings]
by André Schwarz 12 Aug '08

12 Aug '08

sorry - wrong list address. -------- Original Message -------- Subject: Re: mvbc_p board: build warnings Date: Tue, 12 Aug 2008 17:38:28 +0200 From: André Schwarz <Andre.Schwarz(a)matrix-vision.de> To: Wolfgang Denk <wd(a)denx.de> CC: u-boot-users(a)lists.sourceforge.net References: <20080731132612.9CA54248B9(a)gemini.denx.de> <4891F7AF.4030902(a)matrix-vision.de> <20080812120655.280B3248EA(a)gemini.denx.de> Wolfgang, sorry for this - it's been quite a mess before my holiday. I'll be back in office next week and won't be able to fix it before mid of next week. I have absolutely no problem if you do not wait for the patch. Maybe there will be other changes also ... regards, André Wolfgang Denk wrote: > Dear André, > > in message <4891F7AF.4030902(a)matrix-vision.de> you wrote: > >> thanks - I'll fix it on monday/tuesday and send a patch after testing >> the -rc2. >> > > Maybe I have missed your patch? > > This problem is still open! > > I have to decide if you fix this now, i. e. wait with the 1.3.4 > release, or later. > > Best regards, > > Wolfgang Denk > > MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

1 0

[U-Boot] Xilinx FX12MM Board - xparameters.h
by Georg Schardt 12 Aug '08

12 Aug '08

Hi again, after working for another project the last months i'm back to my virtex4 minimodul. now i have a working u-boot configuration, but some things are still dirty :) for example i copy the xparameters.h to the new board/xilinx/fx12mm directory, but also in board/xilinx/common and board/xilinx/xilinx_enet. this is not correct, or ? i think there is something wrong in the configuration, so the compiler did not found the file in board/xilinx/fx12mm ? after cleanup the files i will try to generate some patches with the new board infos greetings georg

2 1

[U-Boot] boots (subcommands)
by Kumar Gala 12 Aug '08

12 Aug '08

So after refactoring the bootm code I get to the following "sub command set": * interrupt on/off (to enable/disable interrupts) * icache/dcache (already exists) * usb stop (already exists) * boots (boot sub command): start <ARGS> - takes same args as bootm, parses the args and sets up bootm_headers_t load_os - decompresses and loads OS image relocate_initrd - relocates initrd based on constraints relocate_fdt - relocates fdt based on constraints jump (load_os, relocate_initrd, relocate_fdt, jump will fail if start has been called, beyond that they can be called in any order and its left to the user to do the right thing). * fdt: chosen -- expand to allow setting initrd info boardsetup -- exists resize - new We might need one or two other commands to prep things for the OS and some bd related foo. - k

1 0

[U-Boot] [PATCH] ppc4xx: Optimize PLB4 arbiter and Memory Queue settings for PPC 440SP/SPe and 460EX/GT/SX
by prodyut hazarika 12 Aug '08

12 Aug '08

Read Pipeline depth should be set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors. Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors Please apply patch against next branch of Stefan's git tree. Signed-off-by: Prodyut Hazarika <phazarika(a)amcc.com> --- cpu/ppc4xx/44x_spd_ddr2.c | 28 +++++++++++++++++--- cpu/ppc4xx/cpu_init.c | 21 ++++++++++++++- include/asm-ppc/ppc4xx-sdram.h | 48 +++++++++++++++++++++++----------- include/ppc440.h | 47 ---------------------------------- include/ppc4xx.h | 55 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 131 insertions(+), 68 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 1c36324..2ba7715 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2172,6 +2172,11 @@ static void program_memory_queue(unsigned long *dimm_populated, unsigned long i; unsigned long bank_0_populated = 0; phys_size_t total_size = 0; +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + unsigned long val; +#endif /*------------------------------------------------------------------ * Reset the rank_base_address. @@ -2249,18 +2254,33 @@ static void program_memory_queue(unsigned long *dimm_populated, } } -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + /* - * Enable high bandwidth access on 460EX/GT. - * This should/could probably be done on other - * PPC's too, like 440SPe. + * Enable high bandwidth access * This is currently not used, but with this setup * it is possible to use it later on in e.g. the Linux * EMAC driver for performance gain. */ mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */ mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */ + + /* + * Set optimal value for Memory Queue HB/LL Configuration registers + */ + + val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE); + mtdcr(SDRAM_CONF1HB, val); + + val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONF1LL, val); + + val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); + mtdcr(SDRAM_CONFPATHB, val); #endif + } /*-----------------------------------------------------------------------------+ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index e2d0402..033d4f5 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -138,7 +138,9 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ + defined (CONFIG_460GT) || defined(CONFIG_460SX) u32 val; #endif @@ -301,6 +303,23 @@ cpu_init_f (void) val |= 0x400; mtsdr(SDR0_USB2HOST_CFG, val); #endif /* CONFIG_460EX */ + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) || defined(CONFIG_460SX) + + /* + * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read + */ + + val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + mtdcr(plb0_acr, val); + + val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + mtdcr(plb1_acr, val); + +#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ + } /* diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index df787b3..d2e3b42 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -259,23 +259,39 @@ /* * Memory queue defines */ -#define SDRAMQ_DCR_BASE 0x040 - -#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ -#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ -#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ -#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ -#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ -#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ -#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ -#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ -#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ -#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ -#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ -#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ -#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ -#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ +#define SDRAMQ_DCR_BASE 0x040 + +#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ +#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ +#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ +#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ +#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ +#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ +#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ +#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ +#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ +#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ + +#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ +#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ +#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ +#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ +#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ +#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ +#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ +#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ +#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ +#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ + +#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ +#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ +#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ +#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ +#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */ + +#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ #if !defined(CONFIG_405EX) /* diff --git a/include/ppc440.h b/include/ppc440.h index 92db15f..3584fd2 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -341,53 +341,6 @@ #define PLB4_ACR_WRP (0x80000000 >> 7) -/* Nebula PLB4 Arbiter - PowerPC440EP */ -#define PLB_ARBITER_BASE 0x80 - -#define plb0_revid (PLB_ARBITER_BASE+ 0x00) -#define plb0_acr (PLB_ARBITER_BASE+ 0x01) -#define plb0_acr_ppm_mask 0xF0000000 -#define plb0_acr_ppm_fixed 0x00000000 -#define plb0_acr_ppm_fair 0xD0000000 -#define plb0_acr_hbu_mask 0x08000000 -#define plb0_acr_hbu_disabled 0x00000000 -#define plb0_acr_hbu_enabled 0x08000000 -#define plb0_acr_rdp_mask 0x06000000 -#define plb0_acr_rdp_disabled 0x00000000 -#define plb0_acr_rdp_2deep 0x02000000 -#define plb0_acr_rdp_3deep 0x04000000 -#define plb0_acr_rdp_4deep 0x06000000 -#define plb0_acr_wrp_mask 0x01000000 -#define plb0_acr_wrp_disabled 0x00000000 -#define plb0_acr_wrp_2deep 0x01000000 - -#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) -#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) -#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) -#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) -#define plb0_ccr (PLB_ARBITER_BASE+ 0x08) - -#define plb1_acr (PLB_ARBITER_BASE+ 0x09) -#define plb1_acr_ppm_mask 0xF0000000 -#define plb1_acr_ppm_fixed 0x00000000 -#define plb1_acr_ppm_fair 0xD0000000 -#define plb1_acr_hbu_mask 0x08000000 -#define plb1_acr_hbu_disabled 0x00000000 -#define plb1_acr_hbu_enabled 0x08000000 -#define plb1_acr_rdp_mask 0x06000000 -#define plb1_acr_rdp_disabled 0x00000000 -#define plb1_acr_rdp_2deep 0x02000000 -#define plb1_acr_rdp_3deep 0x04000000 -#define plb1_acr_rdp_4deep 0x06000000 -#define plb1_acr_wrp_mask 0x01000000 -#define plb1_acr_wrp_disabled 0x00000000 -#define plb1_acr_wrp_2deep 0x01000000 - -#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) -#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) -#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) -#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) - /* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index c71da60..154956e 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -46,6 +46,61 @@ #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif +/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) || defined(CONFIG_405EX) + +#define PLB_ARBITER_BASE 0x80 + +#define plb0_revid (PLB_ARBITER_BASE+ 0x00) +#define plb0_acr (PLB_ARBITER_BASE+ 0x01) +#define plb0_acr_ppm_mask 0xF0000000 +#define plb0_acr_ppm_fixed 0x00000000 +#define plb0_acr_ppm_fair 0xD0000000 +#define plb0_acr_hbu_mask 0x08000000 +#define plb0_acr_hbu_disabled 0x00000000 +#define plb0_acr_hbu_enabled 0x08000000 +#define plb0_acr_rdp_mask 0x06000000 +#define plb0_acr_rdp_disabled 0x00000000 +#define plb0_acr_rdp_2deep 0x02000000 +#define plb0_acr_rdp_3deep 0x04000000 +#define plb0_acr_rdp_4deep 0x06000000 +#define plb0_acr_wrp_mask 0x01000000 +#define plb0_acr_wrp_disabled 0x00000000 +#define plb0_acr_wrp_2deep 0x01000000 + +#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) +#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) +#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) +#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) +#define plb0_ccr (PLB_ARBITER_BASE+ 0x08) + +#define plb1_acr (PLB_ARBITER_BASE+ 0x09) +#define plb1_acr_ppm_mask 0xF0000000 +#define plb1_acr_ppm_fixed 0x00000000 +#define plb1_acr_ppm_fair 0xD0000000 +#define plb1_acr_hbu_mask 0x08000000 +#define plb1_acr_hbu_disabled 0x00000000 +#define plb1_acr_hbu_enabled 0x08000000 +#define plb1_acr_rdp_mask 0x06000000 +#define plb1_acr_rdp_disabled 0x00000000 +#define plb1_acr_rdp_2deep 0x02000000 +#define plb1_acr_rdp_3deep 0x04000000 +#define plb1_acr_rdp_4deep 0x06000000 +#define plb1_acr_wrp_mask 0x01000000 +#define plb1_acr_wrp_disabled 0x00000000 +#define plb1_acr_wrp_2deep 0x01000000 + +#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) +#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) +#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) +#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) + +#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ + #if defined(CONFIG_440) /* * Enable long long (%ll ...) printf format on 440 PPC's since most of -- 1.5.5

3 3