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August 2008

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[U-Boot] [PATCH] ColdFire: Multiple fixes for M5282EVB
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Incorrect CFG_HZ value, change 1000000 to 1000. Rename #waring to #warning. RAMBAR1 uses twice in start.S, rename the later to FLASHBAR. Insert nop for DRAM setup. And, env_offset in linker file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- board/freescale/m5282evb/m5282evb.c | 7 +++++++ board/freescale/m5282evb/u-boot.lds | 3 +-- cpu/mcf52x2/cpu_init.c | 2 +- cpu/mcf52x2/start.S | 2 +- include/configs/M5282EVB.h | 4 ++-- 5 files changed, 12 insertions(+), 6 deletions(-) diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index 50e5e77..31d6923 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -51,6 +51,7 @@ phys_size_t initdram (int board_type) MCFSDRAMC_DCR = (0 | MCFSDRAMC_DCR_RTIM_6 | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); + asm("nop"); /* Initialize DACR0 */ MCFSDRAMC_DACR0 = (0 @@ -58,14 +59,17 @@ phys_size_t initdram (int board_type) | MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32); + asm("nop"); /* Initialize DMR0 */ MCFSDRAMC_DMR0 = (0 | ((dramsize - 1) & 0xFFFC0000) | MCFSDRAMC_DMR_V); + asm("nop"); /* Set IP (bit 3) in DACR */ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + asm("nop"); /* Wait 30ns to allow banks to precharge */ for (i = 0; i < 5; i++) { @@ -74,9 +78,11 @@ phys_size_t initdram (int board_type) /* Write to this block to initiate precharge */ *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; + asm("nop"); /* Set RE (bit 15) in DACR */ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + asm("nop"); /* Wait for at least 8 auto refresh cycles to occur */ for (i = 0; i < 2000; i++) { @@ -85,6 +91,7 @@ phys_size_t initdram (int board_type) /* Finish the configuration by issuing the IMRS. */ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + asm("nop"); /* Write to the SDRAM Mode Register */ *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index dd2666b..96fde65 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -60,9 +60,8 @@ SECTIONS lib_generic/string.o (.text) lib_generic/vsprintf.o (.text) lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) -/* . = env_offset; */ + . = env_offset; common/environment.o(.text) *(.text) diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 344bcee..3cacb55 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -442,7 +442,7 @@ void cpu_init_f(void) MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V; #endif #else -#waring "Chip Select 0 are not initialized/used" +#warning "Chip Select 0 are not initialized/used" #endif #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index a054904..2e8ecfb 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -166,7 +166,7 @@ _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 - movec %d0, %RAMBAR1 + movec %d0, %FLASHBAR #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ #endif diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index df46ee4..d05bc70 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -104,7 +104,7 @@ # define CONFIG_OVERWRITE_ETHADDR_ONCE #endif /* CONFIG_MCFFEC */ -#define CONFIG_HOSTNAME M5272C3 +#define CONFIG_HOSTNAME M5282EVB #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ @@ -134,7 +134,7 @@ #define CFG_MEMTEST_START 0x400 #define CFG_MEMTEST_END 0x380000 -#define CFG_HZ 1000000 +#define CFG_HZ 1000 #define CFG_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ -- 1.5.6.4

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[U-Boot] [PATCH] ColdFire: Move m5282evb from board to board/freescale
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- Makefile | 2 +- board/freescale/m5282evb/Makefile | 44 +++++ board/freescale/m5282evb/config.mk | 25 +++ board/freescale/m5282evb/m5282evb.c | 93 +++++++++++ board/freescale/m5282evb/mii.c | 304 +++++++++++++++++++++++++++++++++++ board/freescale/m5282evb/u-boot.lds | 142 ++++++++++++++++ board/m5282evb/Makefile | 44 ----- board/m5282evb/config.mk | 25 --- board/m5282evb/m5282evb.c | 93 ----------- board/m5282evb/mii.c | 304 ----------------------------------- board/m5282evb/u-boot.lds | 142 ---------------- 11 files changed, 609 insertions(+), 609 deletions(-) create mode 100644 board/freescale/m5282evb/Makefile create mode 100644 board/freescale/m5282evb/config.mk create mode 100644 board/freescale/m5282evb/m5282evb.c create mode 100644 board/freescale/m5282evb/mii.c create mode 100644 board/freescale/m5282evb/u-boot.lds delete mode 100644 board/m5282evb/Makefile delete mode 100644 board/m5282evb/config.mk delete mode 100644 board/m5282evb/m5282evb.c delete mode 100644 board/m5282evb/mii.c delete mode 100644 board/m5282evb/u-boot.lds diff --git a/Makefile b/Makefile index 865edf5..a4e6e0d 100644 --- a/Makefile +++ b/Makefile @@ -1870,7 +1870,7 @@ M5275EVB_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale M5282EVB_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale M5329AFEE_config \ M5329BFEE_config : unconfig diff --git a/board/freescale/m5282evb/Makefile b/board/freescale/m5282evb/Makefile new file mode 100644 index 0000000..2ec71ee --- /dev/null +++ b/board/freescale/m5282evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5282evb/config.mk b/board/freescale/m5282evb/config.mk new file mode 100644 index 0000000..0aa2361 --- /dev/null +++ b/board/freescale/m5282evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFE00000 diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c new file mode 100644 index 0000000..50e5e77 --- /dev/null +++ b/board/freescale/m5282evb/m5282evb.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard (void) +{ + puts ("Board: Freescale M5282EVB Evaluation Board\n"); + return 0; +} + +phys_size_t initdram (int board_type) +{ + u32 dramsize, i, dramclk; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) + { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + MCFSDRAMC_DCR = (0 + | MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); + + /* Initialize DACR0 */ + MCFSDRAMC_DACR0 = (0 + | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_32); + + /* Initialize DMR0 */ + MCFSDRAMC_DMR0 = (0 + | ((dramsize - 1) & 0xFFFC0000) + | MCFSDRAMC_DMR_V); + + /* Set IP (bit 3) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm ("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) { + asm(" nop"); + } + + /* Finish the configuration by issuing the IMRS. */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } + return dramsize; +} diff --git a/board/freescale/m5282evb/mii.c b/board/freescale/m5282evb/mii.c new file mode 100644 index 0000000..8ae2ec6 --- /dev/null +++ b/board/freescale/m5282evb/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CFG_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds new file mode 100644 index 0000000..dd2666b --- /dev/null +++ b/board/freescale/m5282evb/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset; */ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile deleted file mode 100644 index 2ec71ee..0000000 --- a/board/m5282evb/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o mii.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk deleted file mode 100644 index 0aa2361..0000000 --- a/board/m5282evb/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xFFE00000 diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c deleted file mode 100644 index 50e5e77..0000000 --- a/board/m5282evb/m5282evb.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/immap.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - puts ("Board: Freescale M5282EVB Evaluation Board\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - u32 dramsize, i, dramclk; - - dramsize = CFG_SDRAM_SIZE * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) - { - dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); - - /* Initialize DRAM Control Register: DCR */ - MCFSDRAMC_DCR = (0 - | MCFSDRAMC_DCR_RTIM_6 - | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); - - /* Initialize DACR0 */ - MCFSDRAMC_DACR0 = (0 - | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) - | MCFSDRAMC_DACR_CASL(1) - | MCFSDRAMC_DACR_CBM(3) - | MCFSDRAMC_DACR_PS_32); - - /* Initialize DMR0 */ - MCFSDRAMC_DMR0 = (0 - | ((dramsize - 1) & 0xFFFC0000) - | MCFSDRAMC_DMR_V); - - /* Set IP (bit 3) in DACR */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; - - /* Wait 30ns to allow banks to precharge */ - for (i = 0; i < 5; i++) { - asm ("nop"); - } - - /* Write to this block to initiate precharge */ - *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; - - /* Set RE (bit 15) in DACR */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) { - asm(" nop"); - } - - /* Finish the configuration by issuing the IMRS. */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; - - /* Write to the SDRAM Mode Register */ - *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; - } - return dramsize; -} diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c deleted file mode 100644 index 8ae2ec6..0000000 --- a/board/m5282evb/mii.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CFG_PEHLPAR; - } else { - MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_AMD79C874VC "AMD79C874VC" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - strcpy(info->phy_name, - STR_ID_AMD79C874VC); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - printf(STR_ID_AMD79C874VC); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5282evb/u-boot.lds b/board/m5282evb/u-boot.lds deleted file mode 100644 index dd2666b..0000000 --- a/board/m5282evb/u-boot.lds +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mcf52x2/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/string.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset; */ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Move m5272c3 from board to board/freescale
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- Makefile | 2 +- board/freescale/m5272c3/Makefile | 44 ++++ board/freescale/m5272c3/config.mk | 25 +++ board/freescale/m5272c3/flash.c | 378 ++++++++++++++++++++++++++++++++++++ board/freescale/m5272c3/m5272c3.c | 51 +++++ board/freescale/m5272c3/mii.c | 303 +++++++++++++++++++++++++++++ board/freescale/m5272c3/u-boot.lds | 143 ++++++++++++++ board/m5272c3/Makefile | 44 ---- board/m5272c3/config.mk | 25 --- board/m5272c3/flash.c | 378 ------------------------------------ board/m5272c3/m5272c3.c | 51 ----- board/m5272c3/mii.c | 303 ----------------------------- board/m5272c3/u-boot.lds | 143 -------------- 13 files changed, 945 insertions(+), 945 deletions(-) create mode 100644 board/freescale/m5272c3/Makefile create mode 100644 board/freescale/m5272c3/config.mk create mode 100644 board/freescale/m5272c3/flash.c create mode 100644 board/freescale/m5272c3/m5272c3.c create mode 100644 board/freescale/m5272c3/mii.c create mode 100644 board/freescale/m5272c3/u-boot.lds delete mode 100644 board/m5272c3/Makefile delete mode 100644 board/m5272c3/config.mk delete mode 100644 board/m5272c3/flash.c delete mode 100644 board/m5272c3/m5272c3.c delete mode 100644 board/m5272c3/mii.c delete mode 100644 board/m5272c3/u-boot.lds diff --git a/Makefile b/Makefile index 171fdd9..865edf5 100644 --- a/Makefile +++ b/Makefile @@ -1864,7 +1864,7 @@ M5271EVB_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb freescale M5272C3_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3 + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3 freescale M5275EVB_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale diff --git a/board/freescale/m5272c3/Makefile b/board/freescale/m5272c3/Makefile new file mode 100644 index 0000000..be704b7 --- /dev/null +++ b/board/freescale/m5272c3/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5272c3/config.mk b/board/freescale/m5272c3/config.mk new file mode 100644 index 0000000..ccb2cf7 --- /dev/null +++ b/board/freescale/m5272c3/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5272c3/flash.c b/board/freescale/m5272c3/flash.c new file mode 100644 index 0000000..ea0b1fd --- /dev/null +++ b/board/freescale/m5272c3/flash.c @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_PL160CB & FLASH_TYPEMASK): + printf ("AM29PL160CB (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done: + return; +} + + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_PL160CB & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured to many flash banks!\n"); + + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j == 0) { + /* 1st is 16 KiB */ + flash_info[i].start[j] = flashbase; + } + if ((j >= 1) && (j <= 2)) { + /* 2nd and 3rd are 8 KiB */ + flash_info[i].start[j] = + flashbase + 0x4000 + 0x2000 * (j - 1); + } + if (j == 3) { + /* 4th is 224 KiB */ + flash_info[i].start[j] = flashbase + 0x8000; + } + if ((j >= 4) && (j <= 10)) { + /* rest is 256 KiB */ + flash_info[i].start[j] = + flashbase + 0x40000 + 0x40000 * (j - + 4); + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); + + return size; +} + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + printf ("\n"); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = + (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + } + +#if 0 + if (cnt & 1) { + printf ("odd transfer sizes not supported\n"); + return ERR_ALIGN; + } +#endif + + wp = addr; + + if (addr & 1) { + data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) + src); + if ((rc = write_word (info, wp - 1, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src) << 8) | + *((volatile u8 *) (wp + 1)); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + return ERR_OK; +} diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c new file mode 100644 index 0000000..d17cb2e --- /dev/null +++ b/board/freescale/m5272c3/m5272c3.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/immap.h> + + +int checkboard (void) { + puts ("Board: "); + puts ("Freescale MCF5272C3 EVB\n"); + return 0; + }; + +phys_size_t initdram (int board_type) { + volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); + + sdp->sdram_sdtr = 0xf539; + sdp->sdram_sdcr = 0x4211; + + /* Dummy write to start SDRAM */ + *((volatile unsigned long *)0) = 0; + + return CFG_SDRAM_SIZE * 1024 * 1024; + }; + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5272c3/mii.c b/board/freescale/m5272c3/mii.c new file mode 100644 index 0000000..b30ba80 --- /dev/null +++ b/board/freescale/m5272c3/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds new file mode 100644 index 0000000..8420c91 --- /dev/null +++ b/board/freescale/m5272c3/u-boot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile deleted file mode 100644 index be704b7..0000000 --- a/board/m5272c3/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o flash.o mii.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/m5272c3/config.mk b/board/m5272c3/config.mk deleted file mode 100644 index ccb2cf7..0000000 --- a/board/m5272c3/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xffe00000 diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c deleted file mode 100644 index ea0b1fd..0000000 --- a/board/m5272c3/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 224 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 10)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x40000 + 0x40000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c deleted file mode 100644 index d17cb2e..0000000 --- a/board/m5272c3/m5272c3.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/immap.h> - - -int checkboard (void) { - puts ("Board: "); - puts ("Freescale MCF5272C3 EVB\n"); - return 0; - }; - -phys_size_t initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); - - sdp->sdram_sdtr = 0xf539; - sdp->sdram_sdcr = 0x4211; - - /* Dummy write to start SDRAM */ - *((volatile unsigned long *)0) = 0; - - return CFG_SDRAM_SIZE * 1024 * 1024; - }; - -int testdram (void) { - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c deleted file mode 100644 index b30ba80..0000000 --- a/board/m5272c3/mii.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; - } else { - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_AMD79C874VC "AMD79C874VC" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - strcpy(info->phy_name, - STR_ID_AMD79C874VC); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - printf(STR_ID_AMD79C874VC); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5272c3/u-boot.lds b/board/m5272c3/u-boot.lds deleted file mode 100644 index 8420c91..0000000 --- a/board/m5272c3/u-boot.lds +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) - common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Move m5271evb from board to board/freescale
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- Makefile | 2 +- board/freescale/m5271evb/Makefile | 44 +++++ board/freescale/m5271evb/config.mk | 25 +++ board/freescale/m5271evb/m5271evb.c | 123 ++++++++++++++ board/freescale/m5271evb/mii.c | 303 +++++++++++++++++++++++++++++++++++ board/freescale/m5271evb/u-boot.lds | 144 +++++++++++++++++ board/m5271evb/Makefile | 44 ----- board/m5271evb/config.mk | 25 --- board/m5271evb/m5271evb.c | 123 -------------- board/m5271evb/mii.c | 303 ----------------------------------- board/m5271evb/u-boot.lds | 144 ----------------- 11 files changed, 640 insertions(+), 640 deletions(-) create mode 100644 board/freescale/m5271evb/Makefile create mode 100644 board/freescale/m5271evb/config.mk create mode 100644 board/freescale/m5271evb/m5271evb.c create mode 100644 board/freescale/m5271evb/mii.c create mode 100644 board/freescale/m5271evb/u-boot.lds delete mode 100644 board/m5271evb/Makefile delete mode 100644 board/m5271evb/config.mk delete mode 100644 board/m5271evb/m5271evb.c delete mode 100644 board/m5271evb/mii.c delete mode 100644 board/m5271evb/u-boot.lds diff --git a/Makefile b/Makefile index 3b99d7a..171fdd9 100644 --- a/Makefile +++ b/Makefile @@ -1861,7 +1861,7 @@ idmr_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr M5271EVB_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb freescale M5272C3_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3 diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile new file mode 100644 index 0000000..2ec71ee --- /dev/null +++ b/board/freescale/m5271evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5271evb/config.mk b/board/freescale/m5271evb/config.mk new file mode 100644 index 0000000..9a7af7c --- /dev/null +++ b/board/freescale/m5271evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c new file mode 100644 index 0000000..e089d5f --- /dev/null +++ b/board/freescale/m5271evb/m5271evb.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/immap.h> + +int checkboard (void) { + puts ("Board: Freescale M5271EVB\n"); + return 0; +}; + +phys_size_t initdram (int board_type) { + + int i; + + /* Enable Address lines 23-21 and lower 16bits of data path */ + mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | + MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | + MCF_GPIO_AD_DATAL); + + /* Set CS2 pin to be SD_CS0 */ + mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) + | MCF_GPIO_PAR_CS_PAR_CS2); + + /* Configure SDRAM Control Pin Assignemnt Register */ + mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | + MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | + MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | + MCF_GPIO_SDRAM_SDCS_11); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCF_SDRAMC_DCR, + MCF_SDRAMC_DCR_RTIM(0x01) + | MCF_SDRAMC_DCR_RC(0x30)); + + /* + * Initialize DACR0 + * + * CASL: 01 + * CBM: cmd at A20, bank select bits 21 and up + * PS: 32bit port size + */ + mbar_writeLong(MCF_SDRAMC_DACR0, + MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) + | MCF_SDRAMC_DACRn_CASL(1) + | MCF_SDRAMC_DACRn_CBM(3) + | MCF_SDRAMC_DACRn_PS(0)); + + /* Initialize DMR0 */ + mbar_writeLong(MCF_SDRAMC_DMR0, + MCF_SDRAMC_DMRn_BAM_16M + | MCF_SDRAMC_DMRn_V); + + /* Set IP bit in DACR */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_IP); + + /* Wait at least 20ns to allow banks to precharge */ + for (i = 0; i < 5; i++) + asm(" nop"); + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5; + + /* Set RE bit in DACR */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_RE); + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) + asm(" nop"); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_MRS); + + /* + * Write to the SDRAM Mode Register A0-A11 = 0x400 + * + * Write Burst Mode = Programmed Burst Length + * Op Mode = Standard Op + * CAS Latency = 2 + * Burst Type = Sequential + * Burst Length = 1 + */ + *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5; + } + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + +int testdram (void) { + + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5271evb/mii.c b/board/freescale/m5271evb/mii.c new file mode 100644 index 0000000..78a7028 --- /dev/null +++ b/board/freescale/m5271evb/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds new file mode 100644 index 0000000..c07d023 --- /dev/null +++ b/board/freescale/m5271evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +GROUP(libgcc.a) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/m5271evb/Makefile b/board/m5271evb/Makefile deleted file mode 100644 index 2ec71ee..0000000 --- a/board/m5271evb/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o mii.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/m5271evb/config.mk b/board/m5271evb/config.mk deleted file mode 100644 index 9a7af7c..0000000 --- a/board/m5271evb/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xffe00000 diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c deleted file mode 100644 index e089d5f..0000000 --- a/board/m5271evb/m5271evb.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/immap.h> - -int checkboard (void) { - puts ("Board: Freescale M5271EVB\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - - int i; - - /* Enable Address lines 23-21 and lower 16bits of data path */ - mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | - MCF_GPIO_AD_DATAL); - - /* Set CS2 pin to be SD_CS0 */ - mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) - | MCF_GPIO_PAR_CS_PAR_CS2); - - /* Configure SDRAM Control Pin Assignemnt Register */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | - MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_11); - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { - /* Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x01) - | MCF_SDRAMC_DCR_RC(0x30)); - - /* - * Initialize DACR0 - * - * CASL: 01 - * CBM: cmd at A20, bank select bits 21 and up - * PS: 32bit port size - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) - | MCF_SDRAMC_DACRn_CASL(1) - | MCF_SDRAMC_DACRn_CBM(3) - | MCF_SDRAMC_DACRn_PS(0)); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M - | MCF_SDRAMC_DMRn_V); - - /* Set IP bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_IP); - - /* Wait at least 20ns to allow banks to precharge */ - for (i = 0; i < 5; i++) - asm(" nop"); - - /* Write to this block to initiate precharge */ - *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5; - - /* Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_RE); - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_MRS); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 2 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5; - } - - return CFG_SDRAM_SIZE * 1024 * 1024; -}; - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c deleted file mode 100644 index 78a7028..0000000 --- a/board/m5271evb/mii.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); - } else { - } - - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ -#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" -#define STR_ID_KS8721BL "KS8721BL" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - strcpy(info->phy_name, - STR_ID_KS8721BL); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - printf(STR_ID_KS8721BL); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5271evb/u-boot.lds b/board/m5271evb/u-boot.lds deleted file mode 100644 index c07d023..0000000 --- a/board/m5271evb/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -GROUP(libgcc.a) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) - common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Add M54451EVB platform support for MCF5445x
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- MAKEALL | 1 + Makefile | 24 +++ board/freescale/m54451evb/Makefile | 44 ++++ board/freescale/m54451evb/config.mk | 27 +++ board/freescale/m54451evb/m54451evb.c | 108 ++++++++++ board/freescale/m54451evb/mii.c | 303 ++++++++++++++++++++++++++++ board/freescale/m54451evb/u-boot.spa | 143 ++++++++++++++ board/freescale/m54451evb/u-boot.stm | 149 ++++++++++++++ include/asm-m68k/immap.h | 6 +- include/configs/M54451EVB.h | 350 +++++++++++++++++++++++++++++++++ 10 files changed, 1153 insertions(+), 2 deletions(-) create mode 100644 board/freescale/m54451evb/Makefile create mode 100644 board/freescale/m54451evb/config.mk create mode 100644 board/freescale/m54451evb/m54451evb.c create mode 100644 board/freescale/m54451evb/mii.c create mode 100644 board/freescale/m54451evb/u-boot.spa create mode 100644 board/freescale/m54451evb/u-boot.stm create mode 100644 include/configs/M54451EVB.h diff --git a/MAKEALL b/MAKEALL index 535d28a..33302ae 100755 --- a/MAKEALL +++ b/MAKEALL @@ -699,6 +699,7 @@ LIST_coldfire=" \ M5282EVB \ M5329AFEE \ M5373EVB \ + M54451EVB \ M54455EVB \ M5475AFE \ M5485AFE \ diff --git a/Makefile b/Makefile index 4fa235e..3b99d7a 100644 --- a/Makefile +++ b/Makefile @@ -1892,6 +1892,30 @@ M5373EVB_config : unconfig fi @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale +M54451EVB_config \ +M54451EVB_spansion_config \ +M54451EVB_stmicro_config : unconfig + @case "$@" in \ + M54451EVB_config) FLASH=SPANSION;; \ + M54451EVB_spansion_config) FLASH=SPANSION;; \ + M54451EVB_stmicro_config) FLASH=STMICRO;; \ + esac; \ + if [ "$${FLASH}" = "SPANSION" ] ; then \ + echo "#define CFG_SPANSION_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \ + cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \ + $(XECHO) "... with SPANSION boot..." ; \ + fi; \ + if [ "$${FLASH}" = "STMICRO" ] ; then \ + echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \ + echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \ + cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \ + $(XECHO) "... with ST Micro boot..." ; \ + fi; \ + echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ; + @$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale + M54455EVB_config \ M54455EVB_atmel_config \ M54455EVB_intel_config \ diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile new file mode 100644 index 0000000..74c2528 --- /dev/null +++ b/board/freescale/m54451evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m54451evb/config.mk b/board/freescale/m54451evb/config.mk new file mode 100644 index 0000000..b42fcc9 --- /dev/null +++ b/board/freescale/m54451evb/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c new file mode 100644 index 0000000..5b33a83 --- /dev/null +++ b/board/freescale/m54451evb/m54451evb.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + /* + * need to to: + * Check serial flash size. if 2mb evb, else 8mb demo + */ + puts("Board: "); + puts("Freescale M54451 EVB\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + u32 dramsize; +#ifdef CONFIG_CF_SBF + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; +#else + volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 i; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + + if ((sdram->sdcfg1 == CFG_SDRAM_CFG1) && + (sdram->sdcfg2 == CFG_SDRAM_CFG2)) + return dramsize; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + gpio->mscr_sdram = 0x44; + + sdram->sdcs0 = (CFG_SDRAM_BASE | i); + + sdram->sdcfg1 = CFG_SDRAM_CFG1; + sdram->sdcfg2 = CFG_SDRAM_CFG2; + + udelay(200); + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + __asm__("nop"); + + /* Perform two refresh cycles */ + sdram->sdcr = CFG_SDRAM_CTRL | 4; + __asm__("nop"); + sdram->sdcr = CFG_SDRAM_CTRL | 4; + __asm__("nop"); + + /* Issue LEMR */ + sdram->sdmr = CFG_SDRAM_MODE; + __asm__("nop"); + sdram->sdmr = CFG_SDRAM_EMOD; + __asm__("nop"); + + sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000000; + + udelay(100); +#endif + return (dramsize); +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m54451evb/mii.c b/board/freescale/m54451evb/mii.c new file mode 100644 index 0000000..5a4330c --- /dev/null +++ b/board/freescale/m54451evb/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fec.h> +#include <asm/immap.h> + +#include <config.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + else + gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + else + gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_KSZ8041NL 0x00221512 +#define STR_ID_KSZ8041NL "KSZ8041NL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + struct eth_device *dev; + int i, miispd; + u16 rst = 0; + + dev = eth_get_dev(); + + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); + for (i = 0; i < FEC_RESET_DELAY; ++i) { + udelay(500); + miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); + if ((rst & PHY_BMCR_RESET) == 0) + break; + } + if (i == FEC_RESET_DELAY) + printf("Mii reset timeout %d\n", i); +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KSZ8041NL: + strcpy(info->phy_name, + STR_ID_KSZ8041NL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KSZ8041NL: + printf(STR_ID_KSZ8041NL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) __attribute__ ((weak, alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m54451evb/u-boot.spa b/board/freescale/m54451evb/u-boot.spa new file mode 100644 index 0000000..22c6048 --- /dev/null +++ b/board/freescale/m54451evb/u-boot.spa @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m54451evb/u-boot.stm b/board/freescale/m54451evb/u-boot.stm new file mode 100644 index 0000000..0752e27 --- /dev/null +++ b/board/freescale/m54451evb/u-boot.stm @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) +/* cpu/mcf5445x/cpu_init.o (.text) + cpu/mcf5445x/cpu.o (.text) + cpu/mcf5445x/dspi.o (.text) + cpu/mcf5445x/interrupt.o (.text) + cpu/mcf5445x/speed.o (.text) + lib_m68k/board.o (.text) + common/serial.o (.text) + common/console.o (.text) + lib_generic/display_options.o (.text) + board/freescale/m54455evb/m54455evb.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) +*/ + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index f1586d5..b0814f1 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -257,12 +257,14 @@ #define CFG_NUM_IRQS (128) #endif /* CONFIG_M5329 && CONFIG_M5373 */ -#ifdef CONFIG_M54455 +#if defined(CONFIG_M54451) || defined(CONFIG_M54455) #include <asm/immap_5445x.h> #include <asm/m5445x.h> #define CFG_FEC0_IOBASE (MMAP_FEC0) +#if defined(CONFIG_M54455EVB) #define CFG_FEC1_IOBASE (MMAP_FEC1) +#endif #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) @@ -295,7 +297,7 @@ #define CFG_PCI_TBATR0 (CFG_MBAR) #define CFG_PCI_TBATR5 (CFG_SDRAM_BASE) #endif -#endif /* CONFIG_M54455 */ +#endif /* CONFIG_M54451 || CONFIG_M54455 */ #ifdef CONFIG_M547x #include <asm/immap_547x_8x.h> diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h new file mode 100644 index 0000000..bdc539e --- /dev/null +++ b/include/configs/M54451EVB.h @@ -0,0 +1,350 @@ +/* + * Configuation settings for the Freescale MCF54451 EVB board. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M54451EVB_H +#define _M54451EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5445x /* define processor family */ +#define CONFIG_M54451 /* define processor type */ +#define CONFIG_M54451EVB /* M54451EVB board */ + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 + +# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME M54451EVB +#ifdef CFG_STMICRO_BOOT +/* ST Micro serial flash */ +#define CFG_LOAD_ADDR2 0x40010007 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \ + "upd=run load; run prog\0" \ + "prog=sf probe 0:1 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ + "save\0" \ + "" +#else +#define CFG_UBOOT_END 0x3FFFF +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 " MK_STR(CFG_UBOOT_END)\ + "; era 0 " MK_STR(CFG_UBOOT_END) \ + "2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" +#endif + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CFG_RTC_OSCILLATOR (32 * CFG_HZ) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_SERIAL_FLASH +#define CONFIG_HARD_SPI +#define CFG_SER_FLASH_BASE 0x01000000 +#define CFG_SBFHDR_SIZE 0x7 +#ifdef CONFIG_CMD_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_STMICRO + +# define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ + DSPI_DCTAR_CPOL | \ + DSPI_DCTAR_CPHA | \ + DSPI_DCTAR_PCSSCK_1CLK | \ + DSPI_DCTAR_PASC(0) | \ + DSPI_DCTAR_PDT(0) | \ + DSPI_DCTAR_CSSCK(0) | \ + DSPI_DCTAR_ASC(0) | \ + DSPI_DCTAR_PBR(0) | \ + DSPI_DCTAR_DT(1) | \ + DSPI_DCTAR_BR(1)) +#endif + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) + +#define CFG_HZ 1000 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 128 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x33633F30 +#define CFG_SDRAM_CFG2 0x57670000 +#define CFG_SDRAM_CTRL 0xE20D2C00 +#define CFG_SDRAM_EMOD 0x80810000 +#define CFG_SDRAM_MODE 0x008D0000 +#define CFG_SDRAM_DRV_STRENGTH 0x44 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#ifdef CONFIG_CF_SBF +# define CFG_MONITOR_BASE (TEXT_BASE + 0x400) +#else +# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#if defined(CONFIG_CF_SBF) +# define CFG_ENV_IS_IN_SPI_FLASH 1 +# define CFG_ENV_SPI_CS 1 +# define CFG_ENV_OFFSET 0x20000 +# define CFG_ENV_SIZE 0x2000 +# define CFG_ENV_SECT_SIZE 0x10000 +#else +# define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) +# define CFG_ENV_SECT_SIZE 0x2000 +#endif +#undef CONFIG_ENV_OVERWRITE +#undef CFG_ENV_IS_EMBEDDED + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CFG_STMICRO_BOOT +# define CFG_FLASH_BASE CFG_SER_FLASH_BASE +# define CFG_FLASH0_BASE CFG_SER_FLASH_BASE +# define CFG_FLASH1_BASE CFG_CS0_BASE +#endif +#ifdef CFG_SPANSION_BOOT +# define CFG_FLASH_BASE CFG_CS0_BASE +# define CFG_FLASH0_BASE CFG_CS0_BASE +# define CFG_FLASH1_BASE CFG_SER_FLASH_BASE +#endif + +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE } + +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CFG_SPANSION_BOOT +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) +#endif +#ifdef CFG_STMICRO_BOOT +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 8MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ + + /* SPANSION Flash */ +#define CFG_CS0_BASE 0x00000000 +#define CFG_CS0_MASK 0x007F0001 +#define CFG_CS0_CTRL 0x00001180 + +#define CFG_SPANSION_BASE CFG_CS0_BASE + +#endif /* _M54451EVB_H */ -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Add Serial Flash support for M54455EVB
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- include/configs/M54455EVB.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index b7b5da0..e68b26e 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -77,6 +77,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SPI +#define CONFIG_CMD_SF #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_LOADS @@ -205,6 +206,9 @@ #define CFG_SER_FLASH_BASE 0x01000000 #define CFG_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_STMICRO + # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ DSPI_DCTAR_CPOL | \ DSPI_DCTAR_CPHA | \ -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Implement SBF feature for M5445EVB
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- Makefile | 16 ++- board/freescale/m54455evb/m54455evb.c | 14 ++- board/freescale/m54455evb/u-boot.stm | 136 +++++++++++++++++ cpu/mcf5445x/cpu_init.c | 2 + cpu/mcf5445x/speed.c | 67 ++++++--- cpu/mcf5445x/start.S | 258 ++++++++++++++++++++++++++++++++- include/configs/M54455EVB.h | 92 ++++++++++-- 7 files changed, 539 insertions(+), 46 deletions(-) create mode 100644 board/freescale/m54455evb/u-boot.stm diff --git a/Makefile b/Makefile index 89746a2..4fa235e 100644 --- a/Makefile +++ b/Makefile @@ -1898,7 +1898,8 @@ M54455EVB_intel_config \ M54455EVB_a33_config \ M54455EVB_a66_config \ M54455EVB_i33_config \ -M54455EVB_i66_config : unconfig +M54455EVB_i66_config \ +M54455EVB_stm33_config : unconfig @case "$@" in \ M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \ M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \ @@ -1907,18 +1908,27 @@ M54455EVB_i66_config : unconfig M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \ M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \ M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \ + M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \ esac; \ if [ "$${FLASH}" = "INTEL" ] ; then \ - echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ + echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \ $(XECHO) "... with INTEL boot..." ; \ - else \ + fi; \ + if [ "$${FLASH}" = "ATMEL" ] ; then \ echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \ $(XECHO) "... with ATMEL boot..." ; \ fi; \ + if [ "$${FLASH}" = "STMICRO" ] ; then \ + echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \ + echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \ + echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \ + cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \ + $(XECHO) "... with ST Micro boot..." ; \ + fi; \ echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ $(XECHO) "... with $${FREQ}Hz input clock" @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 3c7b350..4f02121 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -39,9 +39,17 @@ int checkboard(void) phys_size_t initdram(int board_type) { + u32 dramsize; +#ifdef CONFIG_CF_SBF + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; +#else volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); - u32 dramsize, i; + u32 i; dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; @@ -51,7 +59,7 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = 0xAA; + gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH; sdram->sdcs0 = (CFG_SDRAM_BASE | i); sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); @@ -80,7 +88,7 @@ phys_size_t initdram(int board_type) sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; udelay(100); - +#endif return (dramsize << 1); }; diff --git a/board/freescale/m54455evb/u-boot.stm b/board/freescale/m54455evb/u-boot.stm new file mode 100644 index 0000000..3dd9a6b --- /dev/null +++ b/board/freescale/m54455evb/u-boot.stm @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index e07748b..51a9e90 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -61,11 +61,13 @@ void cpu_init_f(void) GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS; +#if !defined(CONFIG_CF_SBF) #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) fbcs->csar0 = CFG_CS0_BASE; fbcs->cscr0 = CFG_CS0_CTRL; fbcs->csmr0 = CFG_CS0_MASK; #endif +#endif #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) /* Latch chipselect */ diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c index 967becf..f677f3c 100644 --- a/cpu/mcf5445x/speed.c +++ b/cpu/mcf5445x/speed.c @@ -84,26 +84,29 @@ void clock_exit_limp(void) */ int get_clocks(void) { + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; - volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); - volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14); int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; int pllmult_pci[] = { 12, 6, 16, 8 }; - int vco, bPci, temp, fbtemp, pcrvalue; + int vco = 0, bPci, temp, fbtemp, pcrvalue; int *pPllmult = NULL; u16 fbpll_mask; - u8 cpldmode; + +#ifdef CONFIG_M54455EVB + volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); +#endif + u8 bootmode; /* To determine PCI is present or not */ if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { pPllmult = &pllmult_pci[0]; - fbpll_mask = 3; + fbpll_mask = 3; /* 11b */ bPci = 1; } else { pPllmult = &pllmult_nopci[0]; - fbpll_mask = 7; + fbpll_mask = 7; /* 111b */ #ifdef CONFIG_PCI gd->pci_clk = 0; #endif @@ -111,20 +114,36 @@ int get_clocks(void) } #ifdef CONFIG_M54455EVB - /* Temporary place here, belongs in board/freescale/... */ - /* Temporary read from CCR- fixed fb issue, must be the same clock - as pci or input clock, causing cpld/fpga read inconsistancy */ - fbtemp = pPllmult[ccm->ccr & fbpll_mask]; + bootmode = (*cpld & 0x03); - /* Break down into small pieces, code still in flex bus */ - pcrvalue = pll->pcr & 0xFFFFF0FF; - temp = fbtemp - 1; - pcrvalue |= PLL_PCR_OUTDIV3(temp); + if (bootmode != 3) { + /* Temporary read from CCR- fixed fb issue, must be the same clock + as pci or input clock, causing cpld/fpga read inconsistancy */ + fbtemp = pPllmult[ccm->ccr & fbpll_mask]; + /* Break down into small pieces, code still in flex bus */ + pcrvalue = pll->pcr & 0xFFFFF0FF; + temp = fbtemp - 1; + pcrvalue |= PLL_PCR_OUTDIV3(temp); + + pll->pcr = pcrvalue; + } +#endif +#ifdef CONFIG_M54451EVB + /* No external logic to read the bootmode, hard coded from built */ +#ifdef CONFIG_CF_SBF + bootmode = 3; +#else + bootmode = 2; + + /* default value is 16 mul, set to 20 mul */ + pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000; pll->pcr = pcrvalue; + while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK); +#endif +#endif - cpldmode = *cpld & 0x03; - if (cpldmode == 0) { + if (bootmode == 0) { /* RCON mode */ vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC; @@ -151,14 +170,22 @@ int get_clocks(void) pll->pcr = pcrvalue; } gd->vco_clk = vco; /* Vco clock */ - } else if (cpldmode == 2) { + } else if (bootmode == 2) { /* Normal mode */ - vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC; + vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { + /* Default value */ + pcrvalue = (pll->pcr & 0x00FFFFFF); + pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24; + pll->pcr = pcrvalue; + vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + } gd->vco_clk = vco; /* Vco clock */ - } else if (cpldmode == 3) { + } else if (bootmode == 3) { /* serial mode */ + vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + gd->vco_clk = vco; /* Vco clock */ } -#endif /* CONFIG_M54455EVB */ if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 89ec7bc..4bfc625 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -46,15 +46,30 @@ addl #60,%sp; /* space for 15 regs */ \ rte; +#if defined(CONFIG_CF_SBF) +#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR) +#endif + .text + /* * Vector table. This is used for initial platform startup. * These vectors are to catch any un-intended traps. */ _vectors: +#if defined(CONFIG_CF_SBF) + +INITSP: .long 0 /* Initial SP */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ + +#else + +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ + +#endif -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ @@ -83,6 +98,8 @@ vector1D: .long _FAULT /* Autovector Level 5 */ vector1E: .long _FAULT /* Autovector Level 6 */ vector1F: .long _FAULT /* Autovector Level 7 */ +#if !defined(CONFIG_CF_SBF) + /* TRAP #0 - #15 */ vector20_2F: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -122,9 +139,237 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif - .text +#if defined(CONFIG_CF_SBF) + /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ +asm_sbf_img_hdr: + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00030000 /* image length */ + .long TEXT_BASE /* image to be relocated at */ + +asm_dram_init: + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 /* init Rambar */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* Must disable global address */ + move.l #0xFC008000, %a1 + move.l #(CFG_CS0_BASE), (%a1) + move.l #0xFC008008, %a1 + move.l #(CFG_CS0_CTRL), (%a1) + move.l #0xFC008004, %a1 + move.l #(CFG_CS0_MASK), (%a1) + + /* + * Dram Initialization + * a1, a2, and d0 + */ + /* mscr sdram */ + move.l #0xFC0A4074, %a1 + move.b #(CFG_SDRAM_DRV_STRENGTH), (%a1) + nop + + /* SDRAM Chip 0 and 1 */ + move.l #0xFC0B8110, %a1 + move.l #0xFC0B8114, %a2 + + /* calculate the size */ + move.l #0x13, %d1 + move.l #(CFG_SDRAM_SIZE), %d2 +#ifdef CFG_SDRAM_BASE1 + lsr.l #1, %d2 +#endif + +dramsz_loop: + lsr.l #1, %d2 + add.l #1, %d1 + cmp.l #1, %d2 + bne dramsz_loop + + /* SDRAM Chip 0 and 1 */ + move.l #(CFG_SDRAM_BASE), (%a1) + or.l %d1, (%a1) +#ifdef CFG_SDRAM_BASE1 + move.l #(CFG_SDRAM_BASE1), (%a2) + or.l %d1, (%a2) +#endif + nop + + /* dram cfg1 and cfg2 */ + move.l #0xFC0B8008, %a1 + move.l #(CFG_SDRAM_CFG1), (%a1) + nop + move.l #0xFC0B800C, %a2 + move.l #(CFG_SDRAM_CFG2), (%a2) + nop + + move.l #0xFC0B8000, %a1 /* Mode */ + move.l #0xFC0B8004, %a2 /* Ctrl */ + +#ifdef CONFIG_M54455EVB + /* Issue PALL */ + move.l #(CFG_SDRAM_CTRL + 2), (%a2) + nop + + /* Issue LEMR */ + move.l #(CFG_SDRAM_EMOD + 0x408), (%a1) + nop + move.l #(CFG_SDRAM_MODE + 0x300), (%a1) + nop + + move.l #1000, %d0 +wait1000: + nop + subq.l #1, %d0 + bne wait1000 +#endif + + /* Issue PALL */ + move.l #(CFG_SDRAM_CTRL + 2), (%a2) + nop + + /* Perform two refresh cycles */ + move.l #(CFG_SDRAM_CTRL + 4), %d0 + nop + move.l %d0, (%a2) + move.l %d0, (%a2) + nop +#ifdef CONFIG_M54455EVB + move.l #(CFG_SDRAM_MODE + 0x200), (%a1) + nop +#elif defined(CONFIG_M54451EVB) + /* Issue LEMR */ + move.l #(CFG_SDRAM_MODE), (%a2) + nop + move.l #(CFG_SDRAM_EMOD), (%a2) + nop +#endif + + move.l #500, %d0 +wait500: + nop + subq.l #1, %d0 + bne wait500 + + move.l #(CFG_SDRAM_CTRL), %d0 + and.l #0x7FFFFFFF, %d0 +#ifdef CONFIG_M54455EVB + or.l #0x10000c00, %d0 +#elif defined(CONFIG_M54451EVB) + or.l #0x10000000, %d0 +#endif + move.l %d0, (%a2) + nop + + /* + * DSPI Initialization + * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h + * a1 - dspi status + * a2 - dtfr + * a3 - drfr + * a4 - Dst addr + */ + /* Enable pins for DSPI mode - chip-selects are enabled later */ + move.l #0xFC0A4063, %a0 + move.b #0x7F, (%a0) + + /* Configure DSPI module */ + move.l #0xFC05C000, %a0 + move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ + + move.l #0xFC05C00C, %a0 + move.l #0x3E000011, (%a0) + + move.l #0xFC05C034, %a2 /* dtfr */ + move.l #0xFC05C03B, %a3 /* drfr */ + + move.l #(ASM_SBF_IMG_HDR + 4), %a1 + move.l (%a1)+, %d5 + move.l (%a1), %a4 + + move.l #(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0 + move.l #(CFG_SBFHDR_SIZE), %d4 + + move.l #0xFC05C02C, %a1 /* dspi status */ + + /* Issue commands and address */ + move.l #0x8002000B, %d2 /* Fast Read Cmd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 2 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 1 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 0 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Dummy Wr and Rd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* Transfer serial boot header to sram */ +asm_dspi_rd_loop1: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a0) /* read, copy to dst */ + + add.l #1, %a0 /* inc dst by 1 */ + sub.l #1, %d4 /* dec cnt by 1 */ + bne asm_dspi_rd_loop1 + + /* Transfer u-boot from serial flash to memory */ +asm_dspi_rd_loop2: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a4) /* read, copy to dst */ + + add.l #1, %a4 /* inc dst by 1 */ + sub.l #1, %d5 /* dec cnt by 1 */ + bne asm_dspi_rd_loop2 + + move.l #0x00020000, %d2 /* Terminate */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* jump to memory and execute */ + move.l #(TEXT_BASE + 0x400), %a0 + jmp (%a0) + +asm_dspi_wr_status: + move.l (%a1), %d0 /* status */ + and.l #0x0000F000, %d0 + cmp.l #0x00003000, %d0 + bgt asm_dspi_wr_status + + move.l %d2, (%a2) + rts + +asm_dspi_rd_status: + move.l (%a1), %d0 /* status */ + and.l #0x000000F0, %d0 + lsr.l #4, %d0 + cmp.l #0, %d0 + beq asm_dspi_rd_status + + move.b (%a3), %d1 + rts +#endif /* CONFIG_CF_SBF */ + + .text + . = 0x400 .globl _start _start: nop @@ -132,11 +377,16 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ +#if defined(CONFIG_CF_SBF) + move.l #TEXT_BASE, %d0 + movec %d0, %VBR +#else move.l #CFG_FLASH_BASE, %d0 movec %d0, %VBR move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 +#endif /* initialize general use internal ram */ move.l #0, %d0 @@ -253,7 +503,7 @@ clear_bss: /* exception code */ .globl _fault _fault: - bra _fault + jmp _fault .globl _exc_handler _exc_handler: diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 936766a..b7b5da0 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -121,18 +121,45 @@ #endif #define CONFIG_HOSTNAME M54455EVB +#ifdef CFG_STMICRO_BOOT +/* ST Micro serial flash */ +#define CFG_LOAD_ADDR2 0x40010013 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \ "upd=run load; run prog\0" \ - "prog=prot off 4000000 402ffff;" \ - "era 4000000 402ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=sf probe 0:1 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 0x30000;" \ "save\0" \ "" +#else +/* Atmel and Intel */ +#ifdef CFG_ATMEL_BOOT +# define CFG_UBOOT_END 0x0403FFFF +#elif defined(CFG_INTEL_BOOT) +# define CFG_UBOOT_END 0x3FFFF +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off " MK_STR(CFG_FLASH_BASE) \ + " " MK_STR(CFG_UBOOT_END) ";" \ + "era " MK_STR(CFG_FLASH_BASE) " " \ + MK_STR(CFG_UBOOT_END) ";" \ + "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\ + " ${filesize}; save\0" \ + "" +#endif /* ATA configuration */ #define CONFIG_ISO_PARTITION @@ -175,6 +202,8 @@ /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI #define CONFIG_HARD_SPI +#define CFG_SER_FLASH_BASE 0x01000000 +#define CFG_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ DSPI_DCTAR_CPOL | \ @@ -221,7 +250,7 @@ /* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK -#define CONFIG_PRAM 512 /* 512 KB */ +#define CONFIG_PRAM 2048 /* 2048 KB */ #define CFG_PROMPT "-> " #define CFG_LONGHELP /* undef to save memory */ @@ -254,8 +283,9 @@ #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CFG_INIT_RAM_CTRL 0x221 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32) /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -270,11 +300,16 @@ #define CFG_SDRAM_CTRL 0xEA0B2000 #define CFG_SDRAM_EMOD 0x40010000 #define CFG_SDRAM_MODE 0x00010033 +#define CFG_SDRAM_DRV_STRENGTH 0xAA #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) -#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#ifdef CONFIG_CF_SBF +# define CFG_MONITOR_BASE (TEXT_BASE + 0x400) +#else +# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif #define CFG_BOOTPARAMS_LEN 64*1024 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -287,27 +322,44 @@ /* Initial Memory map for Linux */ #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) -/* Configuration for environment +/* + * Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OVERWRITE 1 +#ifdef CONFIG_CF_SBF +# define CFG_ENV_IS_IN_SPI_FLASH +# define CFG_ENV_SPI_CS 1 +#else +# define CFG_ENV_IS_IN_FLASH 1 +#endif +#undef CONFIG_ENV_OVERWRITE #undef CFG_ENV_IS_EMBEDDED /*----------------------------------------------------------------------- * FLASH organization */ +#ifdef CFG_STMICRO_BOOT +# define CFG_FLASH_BASE CFG_SER_FLASH_BASE +# define CFG_FLASH0_BASE CFG_SER_FLASH_BASE +# define CFG_FLASH1_BASE CFG_CS0_BASE +# define CFG_FLASH2_BASE CFG_CS1_BASE +# define CFG_ENV_OFFSET 0x30000 +# define CFG_ENV_SIZE 0x2000 +# define CFG_ENV_SECT_SIZE 0x10000 +#endif #ifdef CFG_ATMEL_BOOT # define CFG_FLASH_BASE CFG_CS0_BASE # define CFG_FLASH0_BASE CFG_CS0_BASE # define CFG_FLASH1_BASE CFG_CS1_BASE # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) # define CFG_ENV_SECT_SIZE 0x2000 -#else +#endif +#ifdef CFG_INTEL_BOOT # define CFG_FLASH_BASE CFG_CS0_BASE # define CFG_FLASH0_BASE CFG_CS0_BASE # define CFG_FLASH1_BASE CFG_CS1_BASE -# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) +# define CFG_ENV_SIZE 0x2000 # define CFG_ENV_SECT_SIZE 0x20000 #endif @@ -339,15 +391,23 @@ * This is setting for JFFS2 support in u-boot. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ +#ifdef CONFIG_CMD_JFFS2 +#ifdef CF_STMICRO_BOOT +# define CONFIG_JFFS2_DEV "nor1" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH2_BASE + 0x500000) +#endif #ifdef CFG_ATMEL_BOOT # define CONFIG_JFFS2_DEV "nor1" # define CONFIG_JFFS2_PART_SIZE 0x01000000 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000) -#else +#endif +#ifdef CFG_INTEL_BOOT # define CONFIG_JFFS2_DEV "nor0" # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) #endif +#endif /*----------------------------------------------------------------------- * Cache Configuration @@ -366,7 +426,7 @@ * CS5 - Available */ -#ifdef CFG_ATMEL_BOOT +#if defined(CFG_ATMEL_BOOT) || defined(CFG_STMICRO_BOOT) /* Atmel Flash */ #define CFG_CS0_BASE 0x04000000 #define CFG_CS0_MASK 0x00070001 -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Add SSPI feature for MCF5445x
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- cpu/mcf5445x/dspi.c | 178 +++++++++++++++++++++++++++++++++++++++++-- include/configs/M54455EVB.h | 16 ++++- lib_m68k/board.c | 17 ++++ 3 files changed, 204 insertions(+), 7 deletions(-) diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c index 44d8505..959d6bd 100644 --- a/cpu/mcf5445x/dspi.c +++ b/cpu/mcf5445x/dspi.c @@ -27,9 +27,11 @@ #include <common.h> #include <spi.h> +#include <malloc.h> #if defined(CONFIG_CF_DSPI) #include <asm/immap.h> + void dspi_init(void) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; @@ -45,11 +47,30 @@ void dspi_init(void) DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; - dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA | - DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) | - DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) | - DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) | - DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1); +#ifdef CFG_DSPI_DCTAR0 + dspi->dctar0 = CFG_DSPI_DCTAR0; +#endif +#ifdef CFG_DSPI_DCTAR1 + dspi->dctar1 = CFG_DSPI_DCTAR1; +#endif +#ifdef CFG_DSPI_DCTAR2 + dspi->dctar2 = CFG_DSPI_DCTAR2; +#endif +#ifdef CFG_DSPI_DCTAR3 + dspi->dctar3 = CFG_DSPI_DCTAR3; +#endif +#ifdef CFG_DSPI_DCTAR4 + dspi->dctar4 = CFG_DSPI_DCTAR4; +#endif +#ifdef CFG_DSPI_DCTAR5 + dspi->dctar5 = CFG_DSPI_DCTAR5; +#endif +#ifdef CFG_DSPI_DCTAR6 + dspi->dctar6 = CFG_DSPI_DCTAR6; +#endif +#ifdef CFG_DSPI_DCTAR7 + dspi->dctar7 = CFG_DSPI_DCTAR7; +#endif } void dspi_tx(int chipsel, u8 attrib, u16 data) @@ -70,4 +91,149 @@ u16 dspi_rx(void) return (dspi->drfr & 0xFFFF); } -#endif /* CONFIG_HARD_SPI */ +#if defined(CONFIG_CMD_SPI) +void spi_init_f(void) +{ +} + +void spi_init_r(void) +{ +} + +void spi_init(void) +{ + dspi_init(); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + static int bWrite = 0; + u8 *spi_rd, *spi_wr; + int len = bitlen >> 3; + + spi_rd = (u8 *) din; + spi_wr = (u8 *) dout; + + /* command handling */ + if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) { + switch (*spi_wr) { + case 0x02: /* Page Prog */ + bWrite = 1; + dspi_tx(slave->cs, 0x80, spi_wr[0]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[1]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[2]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[3]); + dspi_rx(); + return 0; + case 0x05: /* Read Status */ + if (len == 4) + if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF) + && (spi_wr[3] == 0xFF)) { + dspi_tx(slave->cs, 0x80, *spi_wr); + dspi_rx(); + } + return 0; + case 0x06: /* WREN */ + dspi_tx(slave->cs, 0x00, *spi_wr); + dspi_rx(); + return 0; + case 0x0B: /* Fast read */ + if ((len == 5) && (spi_wr[4] == 0)) { + dspi_tx(slave->cs, 0x80, spi_wr[0]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[1]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[2]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[3]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[4]); + dspi_rx(); + } + return 0; + case 0x9F: /* RDID */ + dspi_tx(slave->cs, 0x80, *spi_wr); + dspi_rx(); + return 0; + case 0xD8: /* Sector erase */ + if (len == 4) + if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) { + dspi_tx(slave->cs, 0x80, spi_wr[0]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[1]); + dspi_rx(); + dspi_tx(slave->cs, 0x80, spi_wr[2]); + dspi_rx(); + dspi_tx(slave->cs, 0x00, spi_wr[3]); + dspi_rx(); + } + return 0; + } + } + + if (bWrite) + len--; + + while (len--) { + if (dout != NULL) { + dspi_tx(slave->cs, 0x80, *spi_wr); + dspi_rx(); + spi_wr++; + } + + if (din != NULL) { + dspi_tx(slave->cs, 0x80, 0); + *spi_rd = dspi_rx(); + spi_rd++; + } + } + + if (flags == SPI_XFER_END) { + if (bWrite) { + dspi_tx(slave->cs, 0x00, *spi_wr); + dspi_rx(); + bWrite = 0; + } else { + dspi_tx(slave->cs, 0x00, 0); + dspi_rx(); + } + } + + return 0; +} +#endif /* CONFIG_CMD_SPI */ + +#endif /* CONFIG_CF_DSPI */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 82942d0..936766a 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -76,6 +76,7 @@ #undef CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SPI #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_LOADS @@ -173,7 +174,20 @@ /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI -#define CONFIG_SERIAL_FLASH +#define CONFIG_HARD_SPI +#ifdef CONFIG_CMD_SPI +# define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ + DSPI_DCTAR_CPOL | \ + DSPI_DCTAR_CPHA | \ + DSPI_DCTAR_PCSSCK_1CLK | \ + DSPI_DCTAR_PASC(0) | \ + DSPI_DCTAR_PDT(0) | \ + DSPI_DCTAR_CSSCK(0) | \ + DSPI_DCTAR_ASC(0) | \ + DSPI_DCTAR_PBR(0) | \ + DSPI_DCTAR_DT(1) | \ + DSPI_DCTAR_BR(1)) +#endif /* PCI */ #ifdef CONFIG_CMD_PCI diff --git a/lib_m68k/board.c b/lib_m68k/board.c index a13ea26..dedc9e4 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -59,6 +59,10 @@ #include <i2c.h> #endif +#ifdef CONFIG_CMD_SPI +#include <spi.h> +#endif + DECLARE_GLOBAL_DATA_PTR; static char *failed = "*** failed ***\n"; @@ -212,6 +216,16 @@ static int init_func_i2c (void) } #endif +#if defined(CONFIG_HARD_SPI) +static int init_func_spi (void) +{ + puts ("SPI: "); + spi_init (); + puts ("ready\n"); + return (0); +} +#endif + /***********************************************************************/ /************************************************************************ @@ -231,6 +245,9 @@ init_fnc_t *init_sequence[] = { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) init_func_i2c, #endif +#if defined(CONFIG_HARD_SPI) + init_func_spi, +#endif init_func_ram, #if defined(CFG_DRAM_TEST) testdram, -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Use CFI Flash driver for M54455EVB
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Remove non-common flash driver in board/freescale/m54455evb/flash.c. The non-cfi flash will use CONFIG_FLASH_CFI_LEGACY to configure the flash attribute. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- board/freescale/m54455evb/Makefile | 4 +- board/freescale/m54455evb/flash.c | 1287 --------------------------------- board/freescale/m54455evb/m54455evb.c | 50 ++ include/configs/M54455EVB.h | 45 +- 4 files changed, 58 insertions(+), 1328 deletions(-) delete mode 100644 board/freescale/m54455evb/flash.c diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile index ca9a772..74c2528 100644 --- a/board/freescale/m54455evb/Makefile +++ b/board/freescale/m54455evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o mii.o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -41,4 +41,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -######################################################################### \ No newline at end of file +######################################################################### diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c deleted file mode 100644 index 6b50e8d..0000000 --- a/board/freescale/m54455evb/flash.c +++ /dev/null @@ -1,1287 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#include <asm/immap.h> - -#ifndef CFG_FLASH_CFI -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_WRSETUP 0x00400040 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CFIQRY 0x00980098 -#define INTEL_SUSERASE 0x00B000B0 -#define INTEL_PROTPROG 0x00C000C0 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_WRBLK 0x00e800e8 -#define INTEL_RESET 0x00FF00FF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 -#define INTEL_ERASESUS 0x00600060 -#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) - -/* 28F160C3B CFI Data offset - This could vary */ -#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ -#define INTEL_CFI_PART 0x01 /* Product ID */ -#define INTEL_CFI_LOCK 0x02 /* */ -#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ -#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ -#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ -#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ -#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ -#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ -#define INTEL_CFI_CAP 0x28 -#define INTEL_CFI_WRBUF 0x2A -#define INTEL_CFI_BANK 0x2C /* Number of Bank */ -#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */ -#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */ -#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ -#define INTEL_CFI_SZ1B 0x30 -#define INTEL_CFI_BLK2A 0x31 -#define INTEL_CFI_BLK2B 0x32 -#define INTEL_CFI_SZ2A 0x33 -#define INTEL_CFI_SZ2B 0x34 - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x0aaa - -#define WR_BLOCK 0x20 - -/* not in the flash.h yet */ -#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */ -#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */ -#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */ -#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */ -#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */ -#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */ - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) -#define STM_ID_M25P16 0x20152015 -#define FLASH_M25P16 0x0055 -#endif - -#define SYNC __asm__("nop") - -/*----------------------------------------------------------------------- - * Functions - */ - -ulong flash_get_size(FPWV * addr, flash_info_t * info); -int flash_get_offsets(ulong base, flash_info_t * info); -int flash_cmd_rd(volatile u16 * addr, int index); -int write_data(flash_info_t * info, ulong dest, FPW data); -int write_data_block(flash_info_t * info, ulong src, ulong dest); -int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data); -void inline spin_wheel(void); -void flash_sync_real_protect(flash_info_t * info); -uchar intel_sector_protected(flash_info_t * info, ushort sector); - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) -int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt); -int serial_flash_read_status(int chipsel); -static int ser_flash_cs = 0; -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -ulong flash_init(void) -{ - int i; - ulong size = 0; - ulong fbase = 0; - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - dspi_init(); -#endif - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - memset(&flash_info[i], 0, sizeof(flash_info_t)); - - switch (i) { - case 0: - fbase = (ulong) CFG_FLASH0_BASE; - break; - case 1: - fbase = (ulong) CFG_FLASH1_BASE; - break; -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - case 2: - fbase = (ulong) CFG_FLASH2_BASE; - break; -#endif - } - - flash_get_size((FPWV *) fbase, &flash_info[i]); - flash_get_offsets((ulong) fbase, &flash_info[i]); - fbase += flash_info[i].size; - size += flash_info[i].size; - - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[i]); - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -int flash_get_offsets(ulong base, flash_info_t * info) -{ - int i, j, k; - int sectors, bs, banks; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) { - int sect[] = CFG_ATMEL_SECT; - int sectsz[] = CFG_ATMEL_SECTSZ; - - info->start[0] = base; - for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { - for (j = 0; j < sect[i]; j++, k++) { - info->start[k + 1] = info->start[k] + sectsz[i]; - info->protect[k] = 0; - } - } - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - volatile u16 *addr16 = (volatile u16 *)base; - - *addr16 = (FPW) INTEL_RESET; /* restore read mode */ - *addr16 = (FPW) INTEL_READID; - - banks = addr16[INTEL_CFI_BANK] & 0xff; - - sectors = 0; - info->start[0] = base; - - for (k = 0, i = 0; i < banks; i++) { - /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. - * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count - * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count - */ - bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) - | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * - 0x100); - sectors = - (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; - - for (j = 0; j < sectors; j++, k++) { - info->start[k + 1] = info->start[k] + bs; - } - } - - *addr16 = (FPW) INTEL_RESET; /* restore read mode */ - } -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) { - info->start[0] = CFG_FLASH2_BASE; - for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) { - info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ; - info->protect[k] = 0; - } - } -#endif - - return ERR_OK; -} - -void flash_print_info(flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf("INTEL "); - break; - case FLASH_MAN_ATM: - printf("ATMEL "); - break; -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - case FLASH_MAN_STM: - printf("ST "); - break; -#endif - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AT040: - printf("AT49BV040A\n"); - break; - case FLASH_28F128J3A: - printf("28F128J3A\n"); - break; -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - case FLASH_M25P16: - printf("M25P16\n"); - break; -#endif - default: - printf("Unknown Chip Type\n"); - return; - } - - if (info->size > 0x100000) { - int remainder; - - printf(" Size: %ld", info->size >> 20); - - remainder = (info->size % 0x100000); - if (remainder) { - remainder >>= 10; - remainder = (int)((float) - (((float)remainder / (float)1024) * - 10000)); - printf(".%d ", remainder); - } - - printf("MB in %d Sectors\n", info->sector_count); - } else - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size(FPWV * addr, flash_info_t * info) -{ - volatile u16 *addr16 = (volatile u16 *)addr; - int intel = 0, banks = 0; - u16 value; - int i; - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - if ((ulong) addr == CFG_FLASH2_BASE) { - int manufactId = 0; - int deviceId = 0; - - ser_flash_cs = 1; - - dspi_tx(ser_flash_cs, 0x80, SER_RDID); - dspi_tx(ser_flash_cs, 0x80, 0); - dspi_tx(ser_flash_cs, 0x80, 0); - dspi_tx(ser_flash_cs, 0x80, 0); - - dspi_rx(); - manufactId = dspi_rx(); - deviceId = dspi_rx() << 8; - deviceId |= dspi_rx(); - - dspi_tx(ser_flash_cs, 0x00, 0); - dspi_rx(); - - switch (manufactId) { - case (u8) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - } - - switch (deviceId) { - case (u16) STM_ID_M25P16: - info->flash_id += FLASH_M25P16; - break; - } - - info->sector_count = CFG_STM_SECT; - info->size = CFG_STM_SECT * CFG_STM_SECTSZ; - - return (info->size); - } -#endif - - addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ - - switch (addr[0] & 0xff) { - case (u8) ATM_MANUFACT: - info->flash_id = FLASH_MAN_ATM; - value = addr[1]; - break; - case (u8) INTEL_MANUFACT: - /* Terminate Atmel ID read */ - addr[0] = (FPWV) 0x00F000F0; - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - *addr16 = (FPW) INTEL_RESET; /* restore read mode */ - *addr16 = (FPW) INTEL_READID; - - info->flash_id = FLASH_MAN_INTEL; - value = (addr16[INTEL_CFI_MFG] << 8); - value |= addr16[INTEL_CFI_PART] & 0xff; - intel = 1; - break; - default: - printf("Unknown Flash\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - - *addr = (FPW) 0x00F000F0; - *addr = (FPW) INTEL_RESET; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - switch (value) { - case (u8) ATM_ID_LV040: - info->flash_id += FLASH_AT040; - break; - case (u16) INTEL_ID_28F128J3: - info->flash_id += FLASH_28F128J3A; - break; - case (u16) INTEL_ID_28F64P30T: - info->flash_id += FLASH_28F64P30T; - break; - case (u16) INTEL_ID_28F64P30B: - info->flash_id += FLASH_28F64P30B; - break; - case (u16) INTEL_ID_28F128P30T: - info->flash_id += FLASH_28F128P30T; - break; - case (u16) INTEL_ID_28F128P30B: - info->flash_id += FLASH_28F128P30B; - break; - case (u16) INTEL_ID_28F256P30T: - info->flash_id += FLASH_28F256P30T; - break; - case (u16) INTEL_ID_28F256P30B: - info->flash_id += FLASH_28F256P30B; - break; - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (intel) { - /* Intel spec. under CFI section */ - u32 sz; - int sectors, bs; - - banks = addr16[INTEL_CFI_BANK] & 0xff; - - sectors = sz = 0; - for (i = 0; i < banks; i++) { - /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. - * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count - * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count - */ - bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) - | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * - 0x100); - sectors += - (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; - sz += (bs * sectors); - } - - info->sector_count = sectors; - info->size = sz; - *addr = (FPW) INTEL_RESET; /* restore read mode */ - } else { - int sect[] = CFG_ATMEL_SECT; - int sectsz[] = CFG_ATMEL_SECTSZ; - - info->sector_count = 0; - info->size = 0; - for (i = 0; i < CFG_ATMEL_REGION; i++) { - info->sector_count += sect[i]; - info->size += sect[i] * sectsz[i]; - } - - /* reset ID mode */ - addr[0] = (FPWV) 0x00F000F0; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - return (info->size); -} - -int flash_cmd_rd(volatile u16 * addr, int index) -{ - return (int)addr[index]; -} - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) -int serial_flash_read_status(int chipsel) -{ - u16 status; - - dspi_tx(chipsel, 0x80, SER_RDSR); - dspi_rx(); - - dspi_tx(chipsel, 0x00, 0); - status = dspi_rx(); - - return status; -} -#endif - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -void flash_sync_real_protect(flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - default: - /* no h/w protect support */ - break; - } -} - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -uchar intel_sector_protected(flash_info_t * info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - /*udelay(1); */ - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer(0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* Intel example code uses offset of 4 for 8-bit flash */ - lock_conf_addr = (FPWV *) info->start[sector]; - ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0, flashtype = 0; -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - int count; - u16 status; -#endif - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - - switch (type) { - case FLASH_MAN_ATM: - flashtype = 1; - break; - case FLASH_MAN_INTEL: - flashtype = 2; - break; -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - case FLASH_MAN_STM: - flashtype = 3; - break; -#endif - default: - type = (info->flash_id & FLASH_VENDMASK); - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf("\n"); - - start = get_timer(0); - last = start; - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - /* Perform bulk erase */ - if (flashtype == 3) { - if ((s_last - s_first) == (CFG_STM_SECT - 1)) { - if (prot == 0) { - dspi_tx(ser_flash_cs, 0x00, SER_WREN); - dspi_rx(); - - status = serial_flash_read_status(ser_flash_cs); - if (((status & 0x9C) != 0) - && ((status & 0x02) != 0x02)) { - printf("Can't erase flash\n"); - return 1; - } - - dspi_tx(ser_flash_cs, 0x00, SER_BULK_ERASE); - dspi_rx(); - - count = 0; - start = get_timer(0); - do { - status = - serial_flash_read_status - (ser_flash_cs); - - if (count++ > 0x10000) { - spin_wheel(); - count = 0; - } - - if (get_timer(start) > - CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - } while (status & 0x01); - - printf("\b. done\n"); - return 0; - } else if (prot == CFG_STM_SECT) { - return 1; - } - } - } -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - FPWV *addr = (FPWV *) (info->start[sect]); - int min = 0; - - printf("."); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - switch (flashtype) { - case 1: - { - FPWV *base; /* first address in bank */ - FPWV *atmeladdr; - - flag = disable_interrupts(); - - atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */ - base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */ - - base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ - *atmeladdr = (u8) 0x00300030; /* erase sector */ - - if (flag) - enable_interrupts(); - - while ((*atmeladdr & (u8) 0x00800080) != - (u8) 0x00800080) { - if (get_timer(start) > - CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ - - rcode = 1; - break; - } - } - - *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ - break; - } - - case 2: - { - *addr = (FPW) INTEL_READID; - min = addr[INTEL_CFI_TERB] & 0xff; - min = 1 << min; /* ms */ - min = (min / info->sector_count) * 1000; - - /* start erase block */ - *addr = (FPW) INTEL_CLEAR; /* clear status register */ - *addr = (FPW) INTEL_ERASE; /* erase setup */ - *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ - - while ((*addr & (FPW) INTEL_FINISHED) != - (FPW) INTEL_FINISHED) { - - if (get_timer(start) > - CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ - *addr = (FPW) INTEL_RESET; /* reset to read mode */ - - rcode = 1; - break; - } - } - - *addr = (FPW) INTEL_RESET; /* resest to read mode */ - break; - } - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - case 3: - { - u8 sec = ((ulong) addr >> 16) & 0xFF; - - dspi_tx(ser_flash_cs, 0x00, SER_WREN); - dspi_rx(); - status = - serial_flash_read_status - (ser_flash_cs); - if (((status & 0x9C) != 0) - && ((status & 0x02) != 0x02)) { - printf("Error Programming\n"); - return 1; - } - - dspi_tx(ser_flash_cs, 0x80, - SER_SECT_ERASE); - dspi_tx(ser_flash_cs, 0x80, sec); - dspi_tx(ser_flash_cs, 0x80, 0); - dspi_tx(ser_flash_cs, 0x00, 0); - - dspi_rx(); - dspi_rx(); - dspi_rx(); - dspi_rx(); - - do { - status = - serial_flash_read_status - (ser_flash_cs); - - if (get_timer(start) > - CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - } while (status & 0x01); - - break; - } -#endif - } /* switch (flashtype) */ - } - } - printf(" done\n"); - - return rcode; -} - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int count; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_ATM: - { - u16 data = 0; - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= - sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } - - data = (data >> 8) | (data << 8); - res = write_word_atm(info, (FPWV *) addr, data); - } - return res; - } /* case FLASH_MAN_ATM */ - - case FLASH_MAN_INTEL: - { - ulong cp, wp; - u16 data; - int i, l, rc, port_width; - - /* get lower word aligned address */ - wp = addr; - port_width = sizeof(FPW); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < port_width; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = write_data(info, wp, data)) != 0) - return (rc); - - wp += port_width; - } - - if (cnt > WR_BLOCK) { - /* - * handle word aligned part - */ - count = 0; - while (cnt >= WR_BLOCK) { - - if ((rc = - write_data_block(info, - (ulong) src, - wp)) != 0) - return (rc); - - wp += WR_BLOCK; - src += WR_BLOCK; - cnt -= WR_BLOCK; - - if (count++ > 0x800) { - spin_wheel(); - count = 0; - } - } - } - - /* handle word aligned part */ - if (cnt < WR_BLOCK) { - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) - data = (data << 8) | *src++; - - if ((rc = - write_data(info, - (ulong) ((FPWV *) wp), - (FPW) (data))) != 0) - return (rc); - - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel(); - count = 0; - } - } - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; - ++i, ++cp) { - data = (data << 8) | (*src++); - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return write_data(info, (ulong) ((FPWV *) wp), - (FPW) data); - - } /* case FLASH_MAN_INTEL */ - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) - case FLASH_MAN_STM: - { - ulong wp; - u8 *data = (u8 *) src; - int left; /* number of bytes left to program */ - - wp = addr; - - /* page align, each page is 256 bytes */ - if ((wp % 0x100) != 0) { - left = (0x100 - (wp & 0xFF)); - write_ser_data(info, wp, data, left); - cnt -= left; - wp += left; - data += left; - } - - /* page program - 256 bytes at a time */ - if (cnt > 255) { - count = 0; - while (cnt >= 0x100) { - write_ser_data(info, wp, data, 0x100); - cnt -= 0x100; - wp += 0x100; - data += 0x100; - - if (count++ > 0x400) { - spin_wheel(); - count = 0; - } - } - } - - /* remainint bytes */ - if (cnt && (cnt < 256)) { - write_ser_data(info, wp, data, cnt); - wp += cnt; - data += cnt; - cnt -= cnt; - } - - printf("\b."); - } -#endif - } /* switch */ - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_data_block(flash_info_t * info, ulong src, ulong dest) -{ - FPWV *srcaddr = (FPWV *) src; - FPWV *dstaddr = (FPWV *) dest; - ulong start; - int flag, i; - - /* Check if Flash is (sufficiently) erased */ - for (i = 0; i < WR_BLOCK; i++) - if ((*dstaddr++ & 0xff) != 0xff) { - printf("not erased at %08lx (%lx)\n", - (ulong) dstaddr, *dstaddr); - return (2); - } - - dstaddr = (FPWV *) dest; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */ - - if (flag) - enable_interrupts(); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ - return (1); - } - } - - *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */ - for (i = 0; i < WR_BLOCK; i++) - *dstaddr++ = *srcaddr++; - - dstaddr -= 1; - *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */ - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ - return (1); - } - } - - *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_data(flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = (int)disable_interrupts(); - - *addr = (FPW) INTEL_CLEAR; - *addr = (FPW) INTEL_RESET; - - *addr = (FPW) INTEL_WRSETUP; /* write setup */ - *addr = data; - - if (flag) - enable_interrupts(); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ - *addr = (FPW) INTEL_CLEAR; /* clear status */ - *addr = (FPW) INTEL_RESET; /* reset */ - return (1); - } - } - - *addr = (FPW) INTEL_CLEAR; /* clear status */ - *addr = (FPW) INTEL_RESET; /* restore read mode */ - - return (0); -} - -#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI) -int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt) -{ - ulong start; - int status, i; - u8 flashdata; - - /* Check if Flash is (sufficiently) erased */ - dspi_tx(ser_flash_cs, 0x80, SER_READ); - dspi_tx(ser_flash_cs, 0x80, (dest >> 16) & 0xFF); - dspi_tx(ser_flash_cs, 0x80, (dest >> 8) & 0xFF); - dspi_tx(ser_flash_cs, 0x80, dest & 0xFF); - dspi_rx(); - dspi_rx(); - dspi_rx(); - dspi_rx(); - dspi_tx(ser_flash_cs, 0x80, 0); - flashdata = dspi_rx(); - dspi_tx(ser_flash_cs, 0x00, 0); - dspi_rx(); - - if ((flashdata & *data) != *data) { - printf("not erased at %08lx (%lx)\n", (ulong) dest, - (ulong) flashdata); - return (2); - } - - dspi_tx(ser_flash_cs, 0x00, SER_WREN); - dspi_rx(); - - status = serial_flash_read_status(ser_flash_cs); - if (((status & 0x9C) != 0) && ((status & 0x02) != 0x02)) { - printf("Error Programming\n"); - return 1; - } - - start = get_timer(0); - - dspi_tx(ser_flash_cs, 0x80, SER_PAGE_PROG); - dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF0000) >> 16)); - dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF00) >> 8)); - dspi_tx(ser_flash_cs, 0x80, (dest & 0xFF)); - dspi_rx(); - dspi_rx(); - dspi_rx(); - dspi_rx(); - - for (i = 0; i < (cnt - 1); i++) { - dspi_tx(ser_flash_cs, 0x80, *data); - dspi_rx(); - data++; - } - - dspi_tx(ser_flash_cs, 0x00, *data); - dspi_rx(); - - do { - status = serial_flash_read_status(ser_flash_cs); - - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - } while (status & 0x01); - - return (0); -} -#endif - -/*----------------------------------------------------------------------- - * Write a word to Flash for ATMEL FLASH - * A word is 16 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data) -{ - ulong start; - int flag, i; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile u16 *)dest) & data) != data) { - return (2); - } - - base = (FPWV *) (CFG_ATMEL_BASE); - - for (i = 0; i < sizeof(u16); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (u8) 0x00800080) != - (data & (u8) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (u8) 0x00F000F0; /* reset bank */ - res = 1; - } - } - - *dest++ = (u8) 0x00F000F0; /* reset bank */ - data >>= 8; - } - - return (res); -} - -void inline spin_wheel(void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - *addr = (FPW) INTEL_RESET; /* make sure in read mode */ - *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ - - if (prot) - *addr = (FPW) INTEL_PROTECT; /* lock sector */ - else - *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) INTEL_READID; - - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) INTEL_PROTECT; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) INTEL_PROTECT) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect(info); - break; - - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif -#endif diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 0480b54..3c7b350 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -162,3 +162,53 @@ void pci_init_board(void) pci_mcf5445x_init(&hose); } #endif /* CONFIG_PCI */ + +#if defined(CFG_FLASH_CFI) +#include <flash.h> +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + int i, j, k; + + if (base != CFG_ATMEL_BASE) + return 0; + + info->flash_id = 0x01000000; + info->portwidth = 1; + info->chipwidth = 1; + info->buffer_size = 32; + info->erase_blk_tout = 16384; + info->write_tout = 2; + info->buffer_write_tout = 5; + info->vendor = 2; /* CFI_CMDSET_AMD_STANDARD */ + info->cmd_reset = 0x00F0; + info->interface = FLASH_CFI_X8; + info->legacy_unlock = 0; + info->manufacturer_id = (u16) ATM_MANUFACT; + info->device_id = ATM_ID_LV040; + info->device_id2 = 0; + + info->ext_addr = 0; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0055; + info->addr_unlock1 = 0x00000555; + info->addr_unlock2 = 0x000002AA; + info->name = "CFI conformant"; + + + info->size = 0; + info->sector_count = CFG_ATMEL_TOTALSECT; + info->start[0] = base; + for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { + info->size += sect[i] * sectsz[i]; + + for (j = 0; j < sect[i]; j++, k++) { + info->start[k + 1] = info->start[k] + sectsz[i]; + info->protect[k] = 0; + } + } + + return 1; +} +#endif /* CFG_FLASH_CFI */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 3a022af..82942d0 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -297,9 +297,7 @@ # define CFG_ENV_SECT_SIZE 0x20000 #endif -/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system - keep reset. */ -#undef CFG_FLASH_CFI +#define CFG_FLASH_CFI #ifdef CFG_FLASH_CFI # define CFG_FLASH_CFI_DRIVER 1 @@ -310,50 +308,19 @@ # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ # define CFG_FLASH_CHECKSUM # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } +# define CONFIG_FLASH_CFI_LEGACY -#else - -# define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ - +#ifdef CONFIG_FLASH_CFI_LEGACY # define CFG_ATMEL_REGION 4 # define CFG_ATMEL_TOTALSECT 11 # define CFG_ATMEL_SECT {1, 2, 1, 7} # define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} -# define CFG_INTEL_SECT 137 - -/* max number of sectors on one chip */ -# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT) -# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */ -# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */ -# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ -# define CFG_FLASH_CHECKSUM - -#ifdef CONFIG_SERIAL_FLASH -# define CFG_FLASH2_BASE 0x01000000 -# define CFG_STM_SECT 32 -# define CFG_STM_SECTSZ 0x10000 - -# undef CFG_FLASH_ERASE_TOUT -# define CFG_FLASH_ERASE_TOUT 20000 - -# define SER_WREN 0x06 -# define SER_WRDI 0x04 -# define SER_RDID 0x9F -# define SER_RDSR 0x05 -# define SER_WRSR 0x01 -# define SER_READ 0x03 -# define SER_F_READ 0x0B -# define SER_PAGE_PROG 0x02 -# define SER_SECT_ERASE 0xD8 -# define SER_BULK_ERASE 0xC7 -# define SER_DEEP_PWRDN 0xB9 -# define SER_RES 0xAB #endif - #endif +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#define CFG_FLASH_CHECKSUM + /* * This is setting for JFFS2 support in u-boot. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. -- 1.5.6.4

1 0

[U-Boot] [PATCH] ColdFire: Add M5253DEMO platform support for MCF5253
by Tsi-Chung Liew 12 Aug '08

12 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/freescale/m5253demo/Makefile | 44 +++ board/freescale/m5253demo/config.mk | 25 ++ board/freescale/m5253demo/flash.c | 467 +++++++++++++++++++++++++++++++++ board/freescale/m5253demo/m5253demo.c | 140 ++++++++++ board/freescale/m5253demo/u-boot.lds | 144 ++++++++++ include/configs/M5253DEMO.h | 252 ++++++++++++++++++ 9 files changed, 1077 insertions(+), 0 deletions(-) create mode 100644 board/freescale/m5253demo/Makefile create mode 100644 board/freescale/m5253demo/config.mk create mode 100644 board/freescale/m5253demo/flash.c create mode 100644 board/freescale/m5253demo/m5253demo.c create mode 100644 board/freescale/m5253demo/u-boot.lds create mode 100644 include/configs/M5253DEMO.h diff --git a/MAINTAINERS b/MAINTAINERS index 777d141..10ad5ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -691,6 +691,7 @@ TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> M52277EVB mcf5227x M5235EVB mcf52x2 + M5253DEMO mcf52x2 M5329EVB mcf532x M5373EVB mcf532x M54455EVB mcf5445x diff --git a/MAKEALL b/MAKEALL index ee83cca..535d28a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -691,6 +691,7 @@ LIST_coldfire=" \ M52277EVB \ M5235EVB \ M5249EVB \ + M5253DEMO \ M5253EVBE \ M5271EVB \ M5272C3 \ diff --git a/Makefile b/Makefile index 082b08e..89746a2 100644 --- a/Makefile +++ b/Makefile @@ -1836,6 +1836,9 @@ M5235EVB_Flash32_config: unconfig M5249EVB_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale +M5253DEMO_config : unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253demo freescale + M5253EVBE_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale diff --git a/board/freescale/m5253demo/Makefile b/board/freescale/m5253demo/Makefile new file mode 100644 index 0000000..cf07cf4 --- /dev/null +++ b/board/freescale/m5253demo/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5253demo/config.mk b/board/freescale/m5253demo/config.mk new file mode 100644 index 0000000..fa66b75 --- /dev/null +++ b/board/freescale/m5253demo/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFF800000 diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c new file mode 100644 index 0000000..1bf1e97 --- /dev/null +++ b/board/freescale/m5253demo/flash.c @@ -0,0 +1,467 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <asm/immap.h> + +#ifndef CFG_FLASH_CFI +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x5555 +#define FLASH_CYCLE2 0x2aaa + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int write_word(flash_info_t * info, FPWV * dest, u16 data); +void inline spin_wheel(void); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + ulong size = 0; + ulong fbase = 0; + + fbase = (ulong) CFG_FLASH_BASE; + flash_get_size((FPWV *) fbase, &flash_info[0]); + flash_get_offsets((ulong) fbase, &flash_info[0]); + fbase += flash_info[0].size; + size += flash_info[0].size; + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +int flash_get_offsets(ulong base, flash_info_t * info) +{ + int j, k; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + + info->start[0] = base; + for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) { + info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ; + info->protect[k] = 0; + } + } + + return ERR_OK; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_SST: + printf("SST "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_SST6401B: + printf("SST39VF6401B\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + u16 value; + + addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ + + switch (addr[0] & 0xffff) { + case (u8) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + value = addr[1]; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + + *addr = (FPW) 0x00F000F0; + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u16) SST_ID_xF6401B: + info->flash_id += FLASH_SST6401B; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + info->sector_count = 0; + info->size = 0; + info->sector_count = CFG_SST_SECT; + info->size = CFG_SST_SECT * CFG_SST_SECTSZ; + + /* reset ID mode */ + *addr = (FPWV) 0x00F000F0; + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + return (info->size); +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect, count; + ulong type, start, last; + int rcode = 0, flashtype = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + + switch (type) { + case FLASH_MAN_SST: + flashtype = 1; + break; + default: + type = (info->flash_id & FLASH_VENDMASK); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + flag = disable_interrupts(); + + start = get_timer(0); + last = start; + + if ((s_last - s_first) == (CFG_SST_SECT - 1)) { + if (prot == 0) { + addr = (FPWV *) info->start[0]; + + addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ + addr[FLASH_CYCLE2] = 0x0055; /* unlock */ + addr[FLASH_CYCLE1] = 0x0080; /* erase mode */ + addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ + addr[FLASH_CYCLE2] = 0x0055; /* unlock */ + *addr = 0x0030; /* erase chip */ + + count = 0; + start = get_timer(0); + + while ((*addr & 0x0080) != 0x0080) { + if (count++ > 0x10000) { + spin_wheel(); + count = 0; + } + + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = 0x00F0; /* reset to read mode */ + + return 1; + } + } + + *addr = 0x00F0; /* reset to read mode */ + + printf("\b. done\n"); + + if (flag) + enable_interrupts(); + + return 0; + } else if (prot == CFG_SST_SECT) { + return 1; + } + } + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + addr = (FPWV *) (info->start[sect]); + + printf("."); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + switch (flashtype) { + case 1: + { + FPWV *base; /* first address in bank */ + + flag = disable_interrupts(); + + base = (FPWV *) (CFG_FLASH_BASE); /* First sector */ + + base[FLASH_CYCLE1] = 0x00AA; /* unlock */ + base[FLASH_CYCLE2] = 0x0055; /* unlock */ + base[FLASH_CYCLE1] = 0x0080; /* erase mode */ + base[FLASH_CYCLE1] = 0x00AA; /* unlock */ + base[FLASH_CYCLE2] = 0x0055; /* unlock */ + *addr = 0x0050; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*addr & 0x0080) != 0x0080) { + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = 0x00F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = 0x00F0; /* reset to read mode */ + break; + } + } /* switch (flashtype) */ + } + } + printf(" done\n"); + + if (flag) + enable_interrupts(); + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, count; + u16 data; + int rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + /* get lower word aligned address */ + wp = addr; + port_width = sizeof(FPW); + + /* handle unaligned start bytes */ + if (wp & 1) { + data = *((FPWV *) wp); + data = (data << 8) | *src; + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp++; + cnt -= 1; + src++; + } + + while (cnt >= 2) { + /* + * handle word aligned part + */ + count = 0; + data = *((FPWV *) src); + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp += 2; + src += 2; + cnt -= 2; + + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + /* handle word aligned part */ + if (cnt) { + /* handle word aligned part */ + count = 0; + data = *((FPWV *) wp); + + data = (data & 0x00FF) | (*src << 8); + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp++; + src++; + cnt -= 1; + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + + if (cnt == 0) + return ERR_OK; + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash + * A word is 16 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word(flash_info_t * info, FPWV * dest, u16 data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & (u8) data) != (u8) data) { + return (2); + } + + base = (FPWV *) (CFG_FLASH_BASE); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (u8) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + *dest++ = (u8) 0x00F000F0; /* reset bank */ + + return (res); +} + +void inline spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +#endif diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c new file mode 100644 index 0000000..2eb6a04 --- /dev/null +++ b/board/freescale/m5253demo/m5253demo.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/immap.h> + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale MCF5253 DEMO\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + u32 dramsize = 0; + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { + u32 RC, temp; + + RC = (CFG_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); + __asm__("nop"); + + mbar_writeLong(MCFSIM_DACR0, 0x00003224); + __asm__("nop"); + + /* Initialize DMR0 */ + dramsize = (CFG_SDRAM_SIZE << 20); + temp = (dramsize - 1) & 0xFFFC0000; + mbar_writeLong(MCFSIM_DMR0, temp | 1); + __asm__("nop"); + + mbar_writeLong(MCFSIM_DACR0, 0x0000322c); + __asm__("nop"); + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; + __asm__("nop"); + + /* Set RE bit in DACR */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x8000); + __asm__("nop"); + + /* Wait for at least 8 auto refresh cycles to occur */ + udelay(500); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x0040); + __asm__("nop"); + + *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + } + + return dramsize; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CONFIG_CMD_IDE +#include <ata.h> +int ide_preinit(void) +{ + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ + }; + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(100); + } else { + mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); + +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / (CFG_CLK / 2); /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(2000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif /* CONFIG_CMD_IDE */ diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds new file mode 100644 index 0000000..4bdea5e --- /dev/null +++ b/board/freescale/m5253demo/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h new file mode 100644 index 0000000..b91d7d6 --- /dev/null +++ b/include/configs/M5253DEMO.h @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _M5253DEMO_H +#define _M5253DEMO_H + +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5253 /* define processor type */ +#define CONFIG_M5253DEMO /* define board type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG /* disable watchdog */ + +#define CONFIG_BOOTDELAY 5 + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +# define CFG_ENV_OFFSET 0x4000 +# define CFG_ENV_SECT_SIZE 0x1000 +# define CFG_ENV_IS_IN_FLASH 1 +#else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) +# define CFG_ENV_SECT_SIZE 0x1000 +# define CFG_ENV_IS_IN_FLASH 1 +#endif + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_PING + +#ifdef CONFIG_CMD_IDE +/* ATA */ +# define CONFIG_DOS_PARTITION +# define CONFIG_MAC_PARTITION +# define CONFIG_IDE_RESET 1 +# define CONFIG_IDE_PREINIT 1 +# define CONFIG_ATAPI +# undef CONFIG_LBA48 + +# define CFG_IDE_MAXBUS 1 +# define CFG_IDE_MAXDEVICE 2 + +# define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800) +# define CFG_ATA_IDE0_OFFSET 0 + +# define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +# define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +# define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +# define CFG_ATA_STRIDE 4 /* Interval between registers */ +# define _IO_BASE 0 +#endif + +#define CONFIG_DRIVER_DM9000 +#ifdef CONFIG_DRIVER_DM9000 +# define CONFIG_DM9000_BASE ((CFG_CSAR1 << 16) | 0x300) +# define DM9000_IO CONFIG_DM9000_BASE +# define DM9000_DATA (CONFIG_DM9000_BASE + 4) +# undef CONFIG_DM9000_DEBUG + +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 10.82.121.249 +# define CONFIG_NETMASK 255.255.252.0 +# define CONFIG_SERVERIP 10.82.120.80 +# define CONFIG_GATEWAYIP 10.82.123.254 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +# define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" +#endif + +#define CONFIG_HOSTNAME M5253DEMO + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK +#ifdef CFG_FAST_CLK +# define CFG_PLLCR 0x1243E054 +# define CFG_CLK 140000000 +#else +# define CFG_PLLCR 0x135a4140 +# define CFG_CLK 70000000 +#endif + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */ + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#ifdef CONFIG_MONITOR_IS_IN_RAM +# define CFG_MONITOR_BASE 0x20000 +#else +# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif + +#define CFG_MONITOR_LEN 0x40000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN (64*1024) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CFG_FLASH_BASE (CFG_CSAR0 << 16) +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 + +#define FLASH_SST6401B 0x200 +#define SST_ID_xF6401B 0x236D236D + +#undef CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +/* + * Unable to use CFI driver, due to incompatible sector erase command by SST. + * Amd/Atmel use 0x30 for sector erase, SST use 0x50. + * 0x30 is block erase in SST + */ +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_FLASH_CFI_LEGACY +#else +# define CFG_SST_SECT 2048 +# define CFG_SST_SECTSZ 0x1000 +# define CFG_FLASH_WRITE_TOUT 500 +#endif + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 16 + +/* Port configuration */ +#define CFG_FECI2C 0xF0 + +#define CFG_CSAR0 0xFF80 +#define CFG_CSMR0 0x007F0021 +#define CFG_CSCR0 0x1D80 + +#define CFG_CSAR1 0xE000 +#define CFG_CSMR1 0x00000001 +#define CFG_CSCR1 0x3DD8 + +#define CFG_CSAR2 0 +#define CFG_CSMR2 0 +#define CFG_CSCR2 0 + +#define CFG_CSAR3 0 +#define CFG_CSMR3 0 +#define CFG_CSCR3 0 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +#endif /* _M5253DEMO_H */ -- 1.5.6.4

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